[llvm] [AMDGPU][True16][CodeGen] srl pattern for true16 mode (PR #132987)

[Matt Arsenault via llvm-commits]

================
@@ -2425,6 +2425,13 @@ def : GCNPat <(i1 imm:$imm),
   let WaveSizePredicate = isWave32;
 }
 
+let True16Predicate = UseRealTrue16Insts in
+foreach vt = [i32, v2i16] in
----------------
arsenm wrote:

I don't see how this pattern makes sense for the v2i16 case 

https://github.com/llvm/llvm-project/pull/132987