[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)
Mallikarjuna Gouda via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 27 00:23:20 PDT 2025
================
@@ -0,0 +1,452 @@
+//==- MipsScheduleI6400.td - I6400 Scheduling Definitions --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+def MipsI6400Model : SchedMachineModel {
+ int IssueWidth = 2; // 2x dispatched per cycle
+ int MicroOpBufferSize = 48; // min(48, 48, 64)
+ int LoadLatency = 3;
+ int MispredictPenalty = 8;
+
+ let CompleteModel = 1;
+ let FullInstRWOverlapCheck = 1;
+
+ list<Predicate> UnsupportedFeatures = [HasMips64r5, HasMips32r5,
+ InMicroMips, InMips16Mode, HasCnMips,
+ HasCnMipsP, HasDSP, HasDSPR2,
+ HasMips3D, HasMT, HasCRC,
+ NotMips32r6, NotMips64r6, HasEVA];
+}
+
+let SchedModel = MipsI6400Model in {
+
+ // AGEN Pipelines
+ // ==============
+ def I6400AGEN : ProcResource<1> { let BufferSize = 16; }
+ def I6400IssueLSU : ProcResource<1> { let Super = I6400AGEN; }
+ def I6400IssueALU1 : ProcResource<1> { let Super = I6400AGEN; }
+
+ def I6400WriteLSUStore : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
+ def I6400WriteLSUStore2 : SchedWriteRes<[I6400IssueLSU]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [5];
+ }
+ def I6400WriteLSULoad : SchedWriteRes<[I6400IssueLSU]> { let Latency = 3; }
+ def I6400WriteLSUPref : SchedWriteRes<[I6400IssueLSU]> { let Latency = 1; }
+ def I6400WriteLSUOther : SchedWriteRes<[I6400IssueLSU]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [5];
+ }
+
+ // LSU pipelines
+ // =============
+ def : InstRW<[I6400WriteLSUStore], (instrs SB, SD, SH, SW, SDC1, SDC164, SWC1, SWC2_R6,
+ SDC2_R6, SDC3)>;
+ def : InstRW<[I6400WriteLSUStore2], (instrs SC_R6, SCD_R6, SYNCI, TLBP, TLBR,
+ TLBWI, TLBWR, TLBINV, TLBINVF,
+ CACHE_R6, SC64_R6)>;
+ def : InstRW<[I6400WriteLSULoad],
+ (instrs LB, LBu, LBu64, LD, LH, LHu, LHu64, LW, LWu, LDC1,
+ LDC164, LWC1, LD_F16, ST_F16, LDC2_R6, LDC3, LWC2_R6,
+ LLD_R6, LL_R6, LWPC, LWUPC, LDPC, ST_B, ST_H, ST_W, ST_D,
+ LB64, LH64, LW64, LWL64, LWR64, SB64, SH64, SW64, SWL64,
+ SWR64, LL64_R6)>;
+ def : InstRW<[I6400WriteLSUPref], (instrs PREF, PREF_R6, PAUSE)>;
+ def : InstRW<[I6400WriteLSUOther], (instrs SYNC)>;
+
+ // CONTROL Pipelines
+ // =================
+ def I6400CTRL : ProcResource<1> { let BufferSize = 16; }
+ def I6400IssueCTU : ProcResource<1> { let Super = I6400CTRL; }
+ def I6400IssueALU0 : ProcResource<1> { let Super = I6400CTRL; }
+
+ def I6400WriteALU0 : SchedWriteRes<[I6400IssueALU0]> { let Latency = 1; }
+ def I6400WriteALU1 : SchedWriteRes<[I6400IssueALU1]> { let Latency = 1; }
+ def I6400WriteCTU : SchedWriteRes<[I6400IssueCTU]> { let Latency = 1; }
+
+ // CTU pipelines
+ // =============
+ def : InstRW<[I6400WriteCTU],
+ (instrs J, JAL, JALR, B, BEQ, BNE, BGEZ, BGTZ, BLEZ, BLTZ,
+ JALR64, JALR64Pseudo, JIALC, JIALC64, JIC, JIC64, JR64,
+ JR_HB_R6,
+ JR_HB64_R6, NAL, SDBBP_R6, SYSCALL, BEQC64, BEQZC64, BGEC64,
+ BGEUC64, BGTZC64, BLEZC64, BLTC64, BLTUC64, BNEC64, BNEZC64,
+ PseudoIndirectBranchR6, BC, BALC, BEQZC, BNEZC, BLEZC, BGEZC,
+ BGTZC, BLTZC, BEQZALC, BNEZALC, BLEZALC, BGEZALC, BGTZALC,
+ BLTZALC, BEQC, BNEC, BGEC, BLTC, BGEUC, BLTUC, BAL, BOVC,
+ BNVC, BC1EQZ, BC1NEZ, BREAK, ERET, ERETNC, BAL_BR, DERET,
+ JALRHBPseudo, JALRPseudo, JALR_HB, JALR_HB64, TAILCALL,
+ PseudoIndirectBranch64R6, TAILCALL64R6REG,
+ TAILCALLR6REG, PseudoIndrectHazardBranch64R6,
+ PseudoIndrectHazardBranchR6, TAILCALLHB64R6REG,
+ TAILCALLHBR6REG, PseudoReturn, PseudoReturn64, ERet, RetRA,
+ BC2EQZ, BC2NEZ, TLT, TLTU, TNE, WAIT, DI, TRAP, EI,
+ BEQ64, BGEZ64, BGEZC64, BGTZ64, BGTZ64, BLEZ64, BLTZ64,
+ BLTZC64, BNE64, JALRHB64Pseudo)>;
+
+ // Either ALU0 or ALU1 pipelines
+ // =============================
+ def I6400IssueEitherALU : ProcResGroup<[I6400IssueALU0, I6400IssueALU1]>;
+ def I6400WriteEitherALU : SchedWriteRes<[I6400IssueEitherALU]> {
+ let Latency = 1;
+ }
+
+ def : InstRW<[I6400WriteEitherALU],
+ (instrs ADD, ADDiu, ADDIUPC, ADDu, ALIGN, ALUIPC, AND, ANDi, AUI,
+ AUIPC, BITSWAP, CFC1, CLO_R6, CLZ_R6, CTC1, DADD, DADDiu,
+ DADDu, DAHI, DALIGN, DATI, DAUI, DBITSWAP, DCLO_R6, DCLZ_R6,
+ DEXT, DEXT64_32, DEXTM, DEXTU, DINS, DINSM, DINSU, DLSA_R6,
+ DMFC1, DMTC1, DROTR, DROTR32, DROTRV, DSBH, DSHD, DSLL,
+ DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV,
+ DSUB, DSUBu, EXT, INS, LSA, LSA_R6, LUi, MFC1, MFC1_D64,
+ MFC0, MFC2, MTC0, MTC2,
+ MFHC1_D32, MFHC1_D64, MTC1, MTC1_D64, MTHC1_D32, MTHC1_D64,
+ NOP, NOR, OR, ORi, ROTR, ROTRV, SEB, SEB64, SEH, SEH64,
+ SELEQZ, SELEQZ64, SELNEZ, SELNEZ64, SLL, SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV,
+ SRL, SRLV, SSNOP, SUB, SUBu, WSBH, XOR, XORi, SLT64, SLTu64,
+ AND64, OR64, XOR64, NOR64, SLTi64, SLTiu64, ANDi64, ORi64,
+ XORi64, LUi64, DSLL64_32, SLL64_32, SLL64_64,
+ LONG_BRANCH_LUi2Op_64, LONG_BRANCH_DADDiu2Op,
+ LONG_BRANCH_DADDiu, DLSA,
+ TEQ, TGE, TGEU, COPY,
+ BuildPairF64, BuildPairF64_64,
+ ExtractElementF64, ExtractElementF64_64,
+ SELNEZ_D, SELNEZ_S, SELEQZ_D, SELEQZ_S,
+ SEL_D, SEL_S, EHB, RDHWR, RDHWR64, EVP, DVP,
+ DMFC0, DMFC2, DMTC0, DMTC2)>;
+
+ // MDU pipelines
+ // =============
+ def I6400MDU : ProcResource<1>;
+ def I6400GPMUL : SchedWriteRes<[I6400MDU]> { let Latency = 4; }
+ def : InstRW<[I6400GPMUL], (instrs MUL_R6, MULU, MUH, MUHU, DMUL_R6, DMUH,
+ DMULU, DMUHU)>;
+
+ def I6400GPDIV : SchedWriteRes<[I6400MDU]> { let Latency = 32; }
+ def : InstRW<[I6400GPDIV], (instrs DIV, DIVU, MOD, MODU, DDIV, DMOD, DDIVU,
+ DMODU)>;
+ def : InstRW<[I6400GPDIV], (instregex "^MOD_(S|U)_[BHWD]$")>;
+
+ // FPU pipelines
+ // =============
+ def I6400FPU : ProcResource<3> { let BufferSize = 16; }
----------------
mgoudar wrote:
initialized BufferSize for all resources to 0 as cpu is in-order core.
https://github.com/llvm/llvm-project/pull/132704
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