[llvm] [RISCV] Reverse the order of Base and Offset in Core-V RegReg operand. (PR #133209)
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Wed Mar 26 22:36:20 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
This puts the base before the offset to match the order we use for base ISA where the offset is an immediate.
I'm investigating using sub-operands for the base ISA loads and stores too so having a consistent operand order will allow more sharing.
---
Full diff: https://github.com/llvm/llvm-project/pull/133209.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+7-7)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+6-6)
- (modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td (+3-3)
``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index ef260abb3faa7..02cb1b5c9a12b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2768,9 +2768,9 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Identifier)
return ParseStatus::NoMatch;
- StringRef RegName = getLexer().getTok().getIdentifier();
- MCRegister Reg = matchRegisterNameHelper(RegName);
- if (!Reg)
+ StringRef OffsetRegName = getLexer().getTok().getIdentifier();
+ MCRegister OffsetReg = matchRegisterNameHelper(OffsetRegName);
+ if (!OffsetReg)
return Error(getLoc(), "invalid register");
getLexer().Lex();
@@ -2780,16 +2780,16 @@ ParseStatus RISCVAsmParser::parseRegReg(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Identifier)
return Error(getLoc(), "expected register");
- StringRef Reg2Name = getLexer().getTok().getIdentifier();
- MCRegister Reg2 = matchRegisterNameHelper(Reg2Name);
- if (!Reg2)
+ StringRef BaseRegName = getLexer().getTok().getIdentifier();
+ MCRegister BaseReg = matchRegisterNameHelper(BaseRegName);
+ if (!BaseReg)
return Error(getLoc(), "invalid register");
getLexer().Lex();
if (parseToken(AsmToken::RParen, "expected ')'"))
return ParseStatus::Failure;
- Operands.push_back(RISCVOperand::createRegReg(Reg, Reg2, getLoc()));
+ Operands.push_back(RISCVOperand::createRegReg(BaseReg, OffsetReg, getLoc()));
return ParseStatus::Success;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index a4a40862a67c6..cd2322cc5b26d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -262,15 +262,15 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
- const MCOperand &MO = MI->getOperand(OpNo);
+ const MCOperand &OffsetMO = MI->getOperand(OpNo + 1);
- assert(MO.isReg() && "printRegReg can only print register operands");
- printRegName(O, MO.getReg());
+ assert(OffsetMO.isReg() && "printRegReg can only print register operands");
+ printRegName(O, OffsetMO.getReg());
O << "(";
- const MCOperand &MO1 = MI->getOperand(OpNo + 1);
- assert(MO1.isReg() && "printRegReg can only print register operands");
- printRegName(O, MO1.getReg());
+ const MCOperand &BaseMO = MI->getOperand(OpNo);
+ assert(BaseMO.isReg() && "printRegReg can only print register operands");
+ printRegName(O, BaseMO.getReg());
O << ")";
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 8aa684c56bde0..0268d4f34480d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2853,8 +2853,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegReg(SDValue Addr, SDValue &Base,
if (isa<ConstantSDNode>(Addr.getOperand(1)))
return false;
- Base = Addr.getOperand(1);
- Offset = Addr.getOperand(0);
+ Base = Addr.getOperand(0);
+ Offset = Addr.getOperand(1);
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 9ab7e1ca2936c..c14f8bb9fe41c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -25,7 +25,7 @@ def CVrr : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {
let ParserMatchClass = CVrrAsmOperand;
let PrintMethod = "printRegReg";
- let MIOperandInfo = (ops GPR:$offset, GPR:$base);
+ let MIOperandInfo = (ops GPR:$base, GPR:$offset);
}
def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
@@ -287,7 +287,7 @@ class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
- (ins (CVrr $rs2, $rs1):$addr),
+ (ins (CVrr $rs1, $rs2):$addr),
opcodestr, "$rd, $addr">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
@@ -317,7 +317,7 @@ class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>
class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
- : RVInst<(outs), (ins GPR:$rs2, (CVrr $rs3, $rs1):$addr), opcodestr,
+ : RVInst<(outs), (ins GPR:$rs2, (CVrr $rs1, $rs3):$addr), opcodestr,
"$rs2, $addr", [], InstFormatOther> {
bits<5> rs1;
bits<5> rs2;
``````````
</details>
https://github.com/llvm/llvm-project/pull/133209
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