[llvm] [RISCV] Have GPRMem on the correct operand in QCIRVInstESStore (PR #133042)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/133042

>From 620d3fb7c7de409704ccfbf072ae266c7688ea28 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Wed, 26 Mar 2025 12:14:06 +0530
Subject: [PATCH] [RISCV] Have GPRMem on the correct operand in
 QCIRVInstESStore

It should be on rs1 and not rs2.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 69290c0da1824..86c521010add4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -442,7 +442,7 @@ class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
     : QCIRVInstESBase<funct3, funct2, (outs),
-                      (ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
+                      (ins GPR:$rs2, GPRMem:$rs1, simm26:$imm),
                       opcodestr, "$rs2, ${imm}(${rs1})">;
 
 class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>