[llvm] [RISCV] Set mayRaiseFPException = 0 on FCVT_D_W(U). (PR #133200)
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Wed Mar 26 20:19:42 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
Fixes #<!-- -->133192.
---
Full diff: https://github.com/llvm/llvm-project/pull/133200.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoD.td (+6-4)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/double-imm.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/frm-dependency.ll (+5-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 5a0adeadf35f7..01f6c4db0598b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -144,12 +144,14 @@ foreach Ext = DExts in {
"fcvt.wu.d">,
Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
- defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext, Ext.PrimaryTy, GPR,
- "fcvt.d.w">,
+ let mayRaiseFPException = 0 in
+ defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext,
+ Ext.PrimaryTy, GPR, "fcvt.d.w">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
- defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext, Ext.PrimaryTy, GPR,
- "fcvt.d.wu">,
+ let mayRaiseFPException = 0 in
+ defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext,
+ Ext.PrimaryTy, GPR, "fcvt.d.wu">,
Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>;
} // foreach Ext = DExts
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir
index d87a44d9c9a50..7200fe1b7e448 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv32.mir
@@ -59,7 +59,7 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_W [[COPY]], 0
+ ; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s32) = COPY $x10
@@ -81,7 +81,7 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_WU [[COPY]], 0
+ ; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = FCVT_D_WU [[COPY]], 0
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s32) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll
index 155827ad069cc..5350a28005738 100644
--- a/llvm/test/CodeGen/RISCV/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/double-imm.ll
@@ -123,9 +123,9 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
; CHECK32D-LABEL: negzero_sel:
; CHECK32D: # %bb.0: # %entry
; CHECK32D-NEXT: slli a0, a0, 16
-; CHECK32D-NEXT: fcvt.d.w fa5, zero
; CHECK32D-NEXT: beqz a0, .LBB4_2
; CHECK32D-NEXT: # %bb.1: # %entry
+; CHECK32D-NEXT: fcvt.d.w fa5, zero
; CHECK32D-NEXT: fneg.d fa0, fa5
; CHECK32D-NEXT: .LBB4_2: # %entry
; CHECK32D-NEXT: ret
@@ -143,10 +143,10 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
; CHECKRV32ZDINX-LABEL: negzero_sel:
; CHECKRV32ZDINX: # %bb.0: # %entry
; CHECKRV32ZDINX-NEXT: slli a0, a0, 16
-; CHECKRV32ZDINX-NEXT: fcvt.d.w a4, zero
; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2
; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
-; CHECKRV32ZDINX-NEXT: fneg.d a2, a4
+; CHECKRV32ZDINX-NEXT: fcvt.d.w a0, zero
+; CHECKRV32ZDINX-NEXT: fneg.d a2, a0
; CHECKRV32ZDINX-NEXT: j .LBB4_3
; CHECKRV32ZDINX-NEXT: .LBB4_2:
; CHECKRV32ZDINX-NEXT: mv a3, a2
diff --git a/llvm/test/CodeGen/RISCV/frm-dependency.ll b/llvm/test/CodeGen/RISCV/frm-dependency.ll
index b0cc1946bc983..a596c34ef9123 100644
--- a/llvm/test/CodeGen/RISCV/frm-dependency.ll
+++ b/llvm/test/CodeGen/RISCV/frm-dependency.ll
@@ -87,16 +87,17 @@ define double @fcvt_d_w(i32 %a) nounwind {
; RV32IF-NEXT: liveins: $x10
; RV32IF-NEXT: {{ $}}
; RV32IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV32IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]]
- ; RV32IF-NEXT: $f10_d = COPY %1
+ ; RV32IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
+ ; RV32IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
; RV32IF-NEXT: PseudoRET implicit $f10_d
+ ;
; RV64IF-LABEL: name: fcvt_d_w
; RV64IF: bb.0 (%ir-block.0):
; RV64IF-NEXT: liveins: $x10
; RV64IF-NEXT: {{ $}}
; RV64IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; RV64IF-NEXT: %1:fpr64 = nofpexcept FCVT_D_W [[COPY]]
- ; RV64IF-NEXT: $f10_d = COPY %1
+ ; RV64IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
+ ; RV64IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
; RV64IF-NEXT: PseudoRET implicit $f10_d
%1 = sitofp i32 %a to double
ret double %1
``````````
</details>
https://github.com/llvm/llvm-project/pull/133200
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