[llvm] Add RISC-V support information to readme (PR #132699)

[Min-Yih Hsu via llvm-commits]

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@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISC-V
+  * Supported extensions: M, A, F, C, B, initial V.
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mshockwave wrote:

Reading this part again, I don't think we explicitly exclude any extensions, right? It's usually technical shortfalls that limit the kind of instructions we can measure / generate (e.g. we still can't measure memory instructions in RVV). So perhaps we can rephrase this part of the description.

https://github.com/llvm/llvm-project/pull/132699