[llvm] [RISCV] Update the latency of floating point load in SiFive P500 scheduling model (PR #133165)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 26 14:16:59 PDT 2025
https://github.com/mshockwave created https://github.com/llvm/llvm-project/pull/133165
P500-series cores should have a floating point load latency closer to 5 cycles, just like P400- and P600-series cores.
>From 68d1d13495a9c7491f04c4a2dfbed0842b793fe9 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Wed, 26 Mar 2025 13:50:58 -0700
Subject: [PATCH] [RISCV] Update the latency of floating point load in SiFive
P500 scheduling model
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 2 +-
llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
index 32cfa701c4fdb..ca116e0c54f3f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td
@@ -132,7 +132,7 @@ def : WriteRes<WriteLDW, [SiFiveP500Load]>;
def : WriteRes<WriteLDD, [SiFiveP500Load]>;
}
-let Latency = 6 in {
+let Latency = 5 in {
def : WriteRes<WriteFLD16, [SiFiveP500Load]>;
def : WriteRes<WriteFLD32, [SiFiveP500Load]>;
def : WriteRes<WriteFLD64, [SiFiveP500Load]>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s
index 2b7df9215e0cb..133d7ce4d626d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP500/load.s
@@ -9,12 +9,12 @@ fld ft0, 0(a0)
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
-# CHECK-NEXT: Total Cycles: 12
+# CHECK-NEXT: Total Cycles: 11
# CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 3
-# CHECK-NEXT: uOps Per Cycle: 0.33
-# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: uOps Per Cycle: 0.36
+# CHECK-NEXT: IPC: 0.36
# CHECK-NEXT: Block RThroughput: 4.0
# CHECK: Instruction Info:
@@ -28,8 +28,8 @@ fld ft0, 0(a0)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 1.00 * lw t0, 0(a0)
# CHECK-NEXT: 1 4 1.00 * ld t0, 0(a0)
-# CHECK-NEXT: 1 6 1.00 * flw ft0, 0(a0)
-# CHECK-NEXT: 1 6 1.00 * fld ft0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * flw ft0, 0(a0)
+# CHECK-NEXT: 1 5 1.00 * fld ft0, 0(a0)
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP500Div
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