[llvm] [RISCV] Add Xqci Insn Formats (PR #132986)

[Sam Elliott via llvm-commits]

================
@@ -130,6 +132,219 @@ def simm32_lsb0 : Operand<OtherVT> {
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
+
+class DirectiveInsnQC_EAI<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EAI> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<1> func1;
+
+  bits<5> rd;
+  bits<32> imm32;
+
+  let Inst{47-16} = imm32;
+  let Inst{15}    = func1;
+  let Inst{14-12} = func3;
+  let Inst{11-7}  = rd;
+  let Inst{6-0}   = opcode;
+
+  let AsmString = ".insn qc.eai " # argstr;
+}
+
+class DirectiveInsnQC_EI<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EI> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<2> func2;
+
+  bits<5> rd;
+  bits<5> rs1;
+  bits<26> imm26;
+
+  let Inst{47-32} = imm26{25-10};
+  let Inst{31-30} = func2;
+  let Inst{29-20} = imm26{9-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = func3;
+  let Inst{11-7}  = rd;
+  let Inst{6-0}   = opcode;
+
+  let AsmString = ".insn qc.ei " # argstr;
+}
+
+class DirectiveInsnQC_EB<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EB> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<5> func5;
+
+  bits<5> rs1;
+  bits<12> imm12; // This one is the PC-relative offset
+  bits<16> imm16;
+
+  let Inst{47-32} = imm16;
----------------
lenary wrote:

The intention not to honour the "nonzero" bit of the 16-bit immediate is on purpose - the formats don't put these restrictions in, only individual instructions do.

As for the uimm16/simm16 difference, I'm not sure how to deal with this, but I want to punt on it, as users should be able to convert any unsigned immediates to the equivalent signed 16-bit immediate in their own assembly code, which would be accepted, and would give the expected bit pattern.

This is broadly a limitation of the instruction format idea in practice, especially when architects think of the fields as "just N bits" and push the sign/zero extension into the operation of different instructions.

https://github.com/llvm/llvm-project/pull/132986