[llvm] [TableGen][RISCV] Support sub-operands in CompressInstEmitter.cpp. (PR #133039)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,126 @@
+// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../../include %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+def ArchAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+  let AssemblyWriters = [ArchAsmWriter];
+}
+
+def Reg0 : Register<"reg0"> {
+  let HWEncoding{4-0} = 0;
+}
+def Reg1 : Register<"reg1"> {
+  let HWEncoding{4-0} = 1;
+}
+
+def Regs : RegisterClass<"Arch", [i32], 32, (add Reg0, Reg1)>;
+def RegsC : RegisterClass<"Arch", [i32], 32, (sub Regs, Reg0)>;
+
+def simm6 : Operand<i32>, ImmLeaf<i32, [{return isInt<6>(Imm);}]> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isInt<6>(Imm);
+  }];
+}
+
+def simm12 : Operand<i32>, ImmLeaf<i32, [{return isInt<12>(Imm);}]> {
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isInt<12>(Imm);
+  }];
+}
+
+def MemOpnd : Operand<iPTR> {
+  let MIOperandInfo = (ops Regs, simm12);
+}
+
+def MemOpndC : Operand<iPTR> {
+  let MIOperandInfo = (ops RegsC, simm6);
+}
+
+def BigInst : Instruction {
+  let Namespace = "MyNS";
+  let OutOperandList = (outs Regs:$dst);
+  let InOperandList = (ins MemOpnd:$addr);
+  let Size = 4;
+  let AsmString = "big $dst, $addr";
+}
+
+def SmallInst : Instruction {
+  let Namespace = "MyNS";
+  let OutOperandList = (outs RegsC:$dst);
+  let InOperandList = (ins MemOpndC:$addr);
+  let Size = 2;
+  let AsmString = "small $dst, $addr";
+}
+
+def : CompressPat<(BigInst RegsC:$dst, RegsC:$rs, simm6:$imm),
+                  (SmallInst RegsC:$dst, RegsC:$rs, simm6:$imm)>;
+
+// CHECK-LABEL: ArchValidateMCOperandForCompress
+// CHECK: // simm6
+// CHECK: return isInt<6>(Imm);
+
+// CHECK-LABEL: compressInst
+// CHECK: case Arch::BigInst
+// CHECK-NEXT: if (MI.getOperand(0).isReg() &&
+// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(0).getReg()) &&
+// CHECK-NEXT: MI.getOperand(1).isReg() &&
+// CHECK-NEXT: ArchMCRegisterClasses[Arch::RegsCRegClassID].contains(MI.getOperand(1).getReg()) &&
+// CHECK-NEXT: ArchValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) {
+// CHECK-NEXT: // small $dst, $addr
+// CHECK-NEXT: OutInst.setOpcode(Arch::SmallInst);
+// CHECK-NEXT: // Operand: dst
+// CHECK-NEXT: OutInst.addOperand(MI.getOperand(0));
+// CHECK-NEXT: // Operand: addr
+// CHECK-NEXT: OutInst.addOperand(MI.getOperand(1));
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topperc wrote:

Here you can see that one named operand from the instruction has multiple addOperand calls for the sub-operands

https://github.com/llvm/llvm-project/pull/133039