[llvm] [RISCV] Support .option {no}exact (PR #122483)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 26 09:02:35 PDT 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/122483
>From 8d8ed46fbeec95c2840c612f64dbc65fb98b3f8f Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Fri, 10 Jan 2025 08:02:07 -0800
Subject: [PATCH 01/15] [RISCV] Support .option (no)autocompress
This is the implementation of a new assembler-only option to allow the
automatic compression of RISC-V instructions to be switched off without
changing the currently enabled architectural features.
This allows users better control over the autocompression feature of the
assembler, so they can get the exact instructions they want.
This will become more useful as the following things happen:
- `.option norvc` is deprecated/removed (which is sometimes used for
this purpose).
- Extensions are added where the destination instruction cannot be
disabled separately to the source instruction, either because the
destination is in the base architecture, or because it is in the same
extension as the source.
- Extensions wider than 32-bits are added, which make CompressPats more
complex to use intuitively, especially if the destination is a 32-bit
instruction.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 28 +++++++-
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 2 +
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 2 +
.../MCTargetDesc/RISCVTargetStreamer.cpp | 10 +++
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 4 ++
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++
llvm/test/MC/RISCV/option-autocompress.s | 70 +++++++++++++++++++
8 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/RISCV/option-autocompress.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 2205c67c2d21b..18794ed3b7fbf 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3064,6 +3064,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionRVC();
setFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3074,6 +3076,28 @@ bool RISCVAsmParser::parseDirectiveOption() {
getTargetStreamer().emitDirectiveOptionNoRVC();
clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "autocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionAutoCompress();
+ clearFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
+ return false;
+ }
+
+ if (Option == "noautocompress") {
+ if (Parser.parseEOL())
+ return true;
+
+ getTargetStreamer().emitDirectiveOptionNoAutoCompress();
+ setFeatureBits(RISCV::FeatureDisableAsmCompression,
+ "disable-asm-compression");
return false;
}
@@ -3326,7 +3350,9 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ bool Res = false;
+ if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, getSTI());
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction((Res ? CInst : Inst), getSTI());
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index ea0e9fcde21cf..218e0078999f3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,6 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index 47df31af3057d..33acf5828f9f4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,6 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 99f57f47835ab..1e33633d1169b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,6 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -122,6 +124,14 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
+void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
+ OS << "\t.option\tautocompress\n";
+}
+
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
+ OS << "\t.option\tnoautocompress\n";
+}
+
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
OS << "\t.option\trelax\n";
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index cb8bc21cb6355..33ab55ca85536 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,6 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
+ virtual void emitDirectiveOptionAutoCompress();
+ virtual void emitDirectiveOptionNoAutoCompress();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -84,6 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionAutoCompress() override;
+ void emitDirectiveOptionNoAutoCompress() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index b1990409754b0..d5de046b96053 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -254,7 +254,9 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
- bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
+ bool Res = false;
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+ Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 01bc5387e672e..a4bf4f92de27f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1326,6 +1326,10 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
+def FeatureDisableAsmCompression
+ : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
+ "Disable Automatic Assembly Compression.">;
+
foreach i = {1-31} in
def FeatureReserveX#i :
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
new file mode 100644
index 0000000000000..ac58a4320b259
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
+# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+
+
+# `.option (no)autocompress` enables and disables instruction compression in the
+# assembler, without changing the current architecture.
+#
+# The default is as if `.option autocompress` has been specified, that is, the
+# assembler compresses by default.
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option noautocompress
+.option noautocompress
+
+# CHECK-BYTES: 00052503
+# CHECK-INST: lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x03,0x25,0x05,0x00]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
+# CHECK: .option autocompress
+.option autocompress
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-BYTES: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ALIAS: lw a0, 0(a0)
+# CHECK: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
>From eba37b26f3bb88548ffcf428240c11c2370b2eae Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Mon, 13 Jan 2025 05:44:53 -0800
Subject: [PATCH 02/15] fixup! [RISCV] Support .option (no)autocompress
---
llvm/test/MC/RISCV/option-autocompress.s | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-autocompress.s
index ac58a4320b259..d394f69af0b8a 100644
--- a/llvm/test/MC/RISCV/option-autocompress.s
+++ b/llvm/test/MC/RISCV/option-autocompress.s
@@ -1,22 +1,22 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c %s \
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
-# RUN: -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c < %s \
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
>From c70f679f3285a20b929906e78b3ab31e0a6caadb Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 13:51:43 -0700
Subject: [PATCH 03/15] Update implementation to match proposal
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 47 ++++++------
.../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 10 +++
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 4 +-
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 4 +-
.../MCTargetDesc/RISCVTargetStreamer.cpp | 12 +--
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 8 +-
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +-
...ocompress.s => option-exact-compression.s} | 20 ++---
llvm/test/MC/RISCV/option-exact-relaxation.s | 74 +++++++++++++++++++
10 files changed, 136 insertions(+), 51 deletions(-)
rename llvm/test/MC/RISCV/{option-autocompress.s => option-exact-compression.s} (82%)
create mode 100644 llvm/test/MC/RISCV/option-exact-relaxation.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4989368663b48..a7c2f563536ef 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3173,46 +3173,44 @@ bool RISCVAsmParser::parseDirectiveOption() {
return false;
}
- if (Option == "rvc") {
+ if (Option == "exact") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionRVC();
- setFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionExact();
+ setFeatureBits(RISCV::FeatureExactAssembly,
+ "exact-asm");
+ clearFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
- if (Option == "norvc") {
+ if (Option == "noexact") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionNoRVC();
- clearFeatureBits(RISCV::FeatureStdExtC, "c");
- clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
- setFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionNoExact();
+ clearFeatureBits(RISCV::FeatureExactAssembly,
+ "exact-asm");
+ setFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
- if (Option == "autocompress") {
+ if (Option == "rvc") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionAutoCompress();
- clearFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionRVC();
+ setFeatureBits(RISCV::FeatureStdExtC, "c");
return false;
}
- if (Option == "noautocompress") {
+ if (Option == "norvc") {
if (Parser.parseEOL())
return true;
- getTargetStreamer().emitDirectiveOptionNoAutoCompress();
- setFeatureBits(RISCV::FeatureDisableAsmCompression,
- "disable-asm-compression");
+ getTargetStreamer().emitDirectiveOptionNoRVC();
+ clearFeatureBits(RISCV::FeatureStdExtC, "c");
+ clearFeatureBits(RISCV::FeatureStdExtZca, "zca");
return false;
}
@@ -3254,8 +3252,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
// Unknown option.
Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', "
- "'rvc', 'norvc', 'arch', 'relax' or "
- "'norelax'");
+ "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
+ "'exact' or 'noexact'");
Parser.eatToEndOfStatement();
return false;
}
@@ -3466,11 +3464,12 @@ bool RISCVAsmParser::parseDirectiveVariantCC() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
bool Res = false;
- if (!getSTI().hasFeature(RISCV::FeatureDisableAsmCompression))
- Res = RISCVRVC::compress(CInst, Inst, getSTI());
+ const MCSubtargetInfo &STI = getSTI();
+ if (!STI.hasFeature(RISCV::FeatureExactAssembly))
+ Res = RISCVRVC::compress(CInst, Inst, STI);
if (Res)
++RISCVNumInstrsCompressed;
- S.emitInstruction((Res ? CInst : Inst), getSTI());
+ S.emitInstruction((Res ? CInst : Inst), STI);
}
void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index e752b0ec5f58c..83e6f7169e957 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -344,6 +344,10 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
// Given a compressed control flow instruction this function returns
// the expanded instruction.
unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
+ // Disable relaxation if FeatureExactAssembly
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return Op;
+
switch (Op) {
default:
return Op;
@@ -371,6 +375,12 @@ unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
+ // This function has access to two STIs, the member of the AsmBackend, and the
+ // one passed as an argument. The latter is more specific, so we query it for
+ // specific features.
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return false;
+
return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 0edaf8886402f..1814ca2a077f3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -53,8 +53,8 @@ void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index c7cf28e00e73e..bf84f8e700e6d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -62,8 +62,8 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
- void emitDirectiveOptionAutoCompress() override;
- void emitDirectiveOptionNoAutoCompress() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 0bfb832b65415..04a0feb98eec2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -39,8 +39,8 @@ void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
-void RISCVTargetStreamer::emitDirectiveOptionAutoCompress() {}
-void RISCVTargetStreamer::emitDirectiveOptionNoAutoCompress() {}
+void RISCVTargetStreamer::emitDirectiveOptionExact() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionArch(
@@ -127,12 +127,12 @@ void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
OS << "\t.option\tnorvc\n";
}
-void RISCVTargetAsmStreamer::emitDirectiveOptionAutoCompress() {
- OS << "\t.option\tautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionExact() {
+ OS << "\t.option\texact\n";
}
-void RISCVTargetAsmStreamer::emitDirectiveOptionNoAutoCompress() {
- OS << "\t.option\tnoautocompress\n";
+void RISCVTargetAsmStreamer::emitDirectiveOptionNoExact() {
+ OS << "\t.option\tnoexact\n";
}
void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 33ab55ca85536..a23ac19c0cabb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -47,8 +47,8 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitDirectiveOptionNoPIC();
virtual void emitDirectiveOptionRVC();
virtual void emitDirectiveOptionNoRVC();
- virtual void emitDirectiveOptionAutoCompress();
- virtual void emitDirectiveOptionNoAutoCompress();
+ virtual void emitDirectiveOptionExact();
+ virtual void emitDirectiveOptionNoExact();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
@@ -86,8 +86,8 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
void emitDirectiveOptionNoPIC() override;
void emitDirectiveOptionRVC() override;
void emitDirectiveOptionNoRVC() override;
- void emitDirectiveOptionAutoCompress() override;
- void emitDirectiveOptionNoAutoCompress() override;
+ void emitDirectiveOptionExact() override;
+ void emitDirectiveOptionNoExact() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index c7091fe246b68..225b9fb88cdaf 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -255,7 +255,7 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
bool Res = false;
- if (!SubtargetInfo.hasFeature(RISCV::FeatureDisableAsmCompression))
+ if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a0f4c241a6a80..57029b971193a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1470,9 +1470,9 @@ def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
-def FeatureDisableAsmCompression
- : SubtargetFeature<"disable-asm-compression", "EnableAsmCompression", "false",
- "Disable Automatic Assembly Compression.">;
+def FeatureExactAssembly
+ : SubtargetFeature<"exact-asm", "EnableExactAssembly", "true",
+ "Enable Exact Assembly (Disables Compression and Relaxation)">;
foreach i = {1-31} in
def FeatureReserveX#i :
diff --git a/llvm/test/MC/RISCV/option-autocompress.s b/llvm/test/MC/RISCV/option-exact-compression.s
similarity index 82%
rename from llvm/test/MC/RISCV/option-autocompress.s
rename to llvm/test/MC/RISCV/option-exact-compression.s
index d394f69af0b8a..ae38bf6647d17 100644
--- a/llvm/test/MC/RISCV/option-autocompress.s
+++ b/llvm/test/MC/RISCV/option-exact-compression.s
@@ -21,11 +21,13 @@
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-# `.option (no)autocompress` enables and disables instruction compression in the
-# assembler, without changing the current architecture.
-#
-# The default is as if `.option autocompress` has been specified, that is, the
-# assembler compresses by default.
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the automatic compression part of this behaviour.
# CHECK-BYTES: 4108
# CHECK-INST: c.lw a0, 0(a0)
@@ -39,8 +41,8 @@ lw a0, 0(a0)
# CHECK: # encoding: [0x08,0x41]
c.lw a0, 0(a0)
-# CHECK: .option noautocompress
-.option noautocompress
+# CHECK: .option exact
+.option exact
# CHECK-BYTES: 00052503
# CHECK-INST: lw a0, 0(a0)
@@ -54,8 +56,8 @@ lw a0, 0(a0)
# CHECK: # encoding: [0x08,0x41]
c.lw a0, 0(a0)
-# CHECK: .option autocompress
-.option autocompress
+# CHECK: .option noexact
+.option noexact
# CHECK-BYTES: 4108
# CHECK-INST: c.lw a0, 0(a0)
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact-relaxation.s
new file mode 100644
index 0000000000000..ed0a18290c67d
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-exact-relaxation.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv32 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
+# RUN: | llvm-objdump --triple=riscv64 --no-show-raw-insn -dr - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+
+## `.option exact` disables a variety of assembler behaviour:
+## - automatic compression
+## - branch relaxation (of short branches to longer equivalent sequences)
+## - linker relaxation (emitting R_RISCV_RELAX)
+## `.option noexact` enables these behaviours again. It is also the default.
+
+## This test only checks the branch and linker relaxation part of this behaviour.
+
+
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x10
+# CHECK-OBJDUMP-NEXT: j 0xc
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option exact
+.option exact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NOT: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NOT: R_RISCV_RELAX
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: beq a0, a1, 0x18
+# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
+beq a0, a1, undefined
+
+# CHECK-ASM: .option noexact
+.option noexact
+
+# CHECK-ASM: call undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
+# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
+# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
+# CHECK-OBJDUMP-NEXT: jalr ra
+call undefined at plt
+
+# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
+# CHECK-OBJDUMP: bne a0, a1, 0x2c
+# CHECK-OBJDUMP-NEXT: j 0x28
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+beq a0, a1, undefined
>From 4e2aaee288e84d0c55dc4c7cfa55a23a8e9df36a Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 13:56:57 -0700
Subject: [PATCH 04/15] fixup! Update implementation to match proposal
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index a7c2f563536ef..8dd428a1ba461 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3178,8 +3178,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
return true;
getTargetStreamer().emitDirectiveOptionExact();
- setFeatureBits(RISCV::FeatureExactAssembly,
- "exact-asm");
+ setFeatureBits(RISCV::FeatureExactAssembly, "exact-asm");
clearFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
@@ -3189,8 +3188,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
return true;
getTargetStreamer().emitDirectiveOptionNoExact();
- clearFeatureBits(RISCV::FeatureExactAssembly,
- "exact-asm");
+ clearFeatureBits(RISCV::FeatureExactAssembly, "exact-asm");
setFeatureBits(RISCV::FeatureRelax, "relax");
return false;
}
@@ -3251,9 +3249,10 @@ bool RISCVAsmParser::parseDirectiveOption() {
}
// Unknown option.
- Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', "
- "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
- "'exact' or 'noexact'");
+ Warning(Parser.getTok().getLoc(),
+ "unknown option, expected 'push', 'pop', "
+ "'rvc', 'norvc', 'arch', 'relax', 'norelax', "
+ "'exact' or 'noexact'");
Parser.eatToEndOfStatement();
return false;
}
>From b83209503bdd7c62981f228561b19329021c5670 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 15:36:19 -0700
Subject: [PATCH 05/15] Fix option-invalid.s test
---
llvm/test/MC/RISCV/option-invalid.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/MC/RISCV/option-invalid.s b/llvm/test/MC/RISCV/option-invalid.s
index 7f6de5f38c528..02d6a91913e91 100644
--- a/llvm/test/MC/RISCV/option-invalid.s
+++ b/llvm/test/MC/RISCV/option-invalid.s
@@ -53,7 +53,7 @@
# CHECK: :[[#@LINE+1]]:13: error: expected newline
.option rvc foo
-# CHECK: :[[#@LINE+1]]:12: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'arch', 'relax' or 'norelax'
+# CHECK: :[[#@LINE+1]]:12: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'arch', 'relax', 'norelax', 'exact' or 'noexact'
.option bar
# CHECK: :[[#@LINE+1]]:12: error: .option pop with no .option push
>From 32f3944adfaee667caf1d11cd2deacf876a545d9 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 16:36:51 -0700
Subject: [PATCH 06/15] Address Review Feedback
---
.../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 62 ++++++++++---------
.../RISCV/MCTargetDesc/RISCVAsmBackend.h | 1 -
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +-
llvm/test/MC/RISCV/option-exact-inlineasm.ll | 21 +++++++
llvm/test/MC/RISCV/option-exact-relaxation.s | 41 ++++++++----
5 files changed, 84 insertions(+), 45 deletions(-)
create mode 100644 llvm/test/MC/RISCV/option-exact-inlineasm.ll
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 83e6f7169e957..6ff102957cafe 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -8,6 +8,7 @@
#include "RISCVAsmBackend.h"
#include "RISCVMCExpr.h"
+#include "RISCVMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
@@ -171,8 +172,39 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(
}
}
+// Given a compressed control flow instruction this function returns
+// the expanded instruction.
+static unsigned getRelaxedOpcode(unsigned Op) {
+ switch (Op) {
+ default:
+ return Op;
+ case RISCV::C_BEQZ:
+ return RISCV::BEQ;
+ case RISCV::C_BNEZ:
+ return RISCV::BNE;
+ case RISCV::C_J:
+ case RISCV::C_JAL: // fall through.
+ return RISCV::JAL;
+ case RISCV::BEQ:
+ return RISCV::PseudoLongBEQ;
+ case RISCV::BNE:
+ return RISCV::PseudoLongBNE;
+ case RISCV::BLT:
+ return RISCV::PseudoLongBLT;
+ case RISCV::BGE:
+ return RISCV::PseudoLongBGE;
+ case RISCV::BLTU:
+ return RISCV::PseudoLongBLTU;
+ case RISCV::BGEU:
+ return RISCV::PseudoLongBGEU;
+ }
+}
+
void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const {
+ if (STI.hasFeature(RISCV::FeatureExactAssembly))
+ return;
+
MCInst Res;
switch (Inst.getOpcode()) {
default:
@@ -341,37 +373,7 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
return std::make_pair(Expr.evaluateKnownAbsolute(Value, Asm), false);
}
-// Given a compressed control flow instruction this function returns
-// the expanded instruction.
-unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
- // Disable relaxation if FeatureExactAssembly
- if (STI.hasFeature(RISCV::FeatureExactAssembly))
- return Op;
- switch (Op) {
- default:
- return Op;
- case RISCV::C_BEQZ:
- return RISCV::BEQ;
- case RISCV::C_BNEZ:
- return RISCV::BNE;
- case RISCV::C_J:
- case RISCV::C_JAL: // fall through.
- return RISCV::JAL;
- case RISCV::BEQ:
- return RISCV::PseudoLongBEQ;
- case RISCV::BNE:
- return RISCV::PseudoLongBNE;
- case RISCV::BLT:
- return RISCV::PseudoLongBLT;
- case RISCV::BGE:
- return RISCV::PseudoLongBGE;
- case RISCV::BLTU:
- return RISCV::PseudoLongBLTU;
- case RISCV::BGEU:
- return RISCV::PseudoLongBGEU;
- }
-}
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
index df5ffe7bc91e9..f5e8d340d9bce 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -81,7 +81,6 @@ class RISCVAsmBackend : public MCAsmBackend {
bool mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const override;
- unsigned getRelaxedOpcode(unsigned Op) const;
void relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const override;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 225b9fb88cdaf..12519c86bf44b 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -254,9 +254,7 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
const MCSubtargetInfo &SubtargetInfo) {
MCInst CInst;
- bool Res = false;
- if (!SubtargetInfo.hasFeature(RISCV::FeatureExactAssembly))
- Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
+ bool Res = RISCVRVC::compress(CInst, Inst, SubtargetInfo);
if (Res)
++RISCVNumInstrsCompressed;
S.emitInstruction(Res ? CInst : Inst, SubtargetInfo);
diff --git a/llvm/test/MC/RISCV/option-exact-inlineasm.ll b/llvm/test/MC/RISCV/option-exact-inlineasm.ll
new file mode 100644
index 0000000000000..4aa46f106b1c0
--- /dev/null
+++ b/llvm/test/MC/RISCV/option-exact-inlineasm.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=riscv32 -mattr=+relax,+c %s --filetype=obj -o - \
+; RUN: | llvm-objdump --triple=riscv32 --mattr=+c -M no-aliases -dr - \
+; RUN: | FileCheck %s
+
+define i32 @foo(ptr noundef %f) nounwind {
+; CHECK-LABEL: <foo>:
+; CHECK: auipc ra, 0x0
+; CHECK-NEXT: R_RISCV_CALL_PLT undefined
+; CHECK-NEXT: jalr ra, 0x0(ra)
+; CHECK-NEXT: lw a0, 0x0(a0)
+; CHECK-NEXT: c.jr ra
+
+entry:
+ %0 = tail call i32 asm sideeffect "
+ .option exact
+ call undefined at plt
+ lw $0, ($1)
+ .option noexact", "=^cr,^cr"(ptr %f)
+ ret i32 %0
+}
+
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact-relaxation.s
index ed0a18290c67d..521b70c2f2d48 100644
--- a/llvm/test/MC/RISCV/option-exact-relaxation.s
+++ b/llvm/test/MC/RISCV/option-exact-relaxation.s
@@ -1,13 +1,15 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+relax %s \
+# RUN: llvm-mc -triple riscv32 -show-encoding \
+# RUN: -M no-aliases -mattr=+c,+relax %s \
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+relax %s \
-# RUN: | llvm-objdump --triple=riscv32 --no-show-raw-insn -dr - \
+# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c,+relax %s \
+# RUN: | llvm-objdump --triple=riscv32 -M no-aliases -dr - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+relax %s \
+# RUN: llvm-mc -triple riscv64 -show-encoding \
+# RUN: -M no-aliases -mattr=+c,+relax %s \
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+relax %s \
-# RUN: | llvm-objdump --triple=riscv64 --no-show-raw-insn -dr - \
+# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c,+relax %s \
+# RUN: | llvm-objdump --triple=riscv64 -M no-aliases -dr - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
## `.option exact` disables a variety of assembler behaviour:
@@ -19,7 +21,6 @@
## This test only checks the branch and linker relaxation part of this behaviour.
-
# CHECK-ASM: call undefined
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
@@ -32,10 +33,16 @@ call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
# CHECK-OBJDUMP: bne a0, a1, 0x10
-# CHECK-OBJDUMP-NEXT: j 0xc
+# CHECK-OBJDUMP-NEXT: jal zero, 0xc
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
beq a0, a1, undefined
+# CHECK-ASM: c.j undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
+# CHECK-OBJDUMP: jal zero, 0x10
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+c.j undefined
+
# CHECK-ASM: .option exact
.option exact
@@ -50,10 +57,16 @@ call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
-# CHECK-OBJDUMP: beq a0, a1, 0x18
+# CHECK-OBJDUMP: beq a0, a1, 0x1c
# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
beq a0, a1, undefined
+# CHECK-ASM: c.j undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
+# CHECK-OBJDUMP: c.j 0x20
+# CHECK-OBJDUMP-NEXT: R_RISCV_RVC_JUMP undefined
+c.j undefined
+
# CHECK-ASM: .option noexact
.option noexact
@@ -68,7 +81,13 @@ call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
-# CHECK-OBJDUMP: bne a0, a1, 0x2c
-# CHECK-OBJDUMP-NEXT: j 0x28
+# CHECK-OBJDUMP: bne a0, a1, 0x32
+# CHECK-OBJDUMP-NEXT: jal zero, 0x2e
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
beq a0, a1, undefined
+
+# CHECK-ASM: c.j undefined
+# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
+# CHECK-OBJDUMP: jal zero, 0x32
+# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
+c.j undefined
>From 8133e9d4ff93bbc5cded35fa8d71001dad26047a Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 19 Mar 2025 16:42:47 -0700
Subject: [PATCH 07/15] fixup! Address Review Feedback
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 6ff102957cafe..c4f3172ba5eed 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -373,8 +373,6 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
return std::make_pair(Expr.evaluateKnownAbsolute(Value, Asm), false);
}
-
-
bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
// This function has access to two STIs, the member of the AsmBackend, and the
>From 3fc5749c0fc8877296c97cd80dcb898720412d3e Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Thu, 20 Mar 2025 18:49:18 -0700
Subject: [PATCH 08/15] Serial Comma
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
llvm/test/MC/RISCV/option-invalid.s | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 8dd428a1ba461..37f9f7bdca1a0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3252,7 +3252,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
Warning(Parser.getTok().getLoc(),
"unknown option, expected 'push', 'pop', "
"'rvc', 'norvc', 'arch', 'relax', 'norelax', "
- "'exact' or 'noexact'");
+ "'exact', or 'noexact'");
Parser.eatToEndOfStatement();
return false;
}
diff --git a/llvm/test/MC/RISCV/option-invalid.s b/llvm/test/MC/RISCV/option-invalid.s
index 02d6a91913e91..27cc97bda360f 100644
--- a/llvm/test/MC/RISCV/option-invalid.s
+++ b/llvm/test/MC/RISCV/option-invalid.s
@@ -53,7 +53,7 @@
# CHECK: :[[#@LINE+1]]:13: error: expected newline
.option rvc foo
-# CHECK: :[[#@LINE+1]]:12: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'arch', 'relax', 'norelax', 'exact' or 'noexact'
+# CHECK: :[[#@LINE+1]]:12: warning: unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'arch', 'relax', 'norelax', 'exact', or 'noexact'
.option bar
# CHECK: :[[#@LINE+1]]:12: error: .option pop with no .option push
>From c8bf69562a67c53aa04ed87903009a329c213e07 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Tue, 25 Mar 2025 17:08:23 -0700
Subject: [PATCH 09/15] Address review feedback
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 1 -
llvm/test/MC/RISCV/option-exact-inlineasm.ll | 1 -
2 files changed, 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index c4f3172ba5eed..7c127c5e94d5b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -8,7 +8,6 @@
#include "RISCVAsmBackend.h"
#include "RISCVMCExpr.h"
-#include "RISCVMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCAssembler.h"
diff --git a/llvm/test/MC/RISCV/option-exact-inlineasm.ll b/llvm/test/MC/RISCV/option-exact-inlineasm.ll
index 4aa46f106b1c0..cc1097d06a96f 100644
--- a/llvm/test/MC/RISCV/option-exact-inlineasm.ll
+++ b/llvm/test/MC/RISCV/option-exact-inlineasm.ll
@@ -18,4 +18,3 @@ entry:
.option noexact", "=^cr,^cr"(ptr %f)
ret i32 %0
}
-
>From 7dc2322cdfe523079d90c2b264a38e5fc98f5db6 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Tue, 25 Mar 2025 17:08:27 -0700
Subject: [PATCH 10/15] Release Note
---
llvm/docs/ReleaseNotes.md | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 30d66b4a77a71..ebc29055e67c7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -132,6 +132,9 @@ Changes to the RISC-V Backend
extension.
* Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)
extension.
+* Adds assembler support for ``.option exact``, which disables automatic compression,
+ and branch and linker relaxation. This can be disabled with ``.option noexact``,
+ which is also the default.
Changes to the WebAssembly Backend
----------------------------------
>From 2c62a5b1a0dbc422293d49ccc526d569f180ca97 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Tue, 25 Mar 2025 21:59:55 -0700
Subject: [PATCH 11/15] Fix features-info.ll
---
llvm/test/CodeGen/RISCV/features-info.ll | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index e8b46b8d78523..5d0b7e0e256e3 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -14,6 +14,7 @@
; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic.
; CHECK-NEXT: dlen-factor-2 - Vector unit DLEN(data path width) is half of VLEN.
; CHECK-NEXT: e - 'E' (Embedded Instruction Set with 16 GPRs).
+; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation).
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)).
; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
>From 318afee630ba99f566eb9be5e402758d77ea46c8 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 26 Mar 2025 08:45:04 -0700
Subject: [PATCH 12/15] Move LLC test to test/CodeGen
---
llvm/test/{MC => CodeGen}/RISCV/option-exact-inlineasm.ll | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/{MC => CodeGen}/RISCV/option-exact-inlineasm.ll (100%)
diff --git a/llvm/test/MC/RISCV/option-exact-inlineasm.ll b/llvm/test/CodeGen/RISCV/option-exact-inlineasm.ll
similarity index 100%
rename from llvm/test/MC/RISCV/option-exact-inlineasm.ll
rename to llvm/test/CodeGen/RISCV/option-exact-inlineasm.ll
>From 58a0f1b2a01e198518ea39a2d3a8be007c1dfe0a Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 26 Mar 2025 08:45:20 -0700
Subject: [PATCH 13/15] Alphabetize directiveOption declarations
---
.../RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 12 ++++----
.../RISCV/MCTargetDesc/RISCVELFStreamer.h | 12 ++++----
.../MCTargetDesc/RISCVTargetStreamer.cpp | 15 +++++-----
.../RISCV/MCTargetDesc/RISCVTargetStreamer.h | 28 +++++++++----------
4 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 1814ca2a077f3..5a81c829e3a89 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -47,16 +47,16 @@ RISCVELFStreamer &RISCVTargetELFStreamer::getStreamer() {
return static_cast<RISCVELFStreamer &>(Streamer);
}
-void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
-void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetELFStreamer::emitDirectiveOptionExact() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoExact() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionPIC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionPop() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionPush() {}
void RISCVTargetELFStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetELFStreamer::emitDirectiveOptionNoRelax() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionRVC() {}
+void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
getStreamer().setAttributeItem(Attribute, Value, /*OverwriteExisting=*/true);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index bf84f8e700e6d..98948cd3e9493 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -56,16 +56,16 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
RISCVELFStreamer &getStreamer();
RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
- void emitDirectiveOptionPush() override;
- void emitDirectiveOptionPop() override;
- void emitDirectiveOptionPIC() override;
- void emitDirectiveOptionNoPIC() override;
- void emitDirectiveOptionRVC() override;
- void emitDirectiveOptionNoRVC() override;
void emitDirectiveOptionExact() override;
void emitDirectiveOptionNoExact() override;
+ void emitDirectiveOptionPIC() override;
+ void emitDirectiveOptionNoPIC() override;
+ void emitDirectiveOptionPop() override;
+ void emitDirectiveOptionPush() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
+ void emitDirectiveOptionRVC() override;
+ void emitDirectiveOptionNoRVC() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
void finish() override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 04a0feb98eec2..dd56e09f3bc3c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -33,18 +33,17 @@ RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
void RISCVTargetStreamer::finish() { finishAttributeSection(); }
void RISCVTargetStreamer::reset() {}
-void RISCVTargetStreamer::emitDirectiveOptionPush() {}
-void RISCVTargetStreamer::emitDirectiveOptionPop() {}
-void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
-void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
-void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
-void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) {}
void RISCVTargetStreamer::emitDirectiveOptionExact() {}
void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
+void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
+void RISCVTargetStreamer::emitDirectiveOptionPop() {}
+void RISCVTargetStreamer::emitDirectiveOptionPush() {}
void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
-void RISCVTargetStreamer::emitDirectiveOptionArch(
- ArrayRef<RISCVOptionArchArg> Args) {}
+void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
+void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
void RISCVTargetStreamer::finishAttributeSection() {}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index a23ac19c0cabb..169cb0f79ba78 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -41,17 +41,17 @@ class RISCVTargetStreamer : public MCTargetStreamer {
void finish() override;
virtual void reset();
- virtual void emitDirectiveOptionPush();
- virtual void emitDirectiveOptionPop();
- virtual void emitDirectiveOptionPIC();
- virtual void emitDirectiveOptionNoPIC();
- virtual void emitDirectiveOptionRVC();
- virtual void emitDirectiveOptionNoRVC();
+ virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
virtual void emitDirectiveOptionExact();
virtual void emitDirectiveOptionNoExact();
+ virtual void emitDirectiveOptionPIC();
+ virtual void emitDirectiveOptionNoPIC();
+ virtual void emitDirectiveOptionPop();
+ virtual void emitDirectiveOptionPush();
virtual void emitDirectiveOptionRelax();
virtual void emitDirectiveOptionNoRelax();
- virtual void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args);
+ virtual void emitDirectiveOptionRVC();
+ virtual void emitDirectiveOptionNoRVC();
virtual void emitDirectiveVariantCC(MCSymbol &Symbol);
virtual void emitAttribute(unsigned Attribute, unsigned Value);
virtual void finishAttributeSection();
@@ -80,17 +80,17 @@ class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
public:
RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
- void emitDirectiveOptionPush() override;
- void emitDirectiveOptionPop() override;
- void emitDirectiveOptionPIC() override;
- void emitDirectiveOptionNoPIC() override;
- void emitDirectiveOptionRVC() override;
- void emitDirectiveOptionNoRVC() override;
+ void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
void emitDirectiveOptionExact() override;
void emitDirectiveOptionNoExact() override;
+ void emitDirectiveOptionPIC() override;
+ void emitDirectiveOptionNoPIC() override;
+ void emitDirectiveOptionPop() override;
+ void emitDirectiveOptionPush() override;
void emitDirectiveOptionRelax() override;
void emitDirectiveOptionNoRelax() override;
- void emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) override;
+ void emitDirectiveOptionRVC() override;
+ void emitDirectiveOptionNoRVC() override;
void emitDirectiveVariantCC(MCSymbol &Symbol) override;
};
>From a764474491125c94dd6cbe55fdd26394f0f05495 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 26 Mar 2025 09:00:44 -0700
Subject: [PATCH 14/15] Combine exact test files
---
llvm/test/MC/RISCV/option-exact-compression.s | 72 -----------------
...tion-exact-relaxation.s => option-exact.s} | 77 ++++++++++++++-----
2 files changed, 56 insertions(+), 93 deletions(-)
delete mode 100644 llvm/test/MC/RISCV/option-exact-compression.s
rename llvm/test/MC/RISCV/{option-exact-relaxation.s => option-exact.s} (56%)
diff --git a/llvm/test/MC/RISCV/option-exact-compression.s b/llvm/test/MC/RISCV/option-exact-compression.s
deleted file mode 100644
index ae38bf6647d17..0000000000000
--- a/llvm/test/MC/RISCV/option-exact-compression.s
+++ /dev/null
@@ -1,72 +0,0 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c \
-# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -show-encoding -mattr=+c \
-# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-
-## `.option exact` disables a variety of assembler behaviour:
-## - automatic compression
-## - branch relaxation (of short branches to longer equivalent sequences)
-## - linker relaxation (emitting R_RISCV_RELAX)
-## `.option noexact` enables these behaviours again. It is also the default.
-
-## This test only checks the automatic compression part of this behaviour.
-
-# CHECK-BYTES: 4108
-# CHECK-INST: c.lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x08,0x41]
-lw a0, 0(a0)
-
-# CHECK-BYTES: 4108
-# CHECK-INST: c.lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x08,0x41]
-c.lw a0, 0(a0)
-
-# CHECK: .option exact
-.option exact
-
-# CHECK-BYTES: 00052503
-# CHECK-INST: lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x03,0x25,0x05,0x00]
-lw a0, 0(a0)
-
-# CHECK-BYTES: 4108
-# CHECK-INST: c.lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x08,0x41]
-c.lw a0, 0(a0)
-
-# CHECK: .option noexact
-.option noexact
-
-# CHECK-BYTES: 4108
-# CHECK-INST: c.lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x08,0x41]
-lw a0, 0(a0)
-
-# CHECK-BYTES: 4108
-# CHECK-INST: c.lw a0, 0(a0)
-# CHECK-ALIAS: lw a0, 0(a0)
-# CHECK: # encoding: [0x08,0x41]
-c.lw a0, 0(a0)
diff --git a/llvm/test/MC/RISCV/option-exact-relaxation.s b/llvm/test/MC/RISCV/option-exact.s
similarity index 56%
rename from llvm/test/MC/RISCV/option-exact-relaxation.s
rename to llvm/test/MC/RISCV/option-exact.s
index 521b70c2f2d48..f90bd00621c42 100644
--- a/llvm/test/MC/RISCV/option-exact-relaxation.s
+++ b/llvm/test/MC/RISCV/option-exact.s
@@ -1,16 +1,15 @@
-# RUN: llvm-mc -triple riscv32 -show-encoding \
-# RUN: -M no-aliases -mattr=+c,+relax %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -triple riscv32 -show-encoding -mattr=+c,+relax \
+# RUN: -M no-aliases %s | FileCheck -check-prefixes=CHECK-ASM,CHECK-INST %s
# RUN: llvm-mc -triple riscv32 -filetype=obj -mattr=+c,+relax %s \
-# RUN: | llvm-objdump --triple=riscv32 -M no-aliases -dr - \
-# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+c -dr --no-print-imm-hex -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP,CHECK-INST %s
# RUN: llvm-mc -triple riscv64 -show-encoding \
# RUN: -M no-aliases -mattr=+c,+relax %s \
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
# RUN: llvm-mc -triple riscv64 -filetype=obj -mattr=+c,+relax %s \
-# RUN: | llvm-objdump --triple=riscv64 -M no-aliases -dr - \
-# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP %s
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+c -dr --no-print-imm-hex -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-OBJDUMP,CHECK-INST %s
## `.option exact` disables a variety of assembler behaviour:
## - automatic compression
@@ -18,76 +17,112 @@
## - linker relaxation (emitting R_RISCV_RELAX)
## `.option noexact` enables these behaviours again. It is also the default.
-## This test only checks the branch and linker relaxation part of this behaviour.
+# CHECK-OBJDUMP: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+# CHECK-OBJDUMP: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
# CHECK-ASM: call undefined
+# CHECK-ASM-SAME: # encoding: [0x97'A',A,A,A,0xe7'A',0x80'A',A,A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
-# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP: auipc ra, 0
# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
# CHECK-OBJDUMP-NEXT: jalr ra
call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-SAME: # encoding: [0x63'A',A,0xb5'A',A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
-# CHECK-OBJDUMP: bne a0, a1, 0x10
-# CHECK-OBJDUMP-NEXT: jal zero, 0xc
+# CHECK-OBJDUMP: bne a0, a1, 0x14
+# CHECK-OBJDUMP-NEXT: jal zero, 0x10
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
beq a0, a1, undefined
# CHECK-ASM: c.j undefined
+# CHECK-ASM-SAME: # encoding: [0bAAAAAA01,0b101AAAAA]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
-# CHECK-OBJDUMP: jal zero, 0x10
+# CHECK-OBJDUMP: jal zero, 0x14
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
c.j undefined
# CHECK-ASM: .option exact
.option exact
+# CHECK-OBJDUMP: 00052503
+# CHECK-INST: lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x03,0x25,0x05,0x00]
+lw a0, 0(a0)
+
+# CHECK-OBJDUMP: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
# CHECK-ASM: call undefined
+# CHECK-ASM-SAME: # encoding: [0x97'A',A,A,A,0xe7'A',0x80'A',A,A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
# CHECK-ASM-NOT: fixup_riscv_relax
-# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP: auipc ra, 0
# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
# CHECK-OBJDUMP-NOT: R_RISCV_RELAX
-# CHECK-OBJDUMP-NEXT: jalr ra
+# CHECK-OBJDUMP-NEXT: jalr ra, 0(ra)
call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-SAME: # encoding: [0x63'A',A,0xb5'A',A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
-# CHECK-OBJDUMP: beq a0, a1, 0x1c
+# CHECK-OBJDUMP: beq a0, a1, 0x26
# CHECK-OBJDUMP-NEXT: R_RISCV_BRANCH undefined
beq a0, a1, undefined
# CHECK-ASM: c.j undefined
+# CHECK-ASM-SAME: # encoding: [0bAAAAAA01,0b101AAAAA]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
-# CHECK-OBJDUMP: c.j 0x20
+# CHECK-OBJDUMP: c.j 0x2a
# CHECK-OBJDUMP-NEXT: R_RISCV_RVC_JUMP undefined
c.j undefined
# CHECK-ASM: .option noexact
.option noexact
+# CHECK-OBJDUMP: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x08,0x41]
+lw a0, 0(a0)
+
+# CHECK-OBJDUMP: 4108
+# CHECK-INST: c.lw a0, 0(a0)
+# CHECK-ASM: # encoding: [0x08,0x41]
+c.lw a0, 0(a0)
+
# CHECK-ASM: call undefined
+# CHECK-ASM-SAME: # encoding: [0x97'A',A,A,A,0xe7'A',0x80'A',A,A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_call_plt
# CHECK-ASM-NEXT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
-# CHECK-OBJDUMP: auipc ra, 0x0
+# CHECK-OBJDUMP: auipc ra, 0
# CHECK-OBJDUMP-NEXT: R_RISCV_CALL_PLT undefined
# CHECK-OBJDUMP-NEXT: R_RISCV_RELAX *ABS*
-# CHECK-OBJDUMP-NEXT: jalr ra
+# CHECK-OBJDUMP-NEXT: jalr ra, 0(ra)
call undefined at plt
# CHECK-ASM: beq a0, a1, undefined
+# CHECK-ASM-SAME: # encoding: [0x63'A',A,0xb5'A',A]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_branch
-# CHECK-OBJDUMP: bne a0, a1, 0x32
-# CHECK-OBJDUMP-NEXT: jal zero, 0x2e
+# CHECK-OBJDUMP: bne a0, a1, 0x40
+# CHECK-OBJDUMP-NEXT: jal zero, 0x3c
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
beq a0, a1, undefined
# CHECK-ASM: c.j undefined
+# CHECK-ASM-SAME: # encoding: [0bAAAAAA01,0b101AAAAA]
# CHECK-ASM-NEXT: fixup A - offset: 0, value: undefined, kind: fixup_riscv_rvc_jump
-# CHECK-OBJDUMP: jal zero, 0x32
+# CHECK-OBJDUMP: jal zero, 0x40
# CHECK-OBJDUMP-NEXT: R_RISCV_JAL undefined
c.j undefined
>From 6c108149862f6b5724a64a370fc6fa32771bae2f Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Wed, 26 Mar 2025 09:01:58 -0700
Subject: [PATCH 15/15] clang-format
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index dd56e09f3bc3c..5785f7da88898 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -33,7 +33,8 @@ RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
void RISCVTargetStreamer::finish() { finishAttributeSection(); }
void RISCVTargetStreamer::reset() {}
-void RISCVTargetStreamer::emitDirectiveOptionArch(ArrayRef<RISCVOptionArchArg> Args) {}
+void RISCVTargetStreamer::emitDirectiveOptionArch(
+ ArrayRef<RISCVOptionArchArg> Args) {}
void RISCVTargetStreamer::emitDirectiveOptionExact() {}
void RISCVTargetStreamer::emitDirectiveOptionNoExact() {}
void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
More information about the llvm-commits
mailing list