[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Benjamin Maxwell via llvm-commits]

================
@@ -2712,6 +2736,20 @@ class TargetLoweringBase {
       setCondCodeAction(CCs, VT, Action);
   }
 
+  /// Indicate how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input
+  /// type InputVT should be treated by the target. Either it's legal, needs to
+  /// be promoted to a larger size, needs to be expanded to some other code
+  /// sequence, or the target has a custom expander for it.
+  void setPartialReduceMLAAction(MVT AccVT, MVT InputVT,
+                                 LegalizeAction Action) {
+    assert(AccVT.isValid() && InputVT.isValid() &&
+           "setPartialReduceMLAAction types aren't valid");
+    auto AccI = AccVT.SimpleTy;
+    auto InputI = InputVT.SimpleTy;
+    PartialReduceActionTypes TypeHash = std::make_pair(AccI, InputI);
+    PartialReduceMLAActions[TypeHash] = Action;
----------------
MacDue wrote:

```suggestion
    PartialReduceActionTypes TypePair = std::make_pair(AccI, InputI);
    PartialReduceMLAActions[TypePair] = Action;
```

https://github.com/llvm/llvm-project/pull/130933