[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Benjamin Maxwell via llvm-commits]

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@@ -3658,6 +3696,17 @@ class TargetLoweringBase {
   /// up the MVT::VALUETYPE_SIZE value to the next multiple of 8.
   uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::VALUETYPE_SIZE + 7) / 8];
 
+  using PartialReduceActionTypes =
+      std::pair<MVT::SimpleValueType, MVT::SimpleValueType>;
+  /// For each result type and input type for the ISD::PARTIAL_REDUCE_U/SMLA
+  /// nodes, keep a LegalizeAction which indicates how instruction selection
+  /// should deal with this operation.
+  /// The key is made up of the accumulator type (AccTy) and the input type
+  /// (InTy) in the format of `(AccTy << 16) + InTy`.
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MacDue wrote:

Outdated comment 

https://github.com/llvm/llvm-project/pull/130933