[llvm] [RVIU] Modify operand regclass in load store patterns (PR #133071)
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Wed Mar 26 05:25:07 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sudharsan Veeravalli (svs-quic)
<details>
<summary>Changes</summary>
$rs1 is defined as GPRMem in the correspoding instruction definition classes.
---
Full diff: https://github.com/llvm/llvm-project/pull/133071.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+4-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 253f24aa0d68d..b61992298ca95 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1836,8 +1836,8 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
/// Loads
class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
- : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
- (Inst GPR:$rs1, simm12:$imm12)>;
+ : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12:$imm12))),
+ (Inst GPRMem:$rs1, simm12:$imm12)>;
def : LdPat<sextloadi8, LB>;
def : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
@@ -1851,9 +1851,9 @@ def : LdPat<zextloadi16, LHU>;
class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
ValueType vt>
- : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPR:$rs1),
+ : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPRMem:$rs1),
simm12:$imm12)),
- (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
+ (Inst StTy:$rs2, GPRMem:$rs1, simm12:$imm12)>;
def : StPat<truncstorei8, SB, GPR, XLenVT>;
def : StPat<truncstorei16, SH, GPR, XLenVT>;
``````````
</details>
https://github.com/llvm/llvm-project/pull/133071
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