[llvm] [AArch64] Make use of byte FPR stores for bytes extracted from vectors (PR #131793)

[Gaëtan Bossu via llvm-commits]

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@@ -338,6 +338,8 @@ def amdgpuBufferFatPointer : ValueType<160, 234>;
 // FIXME: Remove this and the getPointerType() override if MVT::i82 is added.
 def amdgpuBufferStridedPointer : ValueType<192, 235>;
 
+def vi8       : ValueType<8,  236>;  // 8-bit integer in FPR (AArch64)
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gbossu wrote:

Curious: Why are 8-bit FPR considered illegal if the SIMD/FP registers can be addressed as B registers?

https://github.com/llvm/llvm-project/pull/131793