[clang] [llvm] [AArch64] Add FEAT_FPAC to Grace (PR #133054)

[Sjoerd Meijer via llvm-commits]

https://github.com/sjoerdmeijer created https://github.com/llvm/llvm-project/pull/133054

This feature is supported in Grace, but wasn't specified in the CPU definition. This is not important for codegen, but is good for completeness, and good for other tools that could query the CPU definition (e.g. llvm-exegesis).

>From 9cb58d69fa66bd079a573d8d43f525ce49210969 Mon Sep 17 00:00:00 2001
From: Sjoerd Meijer <smeijer at nvidia.com>
Date: Wed, 26 Mar 2025 01:38:46 -0700
Subject: [PATCH] [AArch64] Add FEAT_FPAC to Grace

This feature is supported in Grace, but wasn't specified in the CPU
definition. This is not important for codegen, but is good for
completeness, and good for other tools that could query the CPU
definition (e.g. llvm-exegesis).
---
 clang/test/Driver/print-enabled-extensions/aarch64-grace.c | 3 ++-
 llvm/lib/Target/AArch64/AArch64Processors.td               | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
index fde6aee468cdc..739d86f1fae0f 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c
@@ -21,6 +21,7 @@
 // CHECK-NEXT:     FEAT_FHM                                               Enable FP16 FML instructions
 // CHECK-NEXT:     FEAT_FP                                                Enable Armv8.0-A Floating Point Extensions
 // CHECK-NEXT:     FEAT_FP16                                              Enable half-precision floating-point data processing
+// CHECK-NEXT:     FEAT_FPAC                                              Enable Armv8.3-A Pointer Authentication Faulting enhancement
 // CHECK-NEXT:     FEAT_FRINTTS                                           Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
 // CHECK-NEXT:     FEAT_FlagM                                             Enable Armv8.4-A Flag Manipulation instructions
 // CHECK-NEXT:     FEAT_FlagM2                                            Enable alternative NZCV format for floating point comparisons
@@ -59,4 +60,4 @@
 // CHECK-NEXT:     FEAT_TRBE                                              Enable Trace Buffer Extension
 // CHECK-NEXT:     FEAT_TRF                                               Enable Armv8.4-A Trace extension
 // CHECK-NEXT:     FEAT_UAO                                               Enable Armv8.2-A UAO PState
-// CHECK-NEXT:     FEAT_VHE                                               Enable Armv8.1-A Virtual Host extension
\ No newline at end of file
+// CHECK-NEXT:     FEAT_VHE                                               Enable Armv8.1-A Virtual Host extension
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 30d9372e4afd1..43b678ef78713 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1067,7 +1067,8 @@ def ProcessorFeatures {
                                      FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
                                      FeatureSSBS, FeatureCCIDX,
                                      FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
-  list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3]);
+  list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3,
+                                                          FeatureFPAC]);
 
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not