[llvm] [RISCV] Add Xqci Insn Formats (PR #132986)

[Sudharsan Veeravalli via llvm-commits]

================
@@ -130,6 +132,219 @@ def simm32_lsb0 : Operand<OtherVT> {
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
+
+class DirectiveInsnQC_EAI<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EAI> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<1> func1;
+
+  bits<5> rd;
+  bits<32> imm32;
+
+  let Inst{47-16} = imm32;
+  let Inst{15}    = func1;
+  let Inst{14-12} = func3;
+  let Inst{11-7}  = rd;
+  let Inst{6-0}   = opcode;
+
+  let AsmString = ".insn qc.eai " # argstr;
+}
+
+class DirectiveInsnQC_EI<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EI> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<2> func2;
+
+  bits<5> rd;
+  bits<5> rs1;
+  bits<26> imm26;
+
+  let Inst{47-32} = imm26{25-10};
+  let Inst{31-30} = func2;
+  let Inst{29-20} = imm26{9-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = func3;
+  let Inst{11-7}  = rd;
+  let Inst{6-0}   = opcode;
+
+  let AsmString = ".insn qc.ei " # argstr;
+}
+
+class DirectiveInsnQC_EB<dag outs, dag ins, string argstr>
+  : RVInst48<outs, ins, "", "", [], InstFormatQC_EB> {
+  bits<7> opcode;
+  bits<3> func3;
+  bits<5> func5;
+
+  bits<5> rs1;
+  bits<12> imm12; // This one is the PC-relative offset
+  bits<16> imm16;
+
+  let Inst{47-32} = imm16;
----------------
svs-quic wrote:

The qc.e.<branch> instructions all take a non zero imm16. While some take a simm16 there are two that take a uimm16 (qc.e.bgeui/qc.e.bltui). We will not be able to accommodate all valid values for them in simm16. 

Also would the .insn for these instructions error out if the comparison is against 0? I took a look and could not find a test for it. Could you point me to it or add one please?

https://github.com/llvm/llvm-project/pull/132986