[llvm] [AMDGPU] Add sext_trunc in RegBankCombiner (PR #131623)

[Christudasan Devadasan via llvm-commits]

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@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s
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cdevadas wrote:

Yes. It helps to capture the lowering at significant points during the codegen that are important to test in certain scenarios. 

https://github.com/llvm/llvm-project/pull/131623