[llvm] [MCA] Update of RISCV/SiFive7/instruction-tables-tests.s (PR #132972)
Julien Villette via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 25 11:20:14 PDT 2025
https://github.com/jvillette38 created https://github.com/llvm/llvm-project/pull/132972
Fixing MR #130574 after merge in main branch.
Throughput has been updated in between.
>From 399f0d592e8f96bbc017b13a53235767c0713945 Mon Sep 17 00:00:00 2001
From: Julien Villette <julien.villette at sipearl.com>
Date: Tue, 25 Mar 2025 19:13:35 +0100
Subject: [PATCH] [MCA] Update of RISCV/SiFive7/instruction-tables-tests.s
---
.../RISCV/SiFive7/instruction-tables-tests.s | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
index 1e0e90c741c37..4f8b4769b428e 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
@@ -183,7 +183,7 @@
# ISN: [1] [2] [3] [4] [5] [6] Instructions:
# ISN-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
-# ISN-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+# ISN-NEXT: 1 4 2.00 * vlm.v v4, (a1)
# NISB: Instruction Info:
# NISB-NEXT: [1]: #uOps
@@ -217,43 +217,43 @@
# ISF: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# ISF-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
-# ISF-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
+# ISF-NEXT: 1 4 2.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
# ISFB: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
# ISFB-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
-# ISFB-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
+# ISFB-NEXT: 1 4 2.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
# ISFBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Encodings: Instructions:
# ISFBE-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
-# ISFBE-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
+# ISFBE-NEXT: 1 4 2.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
# ISFE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] Encodings: Instructions:
# ISFE-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
-# ISFE-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
+# ISFE-NEXT: 1 4 2.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
# ISNB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# ISNB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
-# ISNB-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+# ISNB-NEXT: 1 4 2.00 * vlm.v v4, (a1)
# ISNBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
# ISNBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
-# ISNBE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+# ISNBE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
# ISNE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
# ISNE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
-# ISNE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+# ISNE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
# NISB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
# NISB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
-# NISB-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+# NISB-NEXT: 1 4 2.00 * vlm.v v4, (a1)
# NISBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
# NISBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
-# NISBE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+# NISBE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
# NISE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
# NISE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
-# NISE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+# NISE-NEXT: 1 4 2.00 * 4 07 82 b5 02 vlm.v v4, (a1)
# ISN: Resources:
# ISN-NEXT: [0] - SiFive7FDiv
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