[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

Hi @paulwalker-arm, I'm very sorry for taking so long to update this. Initially, I was waiting on #129732 to get merged to propose the alternative version that combines SVE LDR/STR into LDP/STP directly, but then that PR took a bit longer than expected and I had to put this on hold.

I believe I've addressed most of your feedback. I also have a tentative patch implementing the SVE LDR/STR pairing you initially suggested. Would you prefer I open a separate PR for this, or should I include it in this patch so we can decide on the approach to go for?

Thanks very much!

https://github.com/llvm/llvm-project/pull/127500