[llvm] f4bb9b5 - [MCA] Extend -instruction-tables option with verbosity levels (#130574)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 25 09:20:01 PDT 2025
Author: Julien Villette
Date: 2025-03-25T09:19:57-07:00
New Revision: f4bb9b53ad09739ae120df66a317c9b89ddcaff0
URL: https://github.com/llvm/llvm-project/commit/f4bb9b53ad09739ae120df66a317c9b89ddcaff0
DIFF: https://github.com/llvm/llvm-project/commit/f4bb9b53ad09739ae120df66a317c9b89ddcaff0.diff
LOG: [MCA] Extend -instruction-tables option with verbosity levels (#130574)
Option becomes: -instruction-tables=`<level>`
The choice of `<level>` controls number of printed information.
`<level>` may be `none` (default), `normal`, `full`.
Note: If the option is used without `<label>`, default is `normal`
(legacy).
When `<level>` is `full`, additional information are:
- `<Bypass Latency>`: Latency when a bypass is implemented between
operands
in pipelines (see SchedReadAdvance).
- `<LLVM Opcode Name>`: mnemonic plus operands identifier.
- `<Resources units>`: Used resources associated with LLVM Opcode.
- `<instruction comment>`: reports comment if any from source assembly.
Level `full` can be used to better check scheduling info when TableGen
is modified.
LLVM Opcode name help to find right instruction regexp to fix TableGen
Scheduling Info.
-instruction-tables=full option is validated on
AArch64/Neoverse/V1-sve-instructions.s
Follow up of MR #126703
---------
Co-authored-by: Julien Villette <julien.villette at sipearl.com>
Added:
llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
Modified:
llvm/docs/CommandGuide/llvm-mca.rst
llvm/include/llvm/MC/MCSchedule.h
llvm/lib/MC/MCSchedule.cpp
llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
llvm/tools/llvm-mca/Views/InstructionInfoView.h
llvm/tools/llvm-mca/llvm-mca.cpp
Removed:
################################################################################
diff --git a/llvm/docs/CommandGuide/llvm-mca.rst b/llvm/docs/CommandGuide/llvm-mca.rst
index f610ea2f21682..bea19317ebd61 100644
--- a/llvm/docs/CommandGuide/llvm-mca.rst
+++ b/llvm/docs/CommandGuide/llvm-mca.rst
@@ -197,7 +197,7 @@ option specifies "``-``", then the output will also be sent to standard output.
Enable all the view.
-.. option:: -instruction-tables
+.. option:: -instruction-tables=<level>
Prints resource pressure information based on the static information
available from the processor model. This
diff ers from the resource pressure
@@ -205,6 +205,24 @@ option specifies "``-``", then the output will also be sent to standard output.
the theoretical uniform distribution of resource pressure for every
instruction in sequence.
+ The choice of `<level>` controls number of printed information.
+ `<level>` may be `none` (default), `normal`, `full`.
+ Note: If the option is used without `<label>`, default is `normal` (legacy).
+
+ When `<level>` is `full`, additional information are:
+ - `<Bypass Latency>`: Latency when a bypass is implemented between operands
+ in pipelines (see SchedReadAdvance).
+ - `<LLVM Opcode Name>`: mnemonic plus operands identifier.
+ - `<Resources units>`: Used resources associated with LLVM Opcode.
+ - `<instruction comment>`: reports comment if any from source assembly.
+
+ `<Resources units>` syntax can be:
+ - <Resource Name>: ReleaseAtCycle is 1.
+ - <Resource Name>[<ReleaseAtCycle>]: ReleaseAtCycle is greater than 1
+ and AcquireAtCycle is 0.
+ - <Resource Name>[<AcquireAtCycle>,<ReleaseAtCycle>]: ReleaseAtCycle
+ is greater than 1 and AcquireAtCycle is greater than 0.
+
.. option:: -bottleneck-analysis
Print information about bottlenecks that affect the throughput. This analysis
diff --git a/llvm/include/llvm/MC/MCSchedule.h b/llvm/include/llvm/MC/MCSchedule.h
index fe731d086f70a..57c8ebeee02a7 100644
--- a/llvm/include/llvm/MC/MCSchedule.h
+++ b/llvm/include/llvm/MC/MCSchedule.h
@@ -402,6 +402,10 @@ struct MCSchedModel {
static unsigned getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
unsigned WriteResourceIdx = 0);
+ /// Returns the bypass delay cycle for the maximum latency write cycle
+ static unsigned getBypassDelayCycles(const MCSubtargetInfo &STI,
+ const MCSchedClassDesc &SCDesc);
+
/// Returns the default initialized model.
static const MCSchedModel Default;
};
diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp
index 60994c13caf02..8aea08919f469 100644
--- a/llvm/lib/MC/MCSchedule.cpp
+++ b/llvm/lib/MC/MCSchedule.cpp
@@ -177,3 +177,37 @@ MCSchedModel::getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
return std::abs(DelayCycles);
}
+
+unsigned MCSchedModel::getBypassDelayCycles(const MCSubtargetInfo &STI,
+ const MCSchedClassDesc &SCDesc) {
+
+ ArrayRef<MCReadAdvanceEntry> Entries = STI.getReadAdvanceEntries(SCDesc);
+ if (Entries.empty())
+ return 0;
+
+ unsigned MaxLatency = 0;
+ unsigned WriteResourceID = 0;
+ unsigned DefEnd = SCDesc.NumWriteLatencyEntries;
+
+ for (unsigned DefIdx = 0; DefIdx != DefEnd; ++DefIdx) {
+ // Lookup the definition's write latency in SubtargetInfo.
+ const MCWriteLatencyEntry *WLEntry =
+ STI.getWriteLatencyEntry(&SCDesc, DefIdx);
+ unsigned Cycles = 0;
+ // If latency is Invalid (<0), consider 0 cycle latency
+ if (WLEntry->Cycles > 0)
+ Cycles = (unsigned)WLEntry->Cycles;
+ if (Cycles > MaxLatency) {
+ MaxLatency = Cycles;
+ WriteResourceID = WLEntry->WriteResourceID;
+ }
+ }
+
+ for (const MCReadAdvanceEntry &E : Entries) {
+ if (E.WriteResourceID == WriteResourceID)
+ return E.Cycles;
+ }
+
+ // Unable to find WriteResourceID in MCReadAdvanceEntry Entries
+ return 0;
+}
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
index bcbc5eecd924b..d855ba06ec992 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-sve-instructions.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables=full < %s | FileCheck %s
abs z0.b, p0/m, z0.b
abs z0.d, p0/m, z0.d
@@ -2467,6 +2467,27 @@ zip2 z31.d, z31.d, z31.d
zip2 z31.h, z31.h, z31.h
zip2 z31.s, z31.s, z31.s
+# CHECK: Resources:
+# CHECK-NEXT: [0] - V1UnitB:2
+# CHECK-NEXT: [1] - V1UnitD:2
+# CHECK-NEXT: [2] - V1UnitFlg:3
+# CHECK-NEXT: [3] - V1UnitI:4 V1UnitS, V1UnitS, V1UnitM0, V1UnitM1
+# CHECK-NEXT: [4] - V1UnitL:3 V1UnitL01, V1UnitL01, V1UnitL2
+# CHECK-NEXT: [5] - V1UnitL2:1
+# CHECK-NEXT: [6] - V1UnitL01:2
+# CHECK-NEXT: [7] - V1UnitM:2 V1UnitM0, V1UnitM1
+# CHECK-NEXT: [8] - V1UnitM0:1
+# CHECK-NEXT: [9] - V1UnitM1:1
+# CHECK-NEXT: [10] - V1UnitS:2
+# CHECK-NEXT: [11] - V1UnitV:4 V1UnitV0, V1UnitV1, V1UnitV2, V1UnitV3
+# CHECK-NEXT: [12] - V1UnitV0:1
+# CHECK-NEXT: [13] - V1UnitV1:1
+# CHECK-NEXT: [14] - V1UnitV2:1
+# CHECK-NEXT: [15] - V1UnitV3:1
+# CHECK-NEXT: [16] - V1UnitV01:2 V1UnitV0, V1UnitV1
+# CHECK-NEXT: [17] - V1UnitV02:2 V1UnitV0, V1UnitV2
+# CHECK-NEXT: [18] - V1UnitV13:2 V1UnitV1, V1UnitV3
+
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
@@ -2474,2473 +2495,2476 @@ zip2 z31.s, z31.s, z31.s
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 0.50 abs z0.b, p0/m, z0.b
-# CHECK-NEXT: 1 2 0.50 abs z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 0.50 abs z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 2 0.50 abs z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 0.50 abs z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 abs z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 abs z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 abs z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 add z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 add z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 add z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 add z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 add z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 add z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 add z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 add z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 add z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 add z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 add z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 add z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 add z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 add z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 add z0.s, z1.s, z2.s
-# CHECK-NEXT: 1 2 0.50 add z21.b, p5/m, z21.b, z10.b
-# CHECK-NEXT: 1 2 0.50 add z21.b, z10.b, z21.b
-# CHECK-NEXT: 1 2 0.50 add z21.d, p5/m, z21.d, z10.d
-# CHECK-NEXT: 1 2 0.50 add z21.d, z10.d, z21.d
-# CHECK-NEXT: 1 2 0.50 add z21.h, p5/m, z21.h, z10.h
-# CHECK-NEXT: 1 2 0.50 add z21.h, z10.h, z21.h
-# CHECK-NEXT: 1 2 0.50 add z21.s, p5/m, z21.s, z10.s
-# CHECK-NEXT: 1 2 0.50 add z21.s, z10.s, z21.s
-# CHECK-NEXT: 1 2 0.50 add z23.b, p3/m, z23.b, z13.b
-# CHECK-NEXT: 1 2 0.50 add z23.b, z13.b, z8.b
-# CHECK-NEXT: 1 2 0.50 add z23.d, p3/m, z23.d, z13.d
-# CHECK-NEXT: 1 2 0.50 add z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 add z23.h, p3/m, z23.h, z13.h
-# CHECK-NEXT: 1 2 0.50 add z23.h, z13.h, z8.h
-# CHECK-NEXT: 1 2 0.50 add z23.s, p3/m, z23.s, z13.s
-# CHECK-NEXT: 1 2 0.50 add z23.s, z13.s, z8.s
-# CHECK-NEXT: 1 2 0.50 add z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 add z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 add z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 add z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 add z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 add z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 add z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 add z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 add z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 add z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 add z31.s, z31.s, #65280
-# CHECK-NEXT: 1 2 0.50 add z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 1.00 addpl sp, sp, #31
-# CHECK-NEXT: 1 2 1.00 addpl x0, x0, #-32
-# CHECK-NEXT: 1 2 1.00 addpl x21, x21, #0
-# CHECK-NEXT: 1 2 1.00 addpl x23, x8, #-1
-# CHECK-NEXT: 1 2 1.00 addvl sp, sp, #31
-# CHECK-NEXT: 1 2 1.00 addvl x0, x0, #-32
-# CHECK-NEXT: 1 2 1.00 addvl x21, x21, #0
-# CHECK-NEXT: 1 2 1.00 addvl x23, x8, #-1
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, lsl #1]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, lsl #2]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, lsl #3]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, sxtw #1]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, sxtw #2]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, sxtw #3]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, sxtw]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, uxtw #1]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, uxtw #2]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, uxtw #3]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d, uxtw]
-# CHECK-NEXT: 1 2 0.50 adr z0.d, [z0.d, z0.d]
-# CHECK-NEXT: 1 2 0.50 adr z0.s, [z0.s, z0.s, lsl #1]
-# CHECK-NEXT: 1 2 0.50 adr z0.s, [z0.s, z0.s, lsl #2]
-# CHECK-NEXT: 1 2 0.50 adr z0.s, [z0.s, z0.s, lsl #3]
-# CHECK-NEXT: 1 2 0.50 adr z0.s, [z0.s, z0.s]
-# CHECK-NEXT: 1 1 1.00 and p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 1 2 0.50 and z0.d, z0.d, #0x6
-# CHECK-NEXT: 1 2 0.50 and z0.d, z0.d, #0xfffffffffffffff9
-# CHECK-NEXT: 1 2 0.50 and z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 and z0.s, z0.s, #0x6
-# CHECK-NEXT: 1 2 0.50 and z0.s, z0.s, #0xfffffff9
-# CHECK-NEXT: 1 2 0.50 and z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 and z23.h, z23.h, #0x6
-# CHECK-NEXT: 1 2 0.50 and z23.h, z23.h, #0xfff9
-# CHECK-NEXT: 1 2 0.50 and z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 and z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 and z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 and z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 and z5.b, z5.b, #0x6
-# CHECK-NEXT: 1 2 0.50 and z5.b, z5.b, #0xf9
-# CHECK-NEXT: 2 2 2.00 ands p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 4 12 2.00 andv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 andv d0, p7, z31.d
-# CHECK-NEXT: 4 12 2.00 andv h0, p7, z31.h
-# CHECK-NEXT: 4 12 2.00 andv s0, p7, z31.s
-# CHECK-NEXT: 1 2 1.00 asr z0.b, p0/m, z0.b, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 asr z0.b, p0/m, z0.b, z1.d
-# CHECK-NEXT: 1 2 1.00 asr z0.b, z0.b, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.b, z1.b, z2.d
-# CHECK-NEXT: 1 2 1.00 asr z0.d, p0/m, z0.d, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 asr z0.d, z0.d, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.h, p0/m, z0.h, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 asr z0.h, p0/m, z0.h, z1.d
-# CHECK-NEXT: 1 2 1.00 asr z0.h, z0.h, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.h, z1.h, z2.d
-# CHECK-NEXT: 1 2 1.00 asr z0.s, p0/m, z0.s, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 1.00 asr z0.s, p0/m, z0.s, z1.d
-# CHECK-NEXT: 1 2 1.00 asr z0.s, z0.s, #1
-# CHECK-NEXT: 1 2 1.00 asr z0.s, z1.s, z2.d
-# CHECK-NEXT: 1 2 1.00 asr z31.b, p0/m, z31.b, #8
-# CHECK-NEXT: 1 2 1.00 asr z31.b, z31.b, #8
-# CHECK-NEXT: 1 2 1.00 asr z31.d, p0/m, z31.d, #64
-# CHECK-NEXT: 1 2 1.00 asr z31.d, z31.d, #64
-# CHECK-NEXT: 1 2 1.00 asr z31.h, p0/m, z31.h, #16
-# CHECK-NEXT: 1 2 1.00 asr z31.h, z31.h, #16
-# CHECK-NEXT: 1 2 1.00 asr z31.s, p0/m, z31.s, #32
-# CHECK-NEXT: 1 2 1.00 asr z31.s, z31.s, #32
-# CHECK-NEXT: 1 4 1.00 asrd z0.b, p0/m, z0.b, #1
-# CHECK-NEXT: 1 4 1.00 asrd z0.d, p0/m, z0.d, #1
-# CHECK-NEXT: 1 4 1.00 asrd z0.h, p0/m, z0.h, #1
-# CHECK-NEXT: 1 4 1.00 asrd z0.s, p0/m, z0.s, #1
-# CHECK-NEXT: 1 4 1.00 asrd z31.b, p0/m, z31.b, #8
-# CHECK-NEXT: 1 4 1.00 asrd z31.d, p0/m, z31.d, #64
-# CHECK-NEXT: 1 4 1.00 asrd z31.h, p0/m, z31.h, #16
-# CHECK-NEXT: 1 4 1.00 asrd z31.s, p0/m, z31.s, #32
-# CHECK-NEXT: 1 2 1.00 asrr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 asrr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 asrr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 asrr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 4 1.00 bfcvt z0.h, p0/m, z1.s
-# CHECK-NEXT: 1 4 1.00 bfcvtnt z0.h, p0/m, z1.s
-# CHECK-NEXT: 1 4 0.50 bfdot z0.s, z1.h, z2.h
-# CHECK-NEXT: 1 4 0.50 bfdot z0.s, z1.h, z2.h[0]
-# CHECK-NEXT: 1 4 0.50 bfdot z0.s, z1.h, z2.h[3]
-# CHECK-NEXT: 1 5 0.50 bfmlalb z0.s, z1.h, z2.h
-# CHECK-NEXT: 1 5 0.50 bfmlalb z0.s, z1.h, z2.h[0]
-# CHECK-NEXT: 1 5 0.50 bfmlalb z0.s, z1.h, z2.h[7]
-# CHECK-NEXT: 1 5 0.50 bfmlalb z10.s, z21.h, z14.h
-# CHECK-NEXT: 1 5 0.50 bfmlalb z21.s, z14.h, z3.h[2]
-# CHECK-NEXT: 1 5 0.50 bfmlalt z0.s, z1.h, z2.h
-# CHECK-NEXT: 1 5 0.50 bfmlalt z0.s, z1.h, z2.h[0]
-# CHECK-NEXT: 1 5 0.50 bfmlalt z0.s, z1.h, z2.h[7]
-# CHECK-NEXT: 1 5 0.50 bfmlalt z0.s, z1.h, z7.h[7]
-# CHECK-NEXT: 1 5 0.50 bfmlalt z14.s, z10.h, z21.h
-# CHECK-NEXT: 1 5 0.50 bfmmla z0.s, z1.h, z2.h
-# CHECK-NEXT: 1 1 1.00 bic p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 1 1 1.00 bic p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 2 0.50 bic z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 bic z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 bic z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 bic z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 bic z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 bic z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 2 2 2.00 bics p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 2 2 2.00 bics p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 brka p0.b, p15/m, p15.b
-# CHECK-NEXT: 1 2 1.00 brka p0.b, p15/z, p15.b
-# CHECK-NEXT: 2 3 2.00 brkas p0.b, p15/z, p15.b
-# CHECK-NEXT: 1 2 1.00 brkb p0.b, p15/m, p15.b
-# CHECK-NEXT: 1 2 1.00 brkb p0.b, p15/z, p15.b
-# CHECK-NEXT: 2 3 2.00 brkbs p0.b, p15/z, p15.b
-# CHECK-NEXT: 1 2 1.00 brkn p0.b, p15/z, p1.b, p0.b
-# CHECK-NEXT: 1 2 1.00 brkn p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 3 2.00 brkns p0.b, p15/z, p1.b, p0.b
-# CHECK-NEXT: 2 3 2.00 brkns p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 brkpa p0.b, p15/z, p1.b, p2.b
-# CHECK-NEXT: 1 2 1.00 brkpa p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 3 2.00 brkpas p0.b, p15/z, p1.b, p2.b
-# CHECK-NEXT: 2 3 2.00 brkpas p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 brkpb p0.b, p15/z, p1.b, p2.b
-# CHECK-NEXT: 1 2 1.00 brkpb p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 3 2.00 brkpbs p0.b, p15/z, p1.b, p2.b
-# CHECK-NEXT: 2 3 2.00 brkpbs p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 3 1.00 clasta b0, p7, b0, z31.b
-# CHECK-NEXT: 1 3 1.00 clasta d0, p7, d0, z31.d
-# CHECK-NEXT: 1 3 1.00 clasta h0, p7, h0, z31.h
-# CHECK-NEXT: 1 3 1.00 clasta s0, p7, s0, z31.s
-# CHECK-NEXT: 2 9 1.00 clasta w0, p7, w0, z31.b
-# CHECK-NEXT: 2 9 1.00 clasta w0, p7, w0, z31.h
-# CHECK-NEXT: 2 9 1.00 clasta w0, p7, w0, z31.s
-# CHECK-NEXT: 2 9 1.00 clasta x0, p7, x0, z31.d
-# CHECK-NEXT: 1 3 1.00 clasta z0.b, p7, z0.b, z31.b
-# CHECK-NEXT: 1 3 1.00 clasta z0.d, p7, z0.d, z31.d
-# CHECK-NEXT: 1 3 1.00 clasta z0.h, p7, z0.h, z31.h
-# CHECK-NEXT: 1 3 1.00 clasta z0.s, p7, z0.s, z31.s
-# CHECK-NEXT: 1 3 1.00 clastb b0, p7, b0, z31.b
-# CHECK-NEXT: 1 3 1.00 clastb d0, p7, d0, z31.d
-# CHECK-NEXT: 1 3 1.00 clastb h0, p7, h0, z31.h
-# CHECK-NEXT: 1 3 1.00 clastb s0, p7, s0, z31.s
-# CHECK-NEXT: 2 9 1.00 clastb w0, p7, w0, z31.b
-# CHECK-NEXT: 2 9 1.00 clastb w0, p7, w0, z31.h
-# CHECK-NEXT: 2 9 1.00 clastb w0, p7, w0, z31.s
-# CHECK-NEXT: 2 9 1.00 clastb x0, p7, x0, z31.d
-# CHECK-NEXT: 1 3 1.00 clastb z0.b, p7, z0.b, z31.b
-# CHECK-NEXT: 1 3 1.00 clastb z0.d, p7, z0.d, z31.d
-# CHECK-NEXT: 1 3 1.00 clastb z0.h, p7, z0.h, z31.h
-# CHECK-NEXT: 1 3 1.00 clastb z0.s, p7, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 cls z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 cls z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 cls z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 cls z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 clz z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 clz z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 clz z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 clz z31.s, p7/m, z31.s
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpeq p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmpge p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmpge p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmpge p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpge p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpge p0.b, p0/z, z1.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpge p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmpge p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmpge p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpge p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpge p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmpge p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmpge p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpge p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpge p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpge p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmpge p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmpge p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpge p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmpge p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.b, p0/z, z1.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmpgt p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmphi p0.b, p0/z, z0.b, #0
-# CHECK-NEXT: 2 4 1.00 cmphi p0.b, p0/z, z0.b, #127
-# CHECK-NEXT: 2 4 1.00 cmphi p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmphi p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphi p0.b, p0/z, z1.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmphi p0.d, p0/z, z0.d, #0
-# CHECK-NEXT: 2 4 1.00 cmphi p0.d, p0/z, z0.d, #127
-# CHECK-NEXT: 2 4 1.00 cmphi p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphi p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphi p0.h, p0/z, z0.h, #0
-# CHECK-NEXT: 2 4 1.00 cmphi p0.h, p0/z, z0.h, #127
-# CHECK-NEXT: 2 4 1.00 cmphi p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphi p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmphi p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmphi p0.s, p0/z, z0.s, #0
-# CHECK-NEXT: 2 4 1.00 cmphi p0.s, p0/z, z0.s, #127
-# CHECK-NEXT: 2 4 1.00 cmphi p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphi p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmphi p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmphs p0.b, p0/z, z0.b, #0
-# CHECK-NEXT: 2 4 1.00 cmphs p0.b, p0/z, z0.b, #127
-# CHECK-NEXT: 2 4 1.00 cmphs p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmphs p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphs p0.b, p0/z, z1.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmphs p0.d, p0/z, z0.d, #0
-# CHECK-NEXT: 2 4 1.00 cmphs p0.d, p0/z, z0.d, #127
-# CHECK-NEXT: 2 4 1.00 cmphs p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphs p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphs p0.h, p0/z, z0.h, #0
-# CHECK-NEXT: 2 4 1.00 cmphs p0.h, p0/z, z0.h, #127
-# CHECK-NEXT: 2 4 1.00 cmphs p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphs p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmphs p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmphs p0.s, p0/z, z0.s, #0
-# CHECK-NEXT: 2 4 1.00 cmphs p0.s, p0/z, z0.s, #127
-# CHECK-NEXT: 2 4 1.00 cmphs p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmphs p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmphs p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 2 4 1.00 cmple p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmple p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmple p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmple p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmple p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmple p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmple p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmple p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmple p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmple p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmple p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplo p0.b, p0/z, z0.b, #0
-# CHECK-NEXT: 2 4 1.00 cmplo p0.b, p0/z, z0.b, #127
-# CHECK-NEXT: 2 4 1.00 cmplo p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplo p0.d, p0/z, z0.d, #0
-# CHECK-NEXT: 2 4 1.00 cmplo p0.d, p0/z, z0.d, #127
-# CHECK-NEXT: 2 4 1.00 cmplo p0.h, p0/z, z0.h, #0
-# CHECK-NEXT: 2 4 1.00 cmplo p0.h, p0/z, z0.h, #127
-# CHECK-NEXT: 2 4 1.00 cmplo p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplo p0.s, p0/z, z0.s, #0
-# CHECK-NEXT: 2 4 1.00 cmplo p0.s, p0/z, z0.s, #127
-# CHECK-NEXT: 2 4 1.00 cmplo p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpls p0.b, p0/z, z0.b, #0
-# CHECK-NEXT: 2 4 1.00 cmpls p0.b, p0/z, z0.b, #127
-# CHECK-NEXT: 2 4 1.00 cmpls p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpls p0.d, p0/z, z0.d, #0
-# CHECK-NEXT: 2 4 1.00 cmpls p0.d, p0/z, z0.d, #127
-# CHECK-NEXT: 2 4 1.00 cmpls p0.h, p0/z, z0.h, #0
-# CHECK-NEXT: 2 4 1.00 cmpls p0.h, p0/z, z0.h, #127
-# CHECK-NEXT: 2 4 1.00 cmpls p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpls p0.s, p0/z, z0.s, #0
-# CHECK-NEXT: 2 4 1.00 cmpls p0.s, p0/z, z0.s, #127
-# CHECK-NEXT: 2 4 1.00 cmpls p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplt p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmplt p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmplt p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplt p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmplt p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmplt p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmplt p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmplt p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmplt p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmplt p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmplt p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpne p0.b, p0/z, z0.b, #-16
-# CHECK-NEXT: 2 4 1.00 cmpne p0.b, p0/z, z0.b, #15
-# CHECK-NEXT: 2 4 1.00 cmpne p0.b, p0/z, z0.b, z0.b
-# CHECK-NEXT: 2 4 1.00 cmpne p0.b, p0/z, z0.b, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpne p0.d, p0/z, z0.d, #-16
-# CHECK-NEXT: 2 4 1.00 cmpne p0.d, p0/z, z0.d, #15
-# CHECK-NEXT: 2 4 1.00 cmpne p0.d, p0/z, z0.d, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpne p0.h, p0/z, z0.h, #-16
-# CHECK-NEXT: 2 4 1.00 cmpne p0.h, p0/z, z0.h, #15
-# CHECK-NEXT: 2 4 1.00 cmpne p0.h, p0/z, z0.h, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpne p0.h, p0/z, z0.h, z0.h
-# CHECK-NEXT: 2 4 1.00 cmpne p0.s, p0/z, z0.s, #-16
-# CHECK-NEXT: 2 4 1.00 cmpne p0.s, p0/z, z0.s, #15
-# CHECK-NEXT: 2 4 1.00 cmpne p0.s, p0/z, z0.s, z0.d
-# CHECK-NEXT: 2 4 1.00 cmpne p0.s, p0/z, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 cnot z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 cnot z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 cnot z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 cnot z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 cnt z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 cnt z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 cnt z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 cnt z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 cntb x0
-# CHECK-NEXT: 1 2 1.00 cntb x0, #28
-# CHECK-NEXT: 1 2 1.00 cntb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 cntb x0, pow2
-# CHECK-NEXT: 1 2 1.00 cntd x0
-# CHECK-NEXT: 1 2 1.00 cntd x0, #28
-# CHECK-NEXT: 1 2 1.00 cntd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 cntd x0, pow2
-# CHECK-NEXT: 1 2 1.00 cnth x0
-# CHECK-NEXT: 1 2 1.00 cnth x0, #28
-# CHECK-NEXT: 1 2 1.00 cnth x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 cnth x0, pow2
-# CHECK-NEXT: 1 2 1.00 cntp x0, p15, p0.b
-# CHECK-NEXT: 1 2 1.00 cntp x0, p15, p0.d
-# CHECK-NEXT: 1 2 1.00 cntp x0, p15, p0.h
-# CHECK-NEXT: 1 2 1.00 cntp x0, p15, p0.s
-# CHECK-NEXT: 1 2 1.00 cntw x0
-# CHECK-NEXT: 1 2 1.00 cntw x0, #28
-# CHECK-NEXT: 1 2 1.00 cntw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 cntw x0, pow2
-# CHECK-NEXT: 1 3 1.00 compact z31.d, p7, z31.d
-# CHECK-NEXT: 1 3 1.00 compact z31.s, p7, z31.s
-# CHECK-NEXT: 2 5 1.00 mov z31.b, p7/m, w0
-# CHECK-NEXT: 2 5 1.00 mov z31.d, p7/m, sp
-# CHECK-NEXT: 2 5 1.00 mov z31.h, p7/m, w0
-# CHECK-NEXT: 2 5 1.00 mov z31.s, p7/m, wsp
-# CHECK-NEXT: 1 1 1.00 ctermeq w30, wzr
-# CHECK-NEXT: 1 1 1.00 ctermeq wzr, w30
-# CHECK-NEXT: 1 1 1.00 ctermeq x30, xzr
-# CHECK-NEXT: 1 1 1.00 ctermeq xzr, x30
-# CHECK-NEXT: 1 1 1.00 ctermne w30, wzr
-# CHECK-NEXT: 1 1 1.00 ctermne wzr, w30
-# CHECK-NEXT: 1 1 1.00 ctermne x30, xzr
-# CHECK-NEXT: 1 1 1.00 ctermne xzr, x30
-# CHECK-NEXT: 1 2 1.00 decb x0
-# CHECK-NEXT: 1 2 1.00 decb x0, #14
-# CHECK-NEXT: 1 2 1.00 decb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 decb x0, pow2
-# CHECK-NEXT: 1 2 1.00 decb x0, vl1
-# CHECK-NEXT: 1 2 1.00 decd x0
-# CHECK-NEXT: 1 2 1.00 decd x0, #14
-# CHECK-NEXT: 1 2 1.00 decd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 decd x0, pow2
-# CHECK-NEXT: 1 2 1.00 decd x0, vl1
-# CHECK-NEXT: 1 2 1.00 dech x0
-# CHECK-NEXT: 1 2 1.00 dech x0, #14
-# CHECK-NEXT: 1 2 1.00 dech x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 dech x0, pow2
-# CHECK-NEXT: 1 2 1.00 dech x0, vl1
-# CHECK-NEXT: 1 2 1.00 decp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 decp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 decp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 decp x0, p0.s
-# CHECK-NEXT: 1 2 1.00 decp xzr, p15.b
-# CHECK-NEXT: 1 2 1.00 decp xzr, p15.d
-# CHECK-NEXT: 1 2 1.00 decp xzr, p15.h
-# CHECK-NEXT: 1 2 1.00 decp xzr, p15.s
-# CHECK-NEXT: 1 2 1.00 decd z19.d
-# CHECK-NEXT: 3 7 2.00 decp z31.d, p15.d
-# CHECK-NEXT: 1 2 1.00 dech z23.h
-# CHECK-NEXT: 3 7 2.00 decp z31.h, p15.h
-# CHECK-NEXT: 3 7 2.00 decp z31.s, p15.s
-# CHECK-NEXT: 1 2 1.00 decw z8.s
-# CHECK-NEXT: 1 2 1.00 decw x0
-# CHECK-NEXT: 1 2 1.00 decw x0, #14
-# CHECK-NEXT: 1 2 1.00 decw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 decw x0, pow2
-# CHECK-NEXT: 1 2 1.00 decw x0, vl1
-# CHECK-NEXT: 1 2 0.50 mov z0.b, #0
-# CHECK-NEXT: 1 2 0.50 mov z0.d, #256
-# CHECK-NEXT: 1 2 0.50 mov z31.h, #127
-# CHECK-NEXT: 1 2 0.50 mov z31.s, #512
-# CHECK-NEXT: 1 3 1.00 mov z0.b, w0
-# CHECK-NEXT: 1 3 1.00 mov z0.d, x0
-# CHECK-NEXT: 1 3 1.00 mov z31.h, wsp
-# CHECK-NEXT: 1 3 1.00 mov z31.s, wsp
-# CHECK-NEXT: 1 2 0.50 dupm z0.d, #0xfffffffffffffff9
-# CHECK-NEXT: 1 2 0.50 dupm z0.s, #0xfffffff9
-# CHECK-NEXT: 1 2 0.50 dupm z23.h, #0xfff9
-# CHECK-NEXT: 1 2 0.50 dupm z5.b, #0xf9
-# CHECK-NEXT: 1 1 1.00 eor p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 1 2 0.50 eor z0.d, z0.d, #0x6
-# CHECK-NEXT: 1 2 0.50 eor z0.d, z0.d, #0xfffffffffffffff9
-# CHECK-NEXT: 1 2 0.50 eor z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 eor z0.s, z0.s, #0x6
-# CHECK-NEXT: 1 2 0.50 eor z0.s, z0.s, #0xfffffff9
-# CHECK-NEXT: 1 2 0.50 eor z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 eor z23.h, z23.h, #0x6
-# CHECK-NEXT: 1 2 0.50 eor z23.h, z23.h, #0xfff9
-# CHECK-NEXT: 1 2 0.50 eor z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 eor z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 eor z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 eor z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 eor z5.b, z5.b, #0x6
-# CHECK-NEXT: 1 2 0.50 eor z5.b, z5.b, #0xf9
-# CHECK-NEXT: 2 2 2.00 eors p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 4 12 2.00 eorv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 eorv d0, p7, z31.d
-# CHECK-NEXT: 4 12 2.00 eorv h0, p7, z31.h
-# CHECK-NEXT: 4 12 2.00 eorv s0, p7, z31.s
-# CHECK-NEXT: 1 2 0.50 ext z31.b, z31.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 ext z31.b, z31.b, z0.b, #255
-# CHECK-NEXT: 1 2 0.50 fabd z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fabd z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fabd z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fabs z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 fabs z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 fabs z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 facge p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 facge p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 facge p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 facgt p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 facgt p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 facgt p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 1 2 0.50 fadd z0.d, p0/m, z0.d, #0.5
-# CHECK-NEXT: 1 2 0.50 fadd z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fadd z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fadd z0.h, p0/m, z0.h, #0.5
-# CHECK-NEXT: 1 2 0.50 fadd z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fadd z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fadd z0.s, p0/m, z0.s, #0.5
-# CHECK-NEXT: 1 2 0.50 fadd z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fadd z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fadd z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fadd z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fadd z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 3 8 1.50 fadda d0, p7, d0, z31.d
-# CHECK-NEXT: 18 19 18.00 fadda h0, p7, h0, z31.h
-# CHECK-NEXT: 10 11 10.00 fadda s0, p7, s0, z31.s
-# CHECK-NEXT: 5 9 2.00 faddv d0, p7, z31.d
-# CHECK-NEXT: 6 13 3.00 faddv h0, p7, z31.h
-# CHECK-NEXT: 6 11 2.50 faddv s0, p7, z31.s
-# CHECK-NEXT: 1 3 0.50 fcadd z0.d, p0/m, z0.d, z0.d, #90
-# CHECK-NEXT: 1 3 0.50 fcadd z0.h, p0/m, z0.h, z0.h, #90
-# CHECK-NEXT: 1 3 0.50 fcadd z0.s, p0/m, z0.s, z0.s, #90
-# CHECK-NEXT: 1 3 0.50 fcadd z31.d, p7/m, z31.d, z31.d, #270
-# CHECK-NEXT: 1 3 0.50 fcadd z31.h, p7/m, z31.h, z31.h, #270
-# CHECK-NEXT: 1 3 0.50 fcadd z31.s, p7/m, z31.s, z31.s, #270
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmeq p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 fcmge p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 fcmge p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 fcmge p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.d, p0/z, z1.d, z0.d
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.h, p0/z, z1.h, z0.h
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 fcmgt p0.s, p0/z, z1.s, z0.s
-# CHECK-NEXT: 1 5 0.50 fcmla z0.d, p0/m, z0.d, z0.d, #0
-# CHECK-NEXT: 1 5 0.50 fcmla z0.d, p0/m, z1.d, z2.d, #90
-# CHECK-NEXT: 1 5 0.50 fcmla z0.h, p0/m, z0.h, z0.h, #0
-# CHECK-NEXT: 1 5 0.50 fcmla z0.h, p0/m, z1.h, z2.h, #90
-# CHECK-NEXT: 1 5 0.50 fcmla z0.h, z0.h, z0.h[0], #0
-# CHECK-NEXT: 1 5 0.50 fcmla z0.s, p0/m, z0.s, z0.s, #0
-# CHECK-NEXT: 1 5 0.50 fcmla z0.s, p0/m, z1.s, z2.s, #90
-# CHECK-NEXT: 1 5 0.50 fcmla z21.s, z10.s, z5.s[1], #90
-# CHECK-NEXT: 1 5 0.50 fcmla z23.s, z13.s, z8.s[0], #270
-# CHECK-NEXT: 1 5 0.50 fcmla z29.d, p7/m, z30.d, z31.d, #180
-# CHECK-NEXT: 1 5 0.50 fcmla z29.h, p7/m, z30.h, z31.h, #180
-# CHECK-NEXT: 1 5 0.50 fcmla z29.s, p7/m, z30.s, z31.s, #180
-# CHECK-NEXT: 1 5 0.50 fcmla z31.d, p7/m, z31.d, z31.d, #270
-# CHECK-NEXT: 1 5 0.50 fcmla z31.h, p7/m, z31.h, z31.h, #270
-# CHECK-NEXT: 1 5 0.50 fcmla z31.h, z31.h, z7.h[3], #270
-# CHECK-NEXT: 1 5 0.50 fcmla z31.s, p7/m, z31.s, z31.s, #270
-# CHECK-NEXT: 1 2 1.00 fcmle p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmle p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmle p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmlt p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmlt p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmlt p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmne p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmne p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, #0.0
-# CHECK-NEXT: 1 2 1.00 fcmne p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 2 1.00 fcmuo p0.d, p0/z, z0.d, z1.d
-# CHECK-NEXT: 1 2 1.00 fcmuo p0.h, p0/z, z0.h, z1.h
-# CHECK-NEXT: 1 2 1.00 fcmuo p0.s, p0/z, z0.s, z1.s
-# CHECK-NEXT: 1 3 1.00 fcvt z0.d, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvt z0.d, p0/m, z0.s
-# CHECK-NEXT: 1 3 1.00 fcvt z0.h, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 fcvt z0.h, p0/m, z0.s
-# CHECK-NEXT: 1 3 1.00 fcvt z0.s, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 fcvt z0.s, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvtzs z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 3 1.00 fcvtzs z0.d, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvtzs z0.d, p0/m, z0.s
-# CHECK-NEXT: 4 6 4.00 fcvtzs z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvtzs z0.s, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 fcvtzs z0.s, p0/m, z0.h
-# CHECK-NEXT: 2 4 2.00 fcvtzs z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 3 1.00 fcvtzu z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 3 1.00 fcvtzu z0.d, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvtzu z0.d, p0/m, z0.s
-# CHECK-NEXT: 4 6 4.00 fcvtzu z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 3 1.00 fcvtzu z0.s, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 fcvtzu z0.s, p0/m, z0.h
-# CHECK-NEXT: 2 4 2.00 fcvtzu z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 15 7.00 fdiv z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 13 10.00 fdiv z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 10 7.00 fdiv z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 15 7.00 fdivr z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 13 10.00 fdivr z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 10 7.00 fdivr z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 3 0.50 fexpa z0.d, z31.d
-# CHECK-NEXT: 1 3 0.50 fexpa z0.h, z31.h
-# CHECK-NEXT: 1 3 0.50 fexpa z0.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fmad z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fmad z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fmad z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fmax z0.d, p0/m, z0.d, #0.0
-# CHECK-NEXT: 1 2 0.50 fmax z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fmax z0.h, p0/m, z0.h, #0.0
-# CHECK-NEXT: 1 2 0.50 fmax z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fmax z0.s, p0/m, z0.s, #0.0
-# CHECK-NEXT: 1 2 0.50 fmax z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fmax z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fmax z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fmax z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.d, p0/m, z0.d, #0.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.h, p0/m, z0.h, #0.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.s, p0/m, z0.s, #0.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fmaxnm z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fmaxnm z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 5 9 2.00 fmaxnmv d0, p7, z31.d
-# CHECK-NEXT: 6 13 3.00 fmaxnmv h0, p7, z31.h
-# CHECK-NEXT: 6 11 2.50 fmaxnmv s0, p7, z31.s
-# CHECK-NEXT: 5 9 2.00 fmaxv d0, p7, z31.d
-# CHECK-NEXT: 6 13 3.00 fmaxv h0, p7, z31.h
-# CHECK-NEXT: 6 11 2.50 fmaxv s0, p7, z31.s
-# CHECK-NEXT: 1 2 0.50 fmin z0.d, p0/m, z0.d, #0.0
-# CHECK-NEXT: 1 2 0.50 fmin z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fmin z0.h, p0/m, z0.h, #0.0
-# CHECK-NEXT: 1 2 0.50 fmin z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fmin z0.s, p0/m, z0.s, #0.0
-# CHECK-NEXT: 1 2 0.50 fmin z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fmin z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fmin z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fmin z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 1 2 0.50 fminnm z0.d, p0/m, z0.d, #0.0
-# CHECK-NEXT: 1 2 0.50 fminnm z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fminnm z0.h, p0/m, z0.h, #0.0
-# CHECK-NEXT: 1 2 0.50 fminnm z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fminnm z0.s, p0/m, z0.s, #0.0
-# CHECK-NEXT: 1 2 0.50 fminnm z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fminnm z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fminnm z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fminnm z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 5 9 2.00 fminnmv d0, p7, z31.d
-# CHECK-NEXT: 6 13 3.00 fminnmv h0, p7, z31.h
-# CHECK-NEXT: 6 11 2.50 fminnmv s0, p7, z31.s
-# CHECK-NEXT: 5 9 2.00 fminv d0, p7, z31.d
-# CHECK-NEXT: 6 13 3.00 fminv h0, p7, z31.h
-# CHECK-NEXT: 6 11 2.50 fminv s0, p7, z31.s
-# CHECK-NEXT: 1 4 0.50 fmla z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fmla z0.d, z1.d, z7.d[1]
-# CHECK-NEXT: 1 4 0.50 fmla z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fmla z0.h, z1.h, z7.h[7]
-# CHECK-NEXT: 1 4 0.50 fmla z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fmla z0.s, z1.s, z7.s[3]
-# CHECK-NEXT: 1 4 0.50 fmls z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fmls z0.d, z1.d, z7.d[1]
-# CHECK-NEXT: 1 4 0.50 fmls z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fmls z0.h, z1.h, z7.h[7]
-# CHECK-NEXT: 1 4 0.50 fmls z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fmls z0.s, z1.s, z7.s[3]
-# CHECK-NEXT: 1 2 0.50 fmov z0.d, #-10.00000000
-# CHECK-NEXT: 1 2 0.50 fmov z0.d, #0.12500000
-# CHECK-NEXT: 1 2 0.50 fmov z0.d, p0/m, #-10.00000000
-# CHECK-NEXT: 1 2 0.50 fmov z0.d, p0/m, #0.12500000
-# CHECK-NEXT: 1 2 0.50 fmov z0.h, #-0.12500000
-# CHECK-NEXT: 1 2 0.50 fmov z0.h, p0/m, #-0.12500000
-# CHECK-NEXT: 1 2 0.50 fmov z0.s, #-0.12500000
-# CHECK-NEXT: 1 2 0.50 fmov z0.s, p0/m, #-0.12500000
-# CHECK-NEXT: 1 4 0.50 fmsb z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fmsb z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fmsb z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 3 0.50 fmul z0.d, p0/m, z0.d, #0.5
-# CHECK-NEXT: 1 3 0.50 fmul z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 3 0.50 fmul z0.d, z0.d, z0.d[0]
-# CHECK-NEXT: 1 3 0.50 fmul z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 3 0.50 fmul z0.h, p0/m, z0.h, #0.5
-# CHECK-NEXT: 1 3 0.50 fmul z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 3 0.50 fmul z0.h, z0.h, z0.h[0]
-# CHECK-NEXT: 1 3 0.50 fmul z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 3 0.50 fmul z0.s, p0/m, z0.s, #0.5
-# CHECK-NEXT: 1 3 0.50 fmul z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 3 0.50 fmul z0.s, z0.s, z0.s[0]
-# CHECK-NEXT: 1 3 0.50 fmul z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 3 0.50 fmul z31.d, p7/m, z31.d, #2.0
-# CHECK-NEXT: 1 3 0.50 fmul z31.d, z31.d, z15.d[1]
-# CHECK-NEXT: 1 3 0.50 fmul z31.h, p7/m, z31.h, #2.0
-# CHECK-NEXT: 1 3 0.50 fmul z31.h, z31.h, z7.h[7]
-# CHECK-NEXT: 1 3 0.50 fmul z31.s, p7/m, z31.s, #2.0
-# CHECK-NEXT: 1 3 0.50 fmul z31.s, z31.s, z7.s[3]
-# CHECK-NEXT: 1 3 0.50 fmulx z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 3 0.50 fmulx z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 3 0.50 fmulx z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fneg z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 fneg z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 fneg z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 4 0.50 fnmad z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fnmad z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fnmad z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fnmla z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fnmla z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fnmla z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fnmls z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fnmls z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fnmls z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 4 0.50 fnmsb z0.d, p7/m, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 fnmsb z0.h, p7/m, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 fnmsb z0.s, p7/m, z1.s, z31.s
-# CHECK-NEXT: 1 3 1.00 frecpe z0.d, z31.d
-# CHECK-NEXT: 4 6 4.00 frecpe z0.h, z31.h
-# CHECK-NEXT: 2 4 2.00 frecpe z0.s, z31.s
-# CHECK-NEXT: 1 4 0.50 frecps z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 frecps z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 frecps z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 3 1.00 frecpx z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 3 1.00 frecpx z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 3 1.00 frecpx z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frinta z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frinta z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frinta z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frinti z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frinti z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frinti z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frintm z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frintm z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frintm z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frintn z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frintn z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frintn z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frintp z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frintp z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frintp z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frintx z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frintx z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frintx z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frintz z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 6 1.00 frintz z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 4 1.00 frintz z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 3 1.00 frsqrte z0.d, z31.d
-# CHECK-NEXT: 4 6 4.00 frsqrte z0.h, z31.h
-# CHECK-NEXT: 2 4 2.00 frsqrte z0.s, z31.s
-# CHECK-NEXT: 1 4 0.50 frsqrts z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 4 0.50 frsqrts z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 4 0.50 frsqrts z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 3 0.50 fscale z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 3 0.50 fscale z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 3 0.50 fscale z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 16 7.00 fsqrt z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 13 10.00 fsqrt z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 10 7.00 fsqrt z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 fsub z0.d, p0/m, z0.d, #0.5
-# CHECK-NEXT: 1 2 0.50 fsub z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fsub z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fsub z0.h, p0/m, z0.h, #0.5
-# CHECK-NEXT: 1 2 0.50 fsub z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fsub z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fsub z0.s, p0/m, z0.s, #0.5
-# CHECK-NEXT: 1 2 0.50 fsub z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fsub z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fsub z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fsub z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fsub z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 1 2 0.50 fsubr z0.d, p0/m, z0.d, #0.5
-# CHECK-NEXT: 1 2 0.50 fsubr z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 fsubr z0.h, p0/m, z0.h, #0.5
-# CHECK-NEXT: 1 2 0.50 fsubr z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 fsubr z0.s, p0/m, z0.s, #0.5
-# CHECK-NEXT: 1 2 0.50 fsubr z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 fsubr z31.d, p7/m, z31.d, #1.0
-# CHECK-NEXT: 1 2 0.50 fsubr z31.h, p7/m, z31.h, #1.0
-# CHECK-NEXT: 1 2 0.50 fsubr z31.s, p7/m, z31.s, #1.0
-# CHECK-NEXT: 1 3 0.50 ftmad z0.d, z0.d, z31.d, #7
-# CHECK-NEXT: 1 3 0.50 ftmad z0.h, z0.h, z31.h, #7
-# CHECK-NEXT: 1 3 0.50 ftmad z0.s, z0.s, z31.s, #7
-# CHECK-NEXT: 1 3 0.50 ftsmul z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 3 0.50 ftsmul z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 3 0.50 ftsmul z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 3 0.50 ftssel z0.d, z1.d, z31.d
-# CHECK-NEXT: 1 3 0.50 ftssel z0.h, z1.h, z31.h
-# CHECK-NEXT: 1 3 0.50 ftssel z0.s, z1.s, z31.s
-# CHECK-NEXT: 1 2 1.00 incb x0
-# CHECK-NEXT: 1 2 1.00 incb x0, #14
-# CHECK-NEXT: 1 2 1.00 incb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 incb x0, pow2
-# CHECK-NEXT: 1 2 1.00 incb x0, vl1
-# CHECK-NEXT: 1 2 1.00 incd x0
-# CHECK-NEXT: 1 2 1.00 incd x0, #14
-# CHECK-NEXT: 1 2 1.00 incd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 incd x0, pow2
-# CHECK-NEXT: 1 2 1.00 incd x0, vl1
-# CHECK-NEXT: 1 2 1.00 incd z0.d
-# CHECK-NEXT: 1 2 1.00 incd z0.d, all, mul #16
-# CHECK-NEXT: 1 2 1.00 inch x0
-# CHECK-NEXT: 1 2 1.00 inch x0, #14
-# CHECK-NEXT: 1 2 1.00 inch x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 inch x0, pow2
-# CHECK-NEXT: 1 2 1.00 inch x0, vl1
-# CHECK-NEXT: 1 2 1.00 inch z0.h
-# CHECK-NEXT: 1 2 1.00 inch z0.h, all, mul #16
-# CHECK-NEXT: 1 2 1.00 incp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 incp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 incp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 incp x0, p0.s
-# CHECK-NEXT: 1 2 1.00 incp xzr, p15.b
-# CHECK-NEXT: 1 2 1.00 incp xzr, p15.d
-# CHECK-NEXT: 1 2 1.00 incp xzr, p15.h
-# CHECK-NEXT: 1 2 1.00 incp xzr, p15.s
-# CHECK-NEXT: 3 7 2.00 incp z31.d, p15.d
-# CHECK-NEXT: 3 7 2.00 incp z31.h, p15.h
-# CHECK-NEXT: 3 7 2.00 incp z31.s, p15.s
-# CHECK-NEXT: 1 2 1.00 incw x0
-# CHECK-NEXT: 1 2 1.00 incw x0, #14
-# CHECK-NEXT: 1 2 1.00 incw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 incw x0, pow2
-# CHECK-NEXT: 1 2 1.00 incw x0, vl1
-# CHECK-NEXT: 1 2 1.00 incw z0.s
-# CHECK-NEXT: 1 2 1.00 incw z0.s, all, mul #16
-# CHECK-NEXT: 1 4 1.00 index z0.b, #0, #0
-# CHECK-NEXT: 2 5 2.00 index z0.d, #0, #0
-# CHECK-NEXT: 1 4 1.00 index z0.h, #0, #0
-# CHECK-NEXT: 2 7 1.00 index z0.h, w0, w0
-# CHECK-NEXT: 1 4 1.00 index z0.s, #0, #0
-# CHECK-NEXT: 2 7 1.00 index z21.b, w10, w21
-# CHECK-NEXT: 4 8 2.00 index z21.d, x10, x21
-# CHECK-NEXT: 2 7 1.00 index z21.s, w10, w21
-# CHECK-NEXT: 2 7 1.00 index z23.b, #13, w8
-# CHECK-NEXT: 2 7 1.00 index z23.b, w13, #8
-# CHECK-NEXT: 4 8 2.00 index z23.d, #13, x8
-# CHECK-NEXT: 4 8 2.00 index z23.d, x13, #8
-# CHECK-NEXT: 2 7 1.00 index z23.h, #13, w8
-# CHECK-NEXT: 2 7 1.00 index z23.h, w13, #8
-# CHECK-NEXT: 2 7 1.00 index z23.s, #13, w8
-# CHECK-NEXT: 2 7 1.00 index z23.s, w13, #8
-# CHECK-NEXT: 1 4 1.00 index z31.b, #-1, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.b, #-1, wzr
-# CHECK-NEXT: 2 7 1.00 index z31.b, wzr, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.b, wzr, wzr
-# CHECK-NEXT: 2 5 2.00 index z31.d, #-1, #-1
-# CHECK-NEXT: 4 8 2.00 index z31.d, #-1, xzr
-# CHECK-NEXT: 4 8 2.00 index z31.d, xzr, #-1
-# CHECK-NEXT: 4 8 2.00 index z31.d, xzr, xzr
-# CHECK-NEXT: 1 4 1.00 index z31.h, #-1, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.h, #-1, wzr
-# CHECK-NEXT: 2 7 1.00 index z31.h, wzr, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.h, wzr, wzr
-# CHECK-NEXT: 1 4 1.00 index z31.s, #-1, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.s, #-1, wzr
-# CHECK-NEXT: 2 7 1.00 index z31.s, wzr, #-1
-# CHECK-NEXT: 2 7 1.00 index z31.s, wzr, wzr
-# CHECK-NEXT: 2 6 1.00 insr z0.b, w0
-# CHECK-NEXT: 2 6 1.00 insr z0.d, x0
-# CHECK-NEXT: 2 6 1.00 insr z0.h, w0
-# CHECK-NEXT: 2 6 1.00 insr z0.s, w0
-# CHECK-NEXT: 1 3 1.00 insr z31.b, b31
-# CHECK-NEXT: 2 6 1.00 insr z31.b, wzr
-# CHECK-NEXT: 1 3 1.00 insr z31.d, d31
-# CHECK-NEXT: 2 6 1.00 insr z31.d, xzr
-# CHECK-NEXT: 1 3 1.00 insr z31.h, h31
-# CHECK-NEXT: 2 6 1.00 insr z31.h, wzr
-# CHECK-NEXT: 1 3 1.00 insr z31.s, s31
-# CHECK-NEXT: 2 6 1.00 insr z31.s, wzr
-# CHECK-NEXT: 1 3 1.00 lasta b0, p7, z31.b
-# CHECK-NEXT: 1 3 1.00 lasta d0, p7, z31.d
-# CHECK-NEXT: 1 3 1.00 lasta h0, p7, z31.h
-# CHECK-NEXT: 1 3 1.00 lasta s0, p7, z31.s
-# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.b
-# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.h
-# CHECK-NEXT: 2 6 1.00 lasta w0, p7, z31.s
-# CHECK-NEXT: 2 6 1.00 lasta x0, p7, z31.d
-# CHECK-NEXT: 1 3 1.00 lastb b0, p7, z31.b
-# CHECK-NEXT: 1 3 1.00 lastb d0, p7, z31.d
-# CHECK-NEXT: 1 3 1.00 lastb h0, p7, z31.h
-# CHECK-NEXT: 1 3 1.00 lastb s0, p7, z31.s
-# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.b
-# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.h
-# CHECK-NEXT: 2 6 1.00 lastb w0, p7, z31.s
-# CHECK-NEXT: 2 6 1.00 lastb x0, p7, z31.d
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.b }, p0/z, [sp, x0]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.b }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1b { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 2 9 0.33 * ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 2 11 0.33 * ld1b { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z21.b }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z21.s }, p5/z, [x10, x21]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z23.d }, p3/z, [x13, x8]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1b { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1b { z31.d }, p7/z, [z31.d, #31]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 11 0.33 * ld1b { z31.s }, p7/z, [z31.s, #31]
-# CHECK-NEXT: 1 6 0.50 * ld1b { z5.h }, p3/z, [x17, x16]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
-# CHECK-NEXT: 1 6 0.50 * ld1d { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 1 6 0.50 * ld1d { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1d { z23.d }, p3/z, [sp, x8, lsl #3]
-# CHECK-NEXT: 1 6 0.50 * ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
-# CHECK-NEXT: 1 6 0.50 * ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1d { z31.d }, p7/z, [z31.d, #248]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 2 9 0.33 * ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 2 11 0.33 * ld1h { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 2 7 0.50 * ld1h { z21.s }, p5/z, [x10, x21, lsl #1]
-# CHECK-NEXT: 2 7 0.50 * ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1h { z31.d }, p7/z, [z31.d, #62]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 11 0.67 * ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
-# CHECK-NEXT: 4 11 0.67 * ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
-# CHECK-NEXT: 2 11 0.33 * ld1h { z31.s }, p7/z, [z31.s, #62]
-# CHECK-NEXT: 2 7 0.50 * ld1h { z5.h }, p3/z, [sp, x16, lsl #1]
-# CHECK-NEXT: 2 7 0.50 * ld1h { z5.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z0.b }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z31.b }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z31.d }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z31.h }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rb { z31.s }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rd { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rd { z31.d }, p7/z, [sp, #504]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z31.d }, p7/z, [sp, #126]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z31.h }, p7/z, [sp, #126]
-# CHECK-NEXT: 1 6 0.50 * ld1rh { z31.s }, p7/z, [sp, #126]
-# CHECK-NEXT: 1 6 0.50 * ld1rqb { z0.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rqb { z0.b }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rqb { z21.b }, p5/z, [x10, #112]
-# CHECK-NEXT: 1 6 0.50 * ld1rqb { z23.b }, p3/z, [x13, #-128]
-# CHECK-NEXT: 1 6 0.50 * ld1rqb { z31.b }, p7/z, [sp, #-16]
-# CHECK-NEXT: 1 6 0.50 * ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 1 6 0.50 * ld1rqd { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rqd { z23.d }, p3/z, [x13, #-128]
-# CHECK-NEXT: 1 6 0.50 * ld1rqd { z23.d }, p3/z, [x13, #112]
-# CHECK-NEXT: 1 6 0.50 * ld1rqd { z31.d }, p7/z, [sp, #-16]
-# CHECK-NEXT: 2 7 0.50 * ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ld1rqh { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rqh { z23.h }, p3/z, [x13, #-128]
-# CHECK-NEXT: 1 6 0.50 * ld1rqh { z23.h }, p3/z, [x13, #112]
-# CHECK-NEXT: 1 6 0.50 * ld1rqh { z31.h }, p7/z, [sp, #-16]
-# CHECK-NEXT: 1 6 0.50 * ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1rqw { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rqw { z23.s }, p3/z, [x13, #-128]
-# CHECK-NEXT: 1 6 0.50 * ld1rqw { z23.s }, p3/z, [x13, #112]
-# CHECK-NEXT: 1 6 0.50 * ld1rqw { z31.s }, p7/z, [sp, #-16]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z31.d }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z31.h }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rsb { z31.s }, p7/z, [sp, #63]
-# CHECK-NEXT: 1 6 0.50 * ld1rsh { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsh { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsh { z31.d }, p7/z, [sp, #126]
-# CHECK-NEXT: 1 6 0.50 * ld1rsh { z31.s }, p7/z, [sp, #126]
-# CHECK-NEXT: 1 6 0.50 * ld1rsw { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rsw { z31.d }, p7/z, [sp, #252]
-# CHECK-NEXT: 1 6 0.50 * ld1rw { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rw { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ld1rw { z31.d }, p7/z, [sp, #252]
-# CHECK-NEXT: 1 6 0.50 * ld1rw { z31.s }, p7/z, [sp, #252]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1sb { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z0.h }, p0/z, [sp, x0]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z0.h }, p0/z, [x0, x0]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 2 9 0.33 * ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 2 11 0.33 * ld1sb { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z21.s }, p5/z, [x10, x21]
-# CHECK-NEXT: 2 9 0.33 * ld1sb { z23.s }, p5/z, [x17, z10.s, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z23.d }, p3/z, [x13, x8]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sb { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1sb { z31.d }, p7/z, [z31.d, #31]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 11 0.33 * ld1sb { z31.s }, p7/z, [z31.s, #31]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 9 0.33 * ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 2 11 0.33 * ld1sh { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 2 7 0.50 * ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 2 7 0.50 * ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]
-# CHECK-NEXT: 2 7 0.50 * ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1sh { z31.d }, p7/z, [z31.d, #62]
-# CHECK-NEXT: 1 6 0.50 * ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 11 0.67 * ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
-# CHECK-NEXT: 4 11 0.67 * ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
-# CHECK-NEXT: 2 11 0.33 * ld1sh { z31.s }, p7/z, [z31.s, #62]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
-# CHECK-NEXT: 1 6 0.50 * ld1sw { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 1 6 0.50 * ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1sw { z31.d }, p7/z, [z31.d, #124]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 9 0.33 * ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 2 11 0.33 * ld1w { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z21.s }, p5/z, [sp, x21, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z21.s }, p5/z, [x10, x21, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 4 9 0.67 * ld1w { z31.d }, p7/z, [z31.d, #124]
-# CHECK-NEXT: 1 6 0.50 * ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 11 0.67 * ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
-# CHECK-NEXT: 4 11 0.67 * ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
-# CHECK-NEXT: 2 11 0.33 * ld1w { z31.s }, p7/z, [z31.s, #124]
-# CHECK-NEXT: 4 9 1.00 * ld2b { z0.b, z1.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 4 8 1.00 * ld2b { z0.b, z1.b }, p0/z, [x0]
-# CHECK-NEXT: 4 8 1.00 * ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
-# CHECK-NEXT: 4 8 1.00 * ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
-# CHECK-NEXT: 4 9 1.00 * ld2b { z5.b, z6.b }, p3/z, [x17, x16]
-# CHECK-NEXT: 4 9 1.00 * ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 4 8 1.00 * ld2d { z0.d, z1.d }, p0/z, [x0]
-# CHECK-NEXT: 4 8 1.00 * ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
-# CHECK-NEXT: 4 8 1.00 * ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
-# CHECK-NEXT: 4 9 1.00 * ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT: 4 10 1.00 * ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 4 8 1.00 * ld2h { z0.h, z1.h }, p0/z, [x0]
-# CHECK-NEXT: 4 8 1.00 * ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
-# CHECK-NEXT: 4 8 1.00 * ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
-# CHECK-NEXT: 4 10 1.00 * ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT: 4 9 1.00 * ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 4 8 1.00 * ld2w { z0.s, z1.s }, p0/z, [x0]
-# CHECK-NEXT: 4 8 1.00 * ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
-# CHECK-NEXT: 4 8 1.00 * ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
-# CHECK-NEXT: 4 9 1.00 * ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT: 7 8 1.50 * ld3b { z0.b - z2.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 6 11 1.50 * ld3b { z0.b - z2.b }, p0/z, [x0]
-# CHECK-NEXT: 6 11 1.50 * ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT: 6 11 1.50 * ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT: 7 8 1.50 * ld3b { z5.b - z7.b }, p3/z, [x17, x16]
-# CHECK-NEXT: 7 8 1.50 * ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 6 11 1.50 * ld3d { z0.d - z2.d }, p0/z, [x0]
-# CHECK-NEXT: 6 11 1.50 * ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT: 6 11 1.50 * ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT: 7 8 1.50 * ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT: 7 8 1.50 * ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 6 11 1.50 * ld3h { z0.h - z2.h }, p0/z, [x0]
-# CHECK-NEXT: 6 11 1.50 * ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT: 6 11 1.50 * ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT: 7 8 1.50 * ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT: 7 8 1.50 * ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 6 11 1.50 * ld3w { z0.s - z2.s }, p0/z, [x0]
-# CHECK-NEXT: 6 11 1.50 * ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
-# CHECK-NEXT: 6 11 1.50 * ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
-# CHECK-NEXT: 7 8 1.50 * ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT: 10 13 2.00 * ld4b { z0.b - z3.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 8 12 2.00 * ld4b { z0.b - z3.b }, p0/z, [x0]
-# CHECK-NEXT: 8 12 2.00 * ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT: 8 12 2.00 * ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT: 10 13 2.00 * ld4b { z5.b - z8.b }, p3/z, [x17, x16]
-# CHECK-NEXT: 10 13 2.00 * ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 8 12 2.00 * ld4d { z0.d - z3.d }, p0/z, [x0]
-# CHECK-NEXT: 8 12 2.00 * ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT: 8 12 2.00 * ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT: 10 13 2.00 * ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
-# CHECK-NEXT: 10 13 2.00 * ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 8 12 2.00 * ld4h { z0.h - z3.h }, p0/z, [x0]
-# CHECK-NEXT: 8 12 2.00 * ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT: 8 12 2.00 * ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT: 10 13 2.00 * ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
-# CHECK-NEXT: 10 13 2.00 * ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 8 12 2.00 * ld4w { z0.s - z3.s }, p0/z, [x0]
-# CHECK-NEXT: 8 12 2.00 * ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
-# CHECK-NEXT: 8 12 2.00 * ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
-# CHECK-NEXT: 10 13 2.00 * ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z0.d }, p0/z, [x0, x0]
-# CHECK-NEXT: 4 9 0.67 * U ldff1b { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z0.h }, p0/z, [x0, x0]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z0.s }, p0/z, [x0, x0]
-# CHECK-NEXT: 2 9 0.33 * U ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * U ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 11 0.33 * U ldff1b { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 4 9 0.67 * U ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z31.b }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1b { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1b { z31.d }, p7/z, [z31.d, #31]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z31.h }, p7/z, [sp]
-# CHECK-NEXT: 2 6 0.50 * U ldff1b { z31.s }, p7/z, [sp]
-# CHECK-NEXT: 2 11 0.33 * U ldff1b { z31.s }, p7/z, [z31.s, #31]
-# CHECK-NEXT: 2 6 0.50 * U ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1d { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1d { z31.d }, p7/z, [z31.d, #248]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 9 0.33 * U ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * U ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 11 0.33 * U ldff1h { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1h { z31.d }, p7/z, [z31.d, #62]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z31.h }, p7/z, [sp]
-# CHECK-NEXT: 4 11 0.67 * U ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
-# CHECK-NEXT: 4 11 0.67 * U ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
-# CHECK-NEXT: 2 7 0.50 * U ldff1h { z31.s }, p7/z, [sp]
-# CHECK-NEXT: 2 11 0.33 * U ldff1h { z31.s }, p7/z, [z31.s, #62]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z0.d }, p0/z, [x0, x0]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sb { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z0.h }, p0/z, [x0, x0]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z0.s }, p0/z, [x0, x0]
-# CHECK-NEXT: 2 9 0.33 * U ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * U ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 11 0.33 * U ldff1sb { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sb { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sb { z31.d }, p7/z, [z31.d, #31]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z31.h }, p7/z, [sp]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sb { z31.s }, p7/z, [sp]
-# CHECK-NEXT: 2 11 0.33 * U ldff1sb { z31.s }, p7/z, [z31.s, #31]
-# CHECK-NEXT: 2 7 0.50 * U ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 7 0.50 * U ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 9 0.33 * U ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * U ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 11 0.33 * U ldff1sh { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 7 0.50 * U ldff1sh { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sh { z31.d }, p7/z, [z31.d, #62]
-# CHECK-NEXT: 4 11 0.67 * U ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
-# CHECK-NEXT: 4 11 0.67 * U ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
-# CHECK-NEXT: 2 7 0.50 * U ldff1sh { z31.s }, p7/z, [sp]
-# CHECK-NEXT: 2 11 0.33 * U ldff1sh { z31.s }, p7/z, [z31.s, #62]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1sw { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1sw { z31.d }, p7/z, [z31.d, #124]
-# CHECK-NEXT: 2 6 0.50 * U ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z0.d }, p0/z, [z0.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 2 9 0.33 * U ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
-# CHECK-NEXT: 2 9 0.33 * U ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 11 0.33 * U ldff1w { z0.s }, p0/z, [z0.s]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z31.d }, p7/z, [sp, z31.d]
-# CHECK-NEXT: 2 6 0.50 * U ldff1w { z31.d }, p7/z, [sp]
-# CHECK-NEXT: 4 9 0.67 * U ldff1w { z31.d }, p7/z, [z31.d, #124]
-# CHECK-NEXT: 4 11 0.67 * U ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
-# CHECK-NEXT: 4 11 0.67 * U ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
-# CHECK-NEXT: 2 6 0.50 * U ldff1w { z31.s }, p7/z, [sp]
-# CHECK-NEXT: 2 11 0.33 * U ldff1w { z31.s }, p7/z, [z31.s, #124]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z0.b }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1d { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sw { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 1 6 0.50 * U ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 6 0.50 * ldnt1b { z0.b }, p0/z, [x0, x0]
-# CHECK-NEXT: 1 6 0.50 * ldnt1b { z0.b }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 6 0.50 * ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
-# CHECK-NEXT: 1 6 0.50 * ldnt1d { z0.d }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 7 0.50 * ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
-# CHECK-NEXT: 1 6 0.50 * ldnt1h { z0.h }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 6 0.50 * ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
-# CHECK-NEXT: 1 6 0.50 * ldnt1w { z0.s }, p0/z, [x0]
-# CHECK-NEXT: 1 6 0.50 * ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 6 0.50 * ldr p0, [x0]
-# CHECK-NEXT: 2 6 0.50 * ldr p5, [x10, #255, mul vl]
-# CHECK-NEXT: 2 6 0.50 * ldr p7, [x13, #-256, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldr z0, [x0]
-# CHECK-NEXT: 1 6 0.50 * ldr z23, [x13, #255, mul vl]
-# CHECK-NEXT: 1 6 0.50 * ldr z31, [sp, #-256, mul vl]
-# CHECK-NEXT: 1 2 1.00 lsl z0.b, p0/m, z0.b, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 lsl z0.b, p0/m, z0.b, z1.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.b, z1.b, z2.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.d, p0/m, z0.d, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.h, p0/m, z0.h, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 lsl z0.h, p0/m, z0.h, z1.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.h, z1.h, z2.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.s, p0/m, z0.s, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 1.00 lsl z0.s, p0/m, z0.s, z1.d
-# CHECK-NEXT: 1 2 1.00 lsl z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 1.00 lsl z0.s, z1.s, z2.d
-# CHECK-NEXT: 1 2 1.00 lsl z31.b, p0/m, z31.b, #7
-# CHECK-NEXT: 1 2 1.00 lsl z31.b, z31.b, #7
-# CHECK-NEXT: 1 2 1.00 lsl z31.d, p0/m, z31.d, #63
-# CHECK-NEXT: 1 2 1.00 lsl z31.d, z31.d, #63
-# CHECK-NEXT: 1 2 1.00 lsl z31.h, p0/m, z31.h, #15
-# CHECK-NEXT: 1 2 1.00 lsl z31.h, z31.h, #15
-# CHECK-NEXT: 1 2 1.00 lsl z31.s, p0/m, z31.s, #31
-# CHECK-NEXT: 1 2 1.00 lsl z31.s, z31.s, #31
-# CHECK-NEXT: 1 2 1.00 lslr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 lslr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 lslr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 lslr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 1.00 lsr z0.b, p0/m, z0.b, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 lsr z0.b, p0/m, z0.b, z1.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.b, z0.b, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.b, z1.b, z2.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.d, p0/m, z0.d, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.d, z0.d, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.h, p0/m, z0.h, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 lsr z0.h, p0/m, z0.h, z1.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.h, z0.h, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.h, z1.h, z2.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.s, p0/m, z0.s, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 1.00 lsr z0.s, p0/m, z0.s, z1.d
-# CHECK-NEXT: 1 2 1.00 lsr z0.s, z0.s, #1
-# CHECK-NEXT: 1 2 1.00 lsr z0.s, z1.s, z2.d
-# CHECK-NEXT: 1 2 1.00 lsr z31.b, p0/m, z31.b, #8
-# CHECK-NEXT: 1 2 1.00 lsr z31.b, z31.b, #8
-# CHECK-NEXT: 1 2 1.00 lsr z31.d, p0/m, z31.d, #64
-# CHECK-NEXT: 1 2 1.00 lsr z31.d, z31.d, #64
-# CHECK-NEXT: 1 2 1.00 lsr z31.h, p0/m, z31.h, #16
-# CHECK-NEXT: 1 2 1.00 lsr z31.h, z31.h, #16
-# CHECK-NEXT: 1 2 1.00 lsr z31.s, p0/m, z31.s, #32
-# CHECK-NEXT: 1 2 1.00 lsr z31.s, z31.s, #32
-# CHECK-NEXT: 1 2 1.00 lsrr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 1.00 lsrr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 1.00 lsrr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 1.00 lsrr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 4 1.00 mad z17.b, p7/m, z4.b, z5.b
-# CHECK-NEXT: 1 4 1.00 mad z29.h, p4/m, z31.h, z18.h
-# CHECK-NEXT: 1 4 1.00 mad z7.s, p4/m, z5.s, z29.s
-# CHECK-NEXT: 2 5 2.00 mad z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 4 1.00 mla z1.b, p0/m, z3.b, z3.b
-# CHECK-NEXT: 1 4 1.00 mla z21.h, p2/m, z31.h, z30.h
-# CHECK-NEXT: 1 4 1.00 mla z24.s, p3/m, z11.s, z9.s
-# CHECK-NEXT: 2 5 2.00 mla z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 4 1.00 mls z11.b, p1/m, z28.b, z6.b
-# CHECK-NEXT: 1 4 1.00 mls z31.h, p0/m, z25.h, z24.h
-# CHECK-NEXT: 1 4 1.00 mls z1.s, p5/m, z7.s, z13.s
-# CHECK-NEXT: 2 5 2.00 mls z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 1 1.00 mov p0.b, p0.b
-# CHECK-NEXT: 1 1 1.00 mov p0.b, p0/m, p0.b
-# CHECK-NEXT: 1 1 1.00 mov p0.b, p0/z, p0.b
-# CHECK-NEXT: 1 1 1.00 mov p15.b, p15.b
-# CHECK-NEXT: 1 1 1.00 mov p15.b, p15/m, p15.b
-# CHECK-NEXT: 1 1 1.00 mov p15.b, p15/z, p15.b
-# CHECK-NEXT: 1 2 0.50 mov z0.b, #127
-# CHECK-NEXT: 1 2 0.50 mov z0.b, b0
-# CHECK-NEXT: 1 2 0.50 mov z0.b, p0/m, b0
-# CHECK-NEXT: 2 5 1.00 mov z0.b, p0/m, w0
-# CHECK-NEXT: 1 2 0.50 mov z0.b, p0/z, #127
-# CHECK-NEXT: 1 3 1.00 mov z0.b, w0
-# CHECK-NEXT: 1 2 0.50 mov z0.d, #0
-# CHECK-NEXT: 1 2 0.50 mov z0.d, #0xe0000000000003ff
-# CHECK-NEXT: 1 2 0.50 mov z0.d, #0xffffffffffff7fff
-# CHECK-NEXT: 1 2 0.50 mov z0.d, #32768
-# CHECK-NEXT: 1 2 0.50 mov z0.d, d0
-# CHECK-NEXT: 1 2 0.50 mov z0.d, p0/m, d0
-# CHECK-NEXT: 2 5 1.00 mov z0.d, p0/m, x0
-# CHECK-NEXT: 1 3 1.00 mov z0.d, x0
-# CHECK-NEXT: 1 2 0.50 mov z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 mov z0.h, #-256
-# CHECK-NEXT: 1 2 0.50 mov z0.h, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z0.h, #0
-# CHECK-NEXT: 1 2 0.50 mov z0.h, #32512
-# CHECK-NEXT: 1 2 0.50 mov z0.h, #32767
-# CHECK-NEXT: 1 2 0.50 mov z0.h, h0
-# CHECK-NEXT: 1 2 0.50 mov z0.h, p0/m, h0
-# CHECK-NEXT: 2 5 1.00 mov z0.h, p0/m, w0
-# CHECK-NEXT: 1 2 0.50 mov z0.h, p0/z, #32512
-# CHECK-NEXT: 1 3 1.00 mov z0.h, w0
-# CHECK-NEXT: 1 2 0.50 mov z0.q, q0
-# CHECK-NEXT: 1 2 0.50 mov z0.s, #0
-# CHECK-NEXT: 1 2 0.50 mov z0.s, #0xffff7fff
-# CHECK-NEXT: 1 2 0.50 mov z0.s, #32768
-# CHECK-NEXT: 1 2 0.50 mov z0.s, p0/m, s0
-# CHECK-NEXT: 2 5 1.00 mov z0.s, p0/m, w0
-# CHECK-NEXT: 1 2 0.50 mov z0.s, s0
-# CHECK-NEXT: 1 3 1.00 mov z0.s, w0
-# CHECK-NEXT: 1 2 0.50 mov z21.d, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.d, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.d, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.d, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p0/z, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p0/z, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p0/z, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p0/z, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p15/m, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.d, p15/m, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.h, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.h, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.h, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.h, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p0/z, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p0/z, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p0/z, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p0/z, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p15/m, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.h, p15/m, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.s, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.s, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.s, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.s, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p0/z, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p0/z, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p0/z, #127
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p0/z, #32512
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p15/m, #-128
-# CHECK-NEXT: 1 2 0.50 mov z21.s, p15/m, #-32768
-# CHECK-NEXT: 1 2 0.50 mov z31.b, p15/m, z31.b
-# CHECK-NEXT: 1 2 0.50 mov z31.b, p7/m, b31
-# CHECK-NEXT: 1 2 0.50 movprfx z31, z6
-# CHECK-NEXT: 2 5 1.00 mov z31.b, p7/m, wsp
-# CHECK-NEXT: 1 2 0.50 movprfx z31.b, p0/m, z4.b
-# CHECK-NEXT: 2 5 1.00 mov z31.b, p0/m, wsp
-# CHECK-NEXT: 1 2 0.50 mov z31.b, z31.b[63]
-# CHECK-NEXT: 1 2 0.50 mov z31.d, p15/m, z31.d
-# CHECK-NEXT: 1 2 0.50 mov z31.d, p7/m, d31
-# CHECK-NEXT: 1 2 0.50 movprfx z31.d, p7/z, z6.d
-# CHECK-NEXT: 2 5 1.00 mov z31.d, p7/m, sp
-# CHECK-NEXT: 1 3 1.00 mov z31.d, sp
-# CHECK-NEXT: 1 2 0.50 mov z31.d, z0.d
-# CHECK-NEXT: 1 2 0.50 mov z31.d, z31.d[7]
-# CHECK-NEXT: 1 2 0.50 mov z31.h, p15/m, z31.h
-# CHECK-NEXT: 1 2 0.50 mov z31.h, p7/m, h31
-# CHECK-NEXT: 2 5 1.00 mov z31.h, p7/m, wsp
-# CHECK-NEXT: 1 3 1.00 mov z31.h, wsp
-# CHECK-NEXT: 1 2 0.50 mov z31.h, z31.h[31]
-# CHECK-NEXT: 1 2 0.50 mov z31.s, p15/m, z31.s
-# CHECK-NEXT: 1 2 0.50 mov z31.s, p7/m, s31
-# CHECK-NEXT: 2 5 1.00 mov z31.s, p7/m, wsp
-# CHECK-NEXT: 1 3 1.00 mov z31.s, wsp
-# CHECK-NEXT: 1 2 0.50 mov z31.s, z31.s[15]
-# CHECK-NEXT: 1 2 0.50 mov z5.b, #-1
-# CHECK-NEXT: 1 2 0.50 mov z5.b, #-128
-# CHECK-NEXT: 1 2 0.50 mov z5.b, #127
-# CHECK-NEXT: 1 2 0.50 mov z5.b, p0/z, #-1
-# CHECK-NEXT: 1 2 0.50 mov z5.b, p0/z, #-128
-# CHECK-NEXT: 1 2 0.50 mov z5.b, p0/z, #127
-# CHECK-NEXT: 1 2 0.50 mov z5.b, p15/m, #-128
-# CHECK-NEXT: 1 2 0.50 mov z5.d, #-6
-# CHECK-NEXT: 1 2 0.50 mov z5.h, #-6
-# CHECK-NEXT: 1 2 0.50 mov z5.q, z17.q[3]
-# CHECK-NEXT: 1 2 0.50 mov z5.s, #-6
-# CHECK-NEXT: 2 2 2.00 movs p0.b, p0.b
-# CHECK-NEXT: 2 2 2.00 movs p0.b, p0/z, p0.b
-# CHECK-NEXT: 2 2 2.00 movs p15.b, p15.b
-# CHECK-NEXT: 2 2 2.00 movs p15.b, p15/z, p15.b
-# CHECK-NEXT: 1 1 0.07 U mrs x3, ID_AA64ZFR0_EL1
-# CHECK-NEXT: 1 1 0.07 U mrs x3, ZCR_EL1
-# CHECK-NEXT: 1 1 0.07 U mrs x3, ZCR_EL12
-# CHECK-NEXT: 1 1 0.07 U mrs x3, ZCR_EL2
-# CHECK-NEXT: 1 1 0.07 U mrs x3, ZCR_EL3
-# CHECK-NEXT: 1 1 0.07 U msr ZCR_EL1, x3
-# CHECK-NEXT: 2 5 2.00 msb z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 4 1.00 msb z18.b, p1/m, z27.b, z0.b
-# CHECK-NEXT: 1 4 1.00 msb z27.h, p5/m, z23.h, z1.h
-# CHECK-NEXT: 1 4 1.00 msb z26.s, p2/m, z0.s, z2.s
-# CHECK-NEXT: 1 1 0.07 U msr ZCR_EL12, x3
-# CHECK-NEXT: 1 1 0.07 U msr ZCR_EL2, x3
-# CHECK-NEXT: 1 1 0.07 U msr ZCR_EL3, x3
-# CHECK-NEXT: 1 4 1.00 mul z0.b, p7/m, z0.b, z31.b
-# CHECK-NEXT: 2 5 2.00 mul z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 4 1.00 mul z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 4 1.00 mul z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 4 1.00 mul z31.b, z31.b, #-128
-# CHECK-NEXT: 1 4 1.00 mul z31.b, z31.b, #127
-# CHECK-NEXT: 2 5 2.00 mul z31.d, z31.d, #-128
-# CHECK-NEXT: 2 5 2.00 mul z31.d, z31.d, #127
-# CHECK-NEXT: 1 4 1.00 mul z31.h, z31.h, #-128
-# CHECK-NEXT: 1 4 1.00 mul z31.h, z31.h, #127
-# CHECK-NEXT: 1 4 1.00 mul z31.s, z31.s, #-128
-# CHECK-NEXT: 1 4 1.00 mul z31.s, z31.s, #127
-# CHECK-NEXT: 1 1 1.00 nand p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 1 1 1.00 nand p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 2 2.00 nands p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 2 2 2.00 nands p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 2 0.50 neg z0.b, p0/m, z0.b
-# CHECK-NEXT: 1 2 0.50 neg z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 0.50 neg z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 2 0.50 neg z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 0.50 neg z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 neg z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 neg z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 neg z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 1 1.00 nor p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 1 1 1.00 nor p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 2 2.00 nors p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 2 2 2.00 nors p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 1 1.00 not p0.b, p0/z, p0.b
-# CHECK-NEXT: 1 1 1.00 not p15.b, p15/z, p15.b
-# CHECK-NEXT: 1 2 0.50 not z31.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 not z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 not z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 not z31.s, p7/m, z31.s
-# CHECK-NEXT: 2 2 2.00 nots p0.b, p0/z, p0.b
-# CHECK-NEXT: 2 2 2.00 nots p15.b, p15/z, p15.b
-# CHECK-NEXT: 1 1 1.00 orn p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 1 1 1.00 orn p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 2 2 2.00 orns p0.b, p0/z, p0.b, p0.b
-# CHECK-NEXT: 2 2 2.00 orns p15.b, p15/z, p15.b, p15.b
-# CHECK-NEXT: 1 1 1.00 orr p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 1 2 0.50 orr z0.d, z0.d, #0x6
-# CHECK-NEXT: 1 2 0.50 orr z0.d, z0.d, #0xfffffffffffffff9
-# CHECK-NEXT: 1 2 0.50 orr z0.s, z0.s, #0x6
-# CHECK-NEXT: 1 2 0.50 orr z0.s, z0.s, #0xfffffff9
-# CHECK-NEXT: 1 2 0.50 orr z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 orr z23.h, z23.h, #0x6
-# CHECK-NEXT: 1 2 0.50 orr z23.h, z23.h, #0xfff9
-# CHECK-NEXT: 1 2 0.50 orr z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 orr z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 orr z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 orr z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 orr z5.b, z5.b, #0x6
-# CHECK-NEXT: 1 2 0.50 orr z5.b, z5.b, #0xf9
-# CHECK-NEXT: 2 2 2.00 orrs p0.b, p0/z, p0.b, p1.b
-# CHECK-NEXT: 4 12 2.00 orv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 orv d0, p7, z31.d
-# CHECK-NEXT: 4 12 2.00 orv h0, p7, z31.h
-# CHECK-NEXT: 4 12 2.00 orv s0, p7, z31.s
-# CHECK-NEXT: 1 2 1.00 pfalse p15.b
-# CHECK-NEXT: 1 2 1.00 pfirst p0.b, p15, p0.b
-# CHECK-NEXT: 1 2 1.00 pfirst p15.b, p15, p15.b
-# CHECK-NEXT: 1 2 1.00 pnext p0.b, p15, p0.b
-# CHECK-NEXT: 1 2 1.00 pnext p0.d, p15, p0.d
-# CHECK-NEXT: 1 2 1.00 pnext p0.h, p15, p0.h
-# CHECK-NEXT: 1 2 1.00 pnext p0.s, p15, p0.s
-# CHECK-NEXT: 1 2 1.00 pnext p15.b, p15, p15.b
-# CHECK-NEXT: 1 4 0.50 * * U prfb #14, p5, [x21]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pldl1keep, p7, [x4, x9]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pldl3strm, p4, [x3, z15.s, uxtw]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pldl1strm, p7, [x28, z4.d, uxtw]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pstl3keep, p2, [x18, z19.d]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pstl3keep, p1, [z28.s]
-# CHECK-NEXT: 1 4 0.50 * * U prfb pstl2strm, p5, [z25.d]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pstl3strm, p3, [x21]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pstl2keep, p3, [x24, x24, lsl #3]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pstl1strm, p3, [x27, z27.s, sxtw #3]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pstl1keep, p0, [x21, z2.d, uxtw #3]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pldl1strm, p7, [x22, z22.d, lsl #3]
-# CHECK-NEXT: 1 4 0.50 * * U prfd pldl2strm, p1, [z2.s]
-# CHECK-NEXT: 1 4 0.50 * * U prfd #15, p1, [z17.d]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pldl2strm, p3, [x17]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pstl2keep, p1, [x28, x9, lsl #1]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pldl1strm, p6, [x0, z10.s, uxtw #1]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pldl3keep, p7, [x24, z21.d, uxtw #1]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pstl1strm, p5, [x10, z6.d, lsl #1]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pldl3strm, p6, [z0.s]
-# CHECK-NEXT: 1 4 0.50 * * U prfh pstl2keep, p2, [z21.d]
-# CHECK-NEXT: 1 4 0.33 U prfm pldl1strm, [x5]
-# CHECK-NEXT: 1 4 0.33 U prfm pldl1keep, [x25, x16]
-# CHECK-NEXT: 1 4 0.50 * * U prfw pldl2strm, p2, [x4]
-# CHECK-NEXT: 1 4 0.50 * * U prfw pstl1keep, p4, [x18, x21, lsl #2]
-# CHECK-NEXT: 1 4 0.50 * * U prfw pldl2strm, p0, [x15, z6.s, uxtw #2]
-# CHECK-NEXT: 1 4 0.50 * * U prfw pstl2keep, p0, [x27, z18.d, sxtw #2]
-# CHECK-NEXT: 1 4 0.50 * * U prfw pstl2keep, p3, [x19, z8.d, lsl #2]
-# CHECK-NEXT: 1 4 0.50 * * U prfw #7, p7, [z27.s]
-# CHECK-NEXT: 1 4 0.50 * * U prfw #7, p1, [z20.d]
-# CHECK-NEXT: 1 2 1.00 ptest p15, p0.b
-# CHECK-NEXT: 1 2 1.00 ptest p15, p15.b
-# CHECK-NEXT: 1 2 1.00 ptrue p0.b, pow2
-# CHECK-NEXT: 1 2 1.00 ptrue p0.d, pow2
-# CHECK-NEXT: 1 2 1.00 ptrue p0.h, pow2
-# CHECK-NEXT: 1 2 1.00 ptrue p0.s, pow2
-# CHECK-NEXT: 1 2 1.00 ptrue p15.b
-# CHECK-NEXT: 1 2 1.00 ptrue p15.d
-# CHECK-NEXT: 1 2 1.00 ptrue p15.h
-# CHECK-NEXT: 1 2 1.00 ptrue p15.s
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #14
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #15
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #16
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #17
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #18
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #19
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #20
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #21
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #22
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #23
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #24
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #25
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #26
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #27
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, #28
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, mul3
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, mul4
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl1
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl128
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl16
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl2
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl256
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl3
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl32
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl4
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl5
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl6
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl64
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl7
-# CHECK-NEXT: 1 2 1.00 ptrue p7.s, vl8
-# CHECK-NEXT: 2 3 2.00 ptrues p0.b, pow2
-# CHECK-NEXT: 2 3 2.00 ptrues p0.d, pow2
-# CHECK-NEXT: 2 3 2.00 ptrues p0.h, pow2
-# CHECK-NEXT: 2 3 2.00 ptrues p0.s, pow2
-# CHECK-NEXT: 2 3 2.00 ptrues p15.b
-# CHECK-NEXT: 2 3 2.00 ptrues p15.d
-# CHECK-NEXT: 2 3 2.00 ptrues p15.h
-# CHECK-NEXT: 2 3 2.00 ptrues p15.s
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #14
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #15
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #16
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #17
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #18
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #19
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #20
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #21
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #22
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #23
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #24
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #25
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #26
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #27
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, #28
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, mul3
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, mul4
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl1
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl128
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl16
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl2
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl256
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl3
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl32
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl4
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl5
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl6
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl64
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl7
-# CHECK-NEXT: 2 3 2.00 ptrues p7.s, vl8
-# CHECK-NEXT: 1 2 1.00 punpkhi p0.h, p0.b
-# CHECK-NEXT: 1 2 1.00 punpkhi p15.h, p15.b
-# CHECK-NEXT: 1 2 1.00 punpklo p0.h, p0.b
-# CHECK-NEXT: 1 2 1.00 punpklo p15.h, p15.b
-# CHECK-NEXT: 1 2 0.50 rbit z0.b, p7/m, z31.b
-# CHECK-NEXT: 1 2 0.50 rbit z0.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 rbit z0.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 rbit z0.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 * U rdffr p0.b
-# CHECK-NEXT: 2 3 2.00 * U rdffr p0.b, p0/z
-# CHECK-NEXT: 1 2 1.00 * U rdffr p15.b
-# CHECK-NEXT: 2 3 2.00 * U rdffr p15.b, p15/z
-# CHECK-NEXT: 1 4 0.50 U rdffrs p0.b, p0/z
-# CHECK-NEXT: 1 4 0.50 U rdffrs p15.b, p15/z
-# CHECK-NEXT: 1 2 1.00 rdvl x0, #0
-# CHECK-NEXT: 1 2 1.00 rdvl x21, #-32
-# CHECK-NEXT: 1 2 1.00 rdvl x23, #31
-# CHECK-NEXT: 1 2 1.00 rdvl xzr, #-1
-# CHECK-NEXT: 1 2 1.00 rev p1.h, p2.h
-# CHECK-NEXT: 1 2 0.50 rev z0.b, z31.b
-# CHECK-NEXT: 1 2 0.50 rev z0.d, z31.d
-# CHECK-NEXT: 1 2 0.50 rev z0.h, z31.h
-# CHECK-NEXT: 1 2 0.50 rev z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 revb z0.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 revb z0.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 0.50 revb z0.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 revh z0.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 revh z0.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 0.50 revw z0.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 sabd z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 sabd z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 sabd z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 sabd z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 5 14 2.00 saddv d0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 saddv d0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 saddv d0, p7, z31.s
-# CHECK-NEXT: 1 3 1.00 scvtf z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 3 1.00 scvtf z18.d, p3/m, z16.s
-# CHECK-NEXT: 4 6 4.00 scvtf z0.h, p0/m, z0.h
-# CHECK-NEXT: 2 4 2.00 scvtf z0.h, p0/m, z0.s
-# CHECK-NEXT: 1 3 1.00 scvtf z18.h, p1/m, z14.d
-# CHECK-NEXT: 1 3 1.00 scvtf z0.s, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 scvtf z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 20 7.00 sdiv z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 12 7.00 sdiv z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 20 7.00 sdivr z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 12 7.00 sdivr z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 4 1.00 sdot z0.d, z1.h, z15.h[1]
-# CHECK-NEXT: 1 4 1.00 sdot z0.d, z1.h, z31.h
-# CHECK-NEXT: 1 3 0.50 sdot z0.s, z1.b, z31.b
-# CHECK-NEXT: 1 3 0.50 sdot z0.s, z1.b, z7.b[3]
-# CHECK-NEXT: 1 2 0.50 sel z23.b, p11, z13.b, z8.b
-# CHECK-NEXT: 1 2 0.50 sel z23.d, p11, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 sel z23.h, p11, z13.h, z8.h
-# CHECK-NEXT: 1 2 0.50 sel z23.s, p11, z13.s, z8.s
-# CHECK-NEXT: 1 2 1.00 * U setffr
-# CHECK-NEXT: 1 2 0.50 smax z0.b, z0.b, #-128
-# CHECK-NEXT: 1 2 0.50 smax z0.d, z0.d, #-128
-# CHECK-NEXT: 1 2 0.50 smax z0.h, z0.h, #-128
-# CHECK-NEXT: 1 2 0.50 smax z0.s, z0.s, #-128
-# CHECK-NEXT: 1 2 0.50 smax z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 smax z31.b, z31.b, #127
-# CHECK-NEXT: 1 2 0.50 smax z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 smax z31.d, z31.d, #127
-# CHECK-NEXT: 1 2 0.50 smax z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 smax z31.h, z31.h, #127
-# CHECK-NEXT: 1 2 0.50 smax z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 smax z31.s, z31.s, #127
-# CHECK-NEXT: 5 14 2.00 smaxv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 smaxv h0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 smaxv s0, p7, z31.s
-# CHECK-NEXT: 2 8 0.50 smaxv d24, p5, z24.d
-# CHECK-NEXT: 1 2 0.50 smin z0.b, z0.b, #-128
-# CHECK-NEXT: 1 2 0.50 smin z0.d, z0.d, #-128
-# CHECK-NEXT: 1 2 0.50 smin z0.h, z0.h, #-128
-# CHECK-NEXT: 1 2 0.50 smin z0.s, z0.s, #-128
-# CHECK-NEXT: 1 2 0.50 smin z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 smin z31.b, z31.b, #127
-# CHECK-NEXT: 1 2 0.50 smin z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 smin z31.d, z31.d, #127
-# CHECK-NEXT: 1 2 0.50 smin z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 smin z31.h, z31.h, #127
-# CHECK-NEXT: 1 2 0.50 smin z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 smin z31.s, z31.s, #127
-# CHECK-NEXT: 5 14 2.00 sminv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 sminv h0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 sminv s0, p7, z31.s
-# CHECK-NEXT: 2 8 0.50 sminv d17, p2, z18.d
-# CHECK-NEXT: 1 3 0.50 smmla z0.s, z1.b, z2.b
-# CHECK-NEXT: 1 4 1.00 smulh z0.b, p7/m, z0.b, z31.b
-# CHECK-NEXT: 2 5 2.00 smulh z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 4 1.00 smulh z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 4 1.00 smulh z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 3 1.00 splice z31.b, p7, z31.b, z31.b
-# CHECK-NEXT: 1 3 1.00 splice z31.d, p7, z31.d, z31.d
-# CHECK-NEXT: 1 3 1.00 splice z31.h, p7, z31.h, z31.h
-# CHECK-NEXT: 1 3 1.00 splice z31.s, p7, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 sqadd z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 sqadd z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 sqadd z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 sqadd z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqadd z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 sqadd z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 sqadd z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqadd z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 sqadd z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 sqadd z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqadd z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 sqadd z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 sqadd z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 sqadd z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 sqadd z31.s, z31.s, #65280
-# CHECK-NEXT: 1 2 1.00 sqdecb x0
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, #14
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, w0
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecb x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecd x0
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, #14
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, w0
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecd x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecd z0.d
-# CHECK-NEXT: 1 2 1.00 sqdecd z0.d, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecd z0.d, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecd z0.d, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdech x0
-# CHECK-NEXT: 1 2 1.00 sqdech x0, #14
-# CHECK-NEXT: 1 2 1.00 sqdech x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdech x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdech x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqdech x0, w0
-# CHECK-NEXT: 1 2 1.00 sqdech x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdech x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdech x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdech z0.h
-# CHECK-NEXT: 1 2 1.00 sqdech z0.h, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdech z0.h, pow2
-# CHECK-NEXT: 1 2 1.00 sqdech z0.h, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 sqdecp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 sqdecp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 sqdecp x0, p0.s
-# CHECK-NEXT: 1 2 1.00 sqdecp xzr, p15.b, wzr
-# CHECK-NEXT: 1 2 1.00 sqdecp xzr, p15.d, wzr
-# CHECK-NEXT: 1 2 1.00 sqdecp xzr, p15.h, wzr
-# CHECK-NEXT: 1 2 1.00 sqdecp xzr, p15.s, wzr
-# CHECK-NEXT: 3 7 2.00 sqdecp z0.d, p0.d
-# CHECK-NEXT: 3 7 2.00 sqdecp z0.h, p0.h
-# CHECK-NEXT: 3 7 2.00 sqdecp z0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 sqdecw x0
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, #14
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, w0
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecw x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecw z0.s
-# CHECK-NEXT: 1 2 1.00 sqdecw z0.s, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqdecw z0.s, pow2
-# CHECK-NEXT: 1 2 1.00 sqdecw z0.s, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincb x0
-# CHECK-NEXT: 1 2 1.00 sqincb x0, #14
-# CHECK-NEXT: 1 2 1.00 sqincb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincb x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincb x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqincb x0, w0
-# CHECK-NEXT: 1 2 1.00 sqincb x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincb x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincb x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincd x0
-# CHECK-NEXT: 1 2 1.00 sqincd x0, #14
-# CHECK-NEXT: 1 2 1.00 sqincd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincd x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincd x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqincd x0, w0
-# CHECK-NEXT: 1 2 1.00 sqincd x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincd x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincd x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincd z0.d
-# CHECK-NEXT: 1 2 1.00 sqincd z0.d, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincd z0.d, pow2
-# CHECK-NEXT: 1 2 1.00 sqincd z0.d, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqinch x0
-# CHECK-NEXT: 1 2 1.00 sqinch x0, #14
-# CHECK-NEXT: 1 2 1.00 sqinch x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqinch x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqinch x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqinch x0, w0
-# CHECK-NEXT: 1 2 1.00 sqinch x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqinch x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqinch x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqinch z0.h
-# CHECK-NEXT: 1 2 1.00 sqinch z0.h, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqinch z0.h, pow2
-# CHECK-NEXT: 1 2 1.00 sqinch z0.h, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 sqincp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 sqincp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 sqincp x0, p0.s
-# CHECK-NEXT: 1 2 1.00 sqincp xzr, p15.b, wzr
-# CHECK-NEXT: 1 2 1.00 sqincp xzr, p15.d, wzr
-# CHECK-NEXT: 1 2 1.00 sqincp xzr, p15.h, wzr
-# CHECK-NEXT: 1 2 1.00 sqincp xzr, p15.s, wzr
-# CHECK-NEXT: 3 7 2.00 sqincp z0.d, p0.d
-# CHECK-NEXT: 3 7 2.00 sqincp z0.h, p0.h
-# CHECK-NEXT: 3 7 2.00 sqincp z0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 sqincw x0
-# CHECK-NEXT: 1 2 1.00 sqincw x0, #14
-# CHECK-NEXT: 1 2 1.00 sqincw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincw x0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincw x0, vl1
-# CHECK-NEXT: 1 2 1.00 sqincw x0, w0
-# CHECK-NEXT: 1 2 1.00 sqincw x0, w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincw x0, w0, pow2
-# CHECK-NEXT: 1 2 1.00 sqincw x0, w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincw z0.s
-# CHECK-NEXT: 1 2 1.00 sqincw z0.s, all, mul #16
-# CHECK-NEXT: 1 2 1.00 sqincw z0.s, pow2
-# CHECK-NEXT: 1 2 1.00 sqincw z0.s, pow2, mul #16
-# CHECK-NEXT: 1 2 0.50 sqsub z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 sqsub z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 sqsub z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 sqsub z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqsub z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 sqsub z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 sqsub z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqsub z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 sqsub z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 sqsub z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sqsub z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 sqsub z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 sqsub z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 sqsub z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 sqsub z31.s, z31.s, #65280
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.b }, p0, [x0, x0]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.b }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.d }, p0, [x0, x0]
-# CHECK-NEXT: 2 6 0.50 * st1b { z0.d }, p0, [x0, z0.d, sxtw]
-# CHECK-NEXT: 2 6 0.50 * st1b { z0.d }, p0, [x0, z0.d, uxtw]
-# CHECK-NEXT: 2 6 0.50 * st1b { z0.d }, p0, [x0, z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.d }, p0, [x0]
-# CHECK-NEXT: 2 6 0.50 * st1b { z0.d }, p7, [z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.h }, p0, [x0, x0]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.h }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.s }, p0, [x0, x0]
-# CHECK-NEXT: 4 10 1.00 * st1b { z0.s }, p0, [x0, z0.s, sxtw]
-# CHECK-NEXT: 4 10 1.00 * st1b { z0.s }, p0, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 2 0.50 * st1b { z0.s }, p0, [x0]
-# CHECK-NEXT: 4 10 1.00 * st1b { z0.s }, p7, [z0.s]
-# CHECK-NEXT: 2 2 0.50 * st1b { z21.b }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z21.d }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z21.h }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z21.s }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z31.b }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z31.d }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 6 0.50 * st1b { z31.d }, p7, [z31.d, #31]
-# CHECK-NEXT: 2 2 0.50 * st1b { z31.h }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1b { z31.s }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 10 1.00 * st1b { z31.s }, p7, [z31.s, #31]
-# CHECK-NEXT: 2 2 0.50 * st1d { z0.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d, lsl #3]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d, sxtw #3]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d, sxtw]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d, uxtw #3]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d, uxtw]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p0, [x0, z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1d { z0.d }, p0, [x0]
-# CHECK-NEXT: 2 6 0.50 * st1d { z0.d }, p7, [z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1d { z21.d }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1d { z31.d }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 6 0.50 * st1d { z31.d }, p7, [z31.d, #248]
-# CHECK-NEXT: 3 2 0.50 * st1h { z0.d }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d, lsl #1]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d, sxtw #1]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d, sxtw]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d, uxtw #1]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d, uxtw]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p0, [x0, z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1h { z0.d }, p0, [x0]
-# CHECK-NEXT: 2 6 0.50 * st1h { z0.d }, p7, [z0.d]
-# CHECK-NEXT: 3 2 0.50 * st1h { z0.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 2 0.50 * st1h { z0.h }, p0, [x0]
-# CHECK-NEXT: 3 2 0.50 * st1h { z0.s }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 4 10 1.00 * st1h { z0.s }, p0, [x0, z0.s, sxtw #1]
-# CHECK-NEXT: 4 10 1.00 * st1h { z0.s }, p0, [x0, z0.s, sxtw]
-# CHECK-NEXT: 4 10 1.00 * st1h { z0.s }, p0, [x0, z0.s, uxtw #1]
-# CHECK-NEXT: 4 10 1.00 * st1h { z0.s }, p0, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 2 0.50 * st1h { z0.s }, p0, [x0]
-# CHECK-NEXT: 4 10 1.00 * st1h { z0.s }, p7, [z0.s]
-# CHECK-NEXT: 2 2 0.50 * st1h { z21.d }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1h { z21.h }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1h { z21.s }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1h { z31.d }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 6 0.50 * st1h { z31.d }, p7, [z31.d, #62]
-# CHECK-NEXT: 2 2 0.50 * st1h { z31.h }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1h { z31.s }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 10 1.00 * st1h { z31.s }, p7, [z31.s, #62]
-# CHECK-NEXT: 2 2 0.50 * st1w { z0.d }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d, lsl #2]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d, sxtw #2]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d, sxtw]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d, uxtw #2]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d, uxtw]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p0, [x0, z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1w { z0.d }, p0, [x0]
-# CHECK-NEXT: 2 6 0.50 * st1w { z0.d }, p7, [z0.d]
-# CHECK-NEXT: 2 2 0.50 * st1w { z0.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 4 10 1.00 * st1w { z0.s }, p0, [x0, z0.s, sxtw #2]
-# CHECK-NEXT: 4 10 1.00 * st1w { z0.s }, p0, [x0, z0.s, sxtw]
-# CHECK-NEXT: 4 10 1.00 * st1w { z0.s }, p0, [x0, z0.s, uxtw #2]
-# CHECK-NEXT: 4 10 1.00 * st1w { z0.s }, p0, [x0, z0.s, uxtw]
-# CHECK-NEXT: 2 2 0.50 * st1w { z0.s }, p0, [x0]
-# CHECK-NEXT: 4 10 1.00 * st1w { z0.s }, p7, [z0.s]
-# CHECK-NEXT: 2 2 0.50 * st1w { z21.d }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1w { z21.s }, p5, [x10, #5, mul vl]
-# CHECK-NEXT: 2 2 0.50 * st1w { z31.d }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 2 6 0.50 * st1w { z31.d }, p7, [z31.d, #124]
-# CHECK-NEXT: 2 2 0.50 * st1w { z31.s }, p7, [sp, #-1, mul vl]
-# CHECK-NEXT: 4 10 1.00 * st1w { z31.s }, p7, [z31.s, #124]
-# CHECK-NEXT: 2 4 0.50 * st2b { z0.b, z1.b }, p0, [x0, x0]
-# CHECK-NEXT: 2 4 0.50 * st2b { z0.b, z1.b }, p0, [x0]
-# CHECK-NEXT: 2 4 0.50 * st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2b { z5.b, z6.b }, p3, [x17, x16]
-# CHECK-NEXT: 2 4 0.50 * st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT: 2 4 0.50 * st2d { z0.d, z1.d }, p0, [x0]
-# CHECK-NEXT: 2 4 0.50 * st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT: 3 4 0.50 * st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 4 0.50 * st2h { z0.h, z1.h }, p0, [x0]
-# CHECK-NEXT: 2 4 0.50 * st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
-# CHECK-NEXT: 3 4 0.50 * st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT: 2 4 0.50 * st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 2 4 0.50 * st2w { z0.s, z1.s }, p0, [x0]
-# CHECK-NEXT: 2 4 0.50 * st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
-# CHECK-NEXT: 2 4 0.50 * st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT: 15 7 2.50 * st3b { z0.b - z2.b }, p0, [x0, x0]
-# CHECK-NEXT: 10 7 2.50 * st3b { z0.b - z2.b }, p0, [x0]
-# CHECK-NEXT: 10 7 2.50 * st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]
-# CHECK-NEXT: 10 7 2.50 * st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT: 15 7 2.50 * st3b { z5.b - z7.b }, p3, [x17, x16]
-# CHECK-NEXT: 15 7 2.50 * st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT: 10 7 2.50 * st3d { z0.d - z2.d }, p0, [x0]
-# CHECK-NEXT: 10 7 2.50 * st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]
-# CHECK-NEXT: 10 7 2.50 * st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT: 15 7 2.50 * st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT: 15 7 2.50 * st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 10 7 2.50 * st3h { z0.h - z2.h }, p0, [x0]
-# CHECK-NEXT: 10 7 2.50 * st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]
-# CHECK-NEXT: 10 7 2.50 * st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT: 15 7 2.50 * st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT: 15 7 2.50 * st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 10 7 2.50 * st3w { z0.s - z2.s }, p0, [x0]
-# CHECK-NEXT: 10 7 2.50 * st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]
-# CHECK-NEXT: 10 7 2.50 * st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]
-# CHECK-NEXT: 15 7 2.50 * st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT: 27 11 4.50 * st4b { z0.b - z3.b }, p0, [x0, x0]
-# CHECK-NEXT: 18 19 4.50 * st4b { z0.b - z3.b }, p0, [x0]
-# CHECK-NEXT: 18 19 4.50 * st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]
-# CHECK-NEXT: 18 19 4.50 * st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT: 27 11 4.50 * st4b { z5.b - z8.b }, p3, [x17, x16]
-# CHECK-NEXT: 27 11 4.50 * st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT: 18 19 4.50 * st4d { z0.d - z3.d }, p0, [x0]
-# CHECK-NEXT: 18 19 4.50 * st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]
-# CHECK-NEXT: 18 19 4.50 * st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT: 27 11 4.50 * st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]
-# CHECK-NEXT: 27 11 4.50 * st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 18 19 4.50 * st4h { z0.h - z3.h }, p0, [x0]
-# CHECK-NEXT: 18 19 4.50 * st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]
-# CHECK-NEXT: 18 19 4.50 * st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT: 27 11 4.50 * st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]
-# CHECK-NEXT: 27 11 4.50 * st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 18 19 4.50 * st4w { z0.s - z3.s }, p0, [x0]
-# CHECK-NEXT: 18 19 4.50 * st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]
-# CHECK-NEXT: 18 19 4.50 * st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]
-# CHECK-NEXT: 27 11 4.50 * st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]
-# CHECK-NEXT: 2 2 0.50 * stnt1b { z0.b }, p0, [x0, x0]
-# CHECK-NEXT: 2 2 0.50 * stnt1b { z0.b }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * stnt1b { z21.b }, p5, [x10, #7, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1b { z23.b }, p3, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1d { z0.d }, p0, [x0, x0, lsl #3]
-# CHECK-NEXT: 2 2 0.50 * stnt1d { z0.d }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * stnt1d { z21.d }, p5, [x10, #7, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1d { z23.d }, p3, [x13, #-8, mul vl]
-# CHECK-NEXT: 3 2 0.50 * stnt1h { z0.h }, p0, [x0, x0, lsl #1]
-# CHECK-NEXT: 2 2 0.50 * stnt1h { z0.h }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * stnt1h { z21.h }, p5, [x10, #7, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1h { z23.h }, p3, [x13, #-8, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1w { z0.s }, p0, [x0, x0, lsl #2]
-# CHECK-NEXT: 2 2 0.50 * stnt1w { z0.s }, p0, [x0]
-# CHECK-NEXT: 2 2 0.50 * stnt1w { z21.s }, p5, [x10, #7, mul vl]
-# CHECK-NEXT: 2 2 0.50 * stnt1w { z23.s }, p3, [x13, #-8, mul vl]
-# CHECK-NEXT: 1 1 0.50 * str p0, [x0]
-# CHECK-NEXT: 1 1 0.50 * str p15, [sp, #-256, mul vl]
-# CHECK-NEXT: 1 1 0.50 * str p5, [x10, #255, mul vl]
-# CHECK-NEXT: 2 2 0.50 * str z0, [x0]
-# CHECK-NEXT: 2 2 0.50 * str z21, [x10, #-256, mul vl]
-# CHECK-NEXT: 2 2 0.50 * str z31, [sp, #255, mul vl]
-# CHECK-NEXT: 1 2 0.50 sub z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 sub z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 sub z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 sub z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 sub z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 sub z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sub z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 sub z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 sub z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 sub z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sub z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 sub z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 sub z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 sub z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 sub z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 sub z21.b, p5/m, z21.b, z10.b
-# CHECK-NEXT: 1 2 0.50 sub z21.b, z10.b, z21.b
-# CHECK-NEXT: 1 2 0.50 sub z21.d, p5/m, z21.d, z10.d
-# CHECK-NEXT: 1 2 0.50 sub z21.d, z10.d, z21.d
-# CHECK-NEXT: 1 2 0.50 sub z21.h, p5/m, z21.h, z10.h
-# CHECK-NEXT: 1 2 0.50 sub z21.h, z10.h, z21.h
-# CHECK-NEXT: 1 2 0.50 sub z21.s, p5/m, z21.s, z10.s
-# CHECK-NEXT: 1 2 0.50 sub z21.s, z10.s, z21.s
-# CHECK-NEXT: 1 2 0.50 sub z23.b, p3/m, z23.b, z13.b
-# CHECK-NEXT: 1 2 0.50 sub z23.b, z13.b, z8.b
-# CHECK-NEXT: 1 2 0.50 sub z23.d, p3/m, z23.d, z13.d
-# CHECK-NEXT: 1 2 0.50 sub z23.d, z13.d, z8.d
-# CHECK-NEXT: 1 2 0.50 sub z23.h, p3/m, z23.h, z13.h
-# CHECK-NEXT: 1 2 0.50 sub z23.h, z13.h, z8.h
-# CHECK-NEXT: 1 2 0.50 sub z23.s, p3/m, z23.s, z13.s
-# CHECK-NEXT: 1 2 0.50 sub z23.s, z13.s, z8.s
-# CHECK-NEXT: 1 2 0.50 sub z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 sub z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 sub z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 sub z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 sub z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 sub z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 sub z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 sub z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 sub z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 sub z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 sub z31.s, z31.s, #65280
-# CHECK-NEXT: 1 2 0.50 sub z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 subr z0.b, p0/m, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 subr z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 subr z0.d, p0/m, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 subr z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 subr z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 subr z0.h, p0/m, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 subr z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 subr z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 subr z0.s, p0/m, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 subr z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 subr z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 subr z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 subr z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 subr z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 subr z31.s, z31.s, #65280
-# CHECK-NEXT: 1 3 0.25 sudot z0.s, z1.b, z7.b[3]
-# CHECK-NEXT: 1 2 0.50 sunpkhi z31.d, z31.s
-# CHECK-NEXT: 1 2 0.50 sunpkhi z31.h, z31.b
-# CHECK-NEXT: 1 2 0.50 sunpkhi z31.s, z31.h
-# CHECK-NEXT: 1 2 0.50 sunpklo z31.d, z31.s
-# CHECK-NEXT: 1 2 0.50 sunpklo z31.h, z31.b
-# CHECK-NEXT: 1 2 0.50 sunpklo z31.s, z31.h
-# CHECK-NEXT: 1 2 1.00 sxtb z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 sxtb z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 2 1.00 sxtb z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 1.00 sxtb z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 1.00 sxtb z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 1.00 sxtb z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 sxth z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 sxth z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 1.00 sxth z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 1.00 sxth z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 sxtw z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 sxtw z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 0.50 tbl z31.b, { z31.b }, z31.b
-# CHECK-NEXT: 1 2 0.50 tbl z31.d, { z31.d }, z31.d
-# CHECK-NEXT: 1 2 0.50 tbl z31.h, { z31.h }, z31.h
-# CHECK-NEXT: 1 2 0.50 tbl z31.s, { z31.s }, z31.s
-# CHECK-NEXT: 1 2 1.00 trn1 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 trn1 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 trn1 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 trn1 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 trn1 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 trn1 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 trn1 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 trn1 z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 1.00 trn2 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 trn2 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 trn2 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 trn2 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 trn2 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 trn2 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 trn2 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 trn2 z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 uabd z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 uabd z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 uabd z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 uabd z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 5 14 2.00 uaddv d0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 uaddv d0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 uaddv d0, p7, z31.s
-# CHECK-NEXT: 2 8 0.50 uaddv d28, p6, z6.d
-# CHECK-NEXT: 1 3 1.00 ucvtf z0.d, p0/m, z0.d
-# CHECK-NEXT: 4 6 4.00 ucvtf z0.h, p0/m, z0.h
-# CHECK-NEXT: 2 4 2.00 ucvtf z0.h, p0/m, z0.s
-# CHECK-NEXT: 1 3 1.00 ucvtf z30.h, p2/m, z24.d
-# CHECK-NEXT: 1 3 1.00 ucvtf z0.s, p0/m, z0.d
-# CHECK-NEXT: 2 4 2.00 ucvtf z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 20 7.00 udiv z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 12 7.00 udiv z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 20 7.00 udivr z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 12 7.00 udivr z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 4 1.00 udot z0.d, z1.h, z15.h[1]
-# CHECK-NEXT: 1 4 1.00 udot z0.d, z1.h, z31.h
-# CHECK-NEXT: 1 3 1.00 ucvtf z24.d, p5/m, z9.s
-# CHECK-NEXT: 1 3 0.50 udot z0.s, z1.b, z31.b
-# CHECK-NEXT: 1 3 0.50 udot z0.s, z1.b, z7.b[3]
-# CHECK-NEXT: 1 2 0.50 umax z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 umax z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 umax z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 umax z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 umax z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 umax z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 5 14 2.00 umaxv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 umaxv h0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 umaxv s0, p7, z31.s
-# CHECK-NEXT: 2 8 0.50 umaxv d11, p4, z11.d
-# CHECK-NEXT: 1 2 0.50 umin z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 umin z31.b, p7/m, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 umin z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 umin z31.d, p7/m, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 umin z31.h, p7/m, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 umin z31.s, p7/m, z31.s, z31.s
-# CHECK-NEXT: 1 2 0.50 umin z21.s, z21.s, #139
-# CHECK-NEXT: 5 14 2.00 uminv b0, p7, z31.b
-# CHECK-NEXT: 4 12 2.00 uminv h0, p7, z31.h
-# CHECK-NEXT: 4 10 2.00 uminv s0, p7, z31.s
-# CHECK-NEXT: 2 8 0.50 uminv d24, p5, z29.d
-# CHECK-NEXT: 1 3 0.50 ummla z0.s, z1.b, z2.b
-# CHECK-NEXT: 1 4 1.00 umulh z0.b, p7/m, z0.b, z31.b
-# CHECK-NEXT: 2 5 2.00 umulh z0.d, p7/m, z0.d, z31.d
-# CHECK-NEXT: 1 4 1.00 umulh z0.h, p7/m, z0.h, z31.h
-# CHECK-NEXT: 1 4 1.00 umulh z0.s, p7/m, z0.s, z31.s
-# CHECK-NEXT: 1 2 0.50 uqadd z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 uqadd z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 uqadd z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 uqadd z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqadd z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 uqadd z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 uqadd z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqadd z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 uqadd z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 uqadd z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqadd z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 uqadd z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 uqadd z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 uqadd z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 uqadd z31.s, z31.s, #65280
-# CHECK-NEXT: 1 2 1.00 uqdecb w0
-# CHECK-NEXT: 1 2 1.00 uqdecb w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecb w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecb w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecb x0
-# CHECK-NEXT: 1 2 1.00 uqdecb x0, #14
-# CHECK-NEXT: 1 2 1.00 uqdecb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecb x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecb x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqdecd w0
-# CHECK-NEXT: 1 2 1.00 uqdecd w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecd w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecd w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecd x0
-# CHECK-NEXT: 1 2 1.00 uqdecd x0, #14
-# CHECK-NEXT: 1 2 1.00 uqdecd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecd x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecd x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqdecd z0.d
-# CHECK-NEXT: 1 2 1.00 uqdecd z0.d, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecd z0.d, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecd z0.d, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdech w0
-# CHECK-NEXT: 1 2 1.00 uqdech w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdech w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdech w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdech x0
-# CHECK-NEXT: 1 2 1.00 uqdech x0, #14
-# CHECK-NEXT: 1 2 1.00 uqdech x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdech x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdech x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqdech z0.h
-# CHECK-NEXT: 1 2 1.00 uqdech z0.h, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdech z0.h, pow2
-# CHECK-NEXT: 1 2 1.00 uqdech z0.h, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecp wzr, p15.b
-# CHECK-NEXT: 1 2 1.00 uqdecp wzr, p15.d
-# CHECK-NEXT: 1 2 1.00 uqdecp wzr, p15.h
-# CHECK-NEXT: 1 2 1.00 uqdecp wzr, p15.s
-# CHECK-NEXT: 1 2 1.00 uqdecp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 uqdecp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 uqdecp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 uqdecp x0, p0.s
-# CHECK-NEXT: 3 7 2.00 uqdecp z0.d, p0.d
-# CHECK-NEXT: 3 7 2.00 uqdecp z0.h, p0.h
-# CHECK-NEXT: 3 7 2.00 uqdecp z0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 uqdecw w0
-# CHECK-NEXT: 1 2 1.00 uqdecw w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecw w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecw w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecw x0
-# CHECK-NEXT: 1 2 1.00 uqdecw x0, #14
-# CHECK-NEXT: 1 2 1.00 uqdecw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecw x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecw x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqdecw z0.s
-# CHECK-NEXT: 1 2 1.00 uqdecw z0.s, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqdecw z0.s, pow2
-# CHECK-NEXT: 1 2 1.00 uqdecw z0.s, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincb w0
-# CHECK-NEXT: 1 2 1.00 uqincb w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincb w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincb w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincb x0
-# CHECK-NEXT: 1 2 1.00 uqincb x0, #14
-# CHECK-NEXT: 1 2 1.00 uqincb x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincb x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincb x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqincd w0
-# CHECK-NEXT: 1 2 1.00 uqincd w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincd w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincd w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincd x0
-# CHECK-NEXT: 1 2 1.00 uqincd x0, #14
-# CHECK-NEXT: 1 2 1.00 uqincd x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincd x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincd x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqincd z0.d
-# CHECK-NEXT: 1 2 1.00 uqincd z0.d, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincd z0.d, pow2
-# CHECK-NEXT: 1 2 1.00 uqincd z0.d, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqinch w0
-# CHECK-NEXT: 1 2 1.00 uqinch w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqinch w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqinch w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqinch x0
-# CHECK-NEXT: 1 2 1.00 uqinch x0, #14
-# CHECK-NEXT: 1 2 1.00 uqinch x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqinch x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqinch x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqinch z0.h
-# CHECK-NEXT: 1 2 1.00 uqinch z0.h, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqinch z0.h, pow2
-# CHECK-NEXT: 1 2 1.00 uqinch z0.h, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincp wzr, p15.b
-# CHECK-NEXT: 1 2 1.00 uqincp wzr, p15.d
-# CHECK-NEXT: 1 2 1.00 uqincp wzr, p15.h
-# CHECK-NEXT: 1 2 1.00 uqincp wzr, p15.s
-# CHECK-NEXT: 1 2 1.00 uqincp x0, p0.b
-# CHECK-NEXT: 1 2 1.00 uqincp x0, p0.d
-# CHECK-NEXT: 1 2 1.00 uqincp x0, p0.h
-# CHECK-NEXT: 1 2 1.00 uqincp x0, p0.s
-# CHECK-NEXT: 3 7 2.00 uqincp z0.d, p0.d
-# CHECK-NEXT: 3 7 2.00 uqincp z0.h, p0.h
-# CHECK-NEXT: 3 7 2.00 uqincp z0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 uqincw w0
-# CHECK-NEXT: 1 2 1.00 uqincw w0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincw w0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincw w0, pow2, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincw x0
-# CHECK-NEXT: 1 2 1.00 uqincw x0, #14
-# CHECK-NEXT: 1 2 1.00 uqincw x0, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincw x0, pow2
-# CHECK-NEXT: 1 2 1.00 uqincw x0, vl1
-# CHECK-NEXT: 1 2 1.00 uqincw z0.s
-# CHECK-NEXT: 1 2 1.00 uqincw z0.s, all, mul #16
-# CHECK-NEXT: 1 2 1.00 uqincw z0.s, pow2
-# CHECK-NEXT: 1 2 1.00 uqincw z0.s, pow2, mul #16
-# CHECK-NEXT: 1 2 0.50 uqsub z0.b, z0.b, #0
-# CHECK-NEXT: 1 2 0.50 uqsub z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 uqsub z0.d, z0.d, #0
-# CHECK-NEXT: 1 2 0.50 uqsub z0.d, z0.d, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqsub z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 uqsub z0.h, z0.h, #0
-# CHECK-NEXT: 1 2 0.50 uqsub z0.h, z0.h, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqsub z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 uqsub z0.s, z0.s, #0
-# CHECK-NEXT: 1 2 0.50 uqsub z0.s, z0.s, #0, lsl #8
-# CHECK-NEXT: 1 2 0.50 uqsub z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 uqsub z31.b, z31.b, #255
-# CHECK-NEXT: 1 2 0.50 uqsub z31.d, z31.d, #65280
-# CHECK-NEXT: 1 2 0.50 uqsub z31.h, z31.h, #65280
-# CHECK-NEXT: 1 2 0.50 uqsub z31.s, z31.s, #65280
-# CHECK-NEXT: 1 3 0.25 usdot z0.s, z1.b, z31.b
-# CHECK-NEXT: 1 3 0.25 usdot z0.s, z1.b, z7.b[3]
-# CHECK-NEXT: 1 3 0.50 usmmla z0.s, z1.b, z2.b
-# CHECK-NEXT: 1 2 0.50 uunpkhi z31.d, z31.s
-# CHECK-NEXT: 1 2 0.50 uunpkhi z31.h, z31.b
-# CHECK-NEXT: 1 2 0.50 uunpkhi z31.s, z31.h
-# CHECK-NEXT: 1 2 0.50 uunpklo z31.d, z31.s
-# CHECK-NEXT: 1 2 0.50 uunpklo z31.h, z31.b
-# CHECK-NEXT: 1 2 0.50 uunpklo z31.s, z31.h
-# CHECK-NEXT: 1 2 1.00 uxtb z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 uxtb z0.h, p0/m, z0.h
-# CHECK-NEXT: 1 2 1.00 uxtb z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 1.00 uxtb z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 1.00 uxtb z31.h, p7/m, z31.h
-# CHECK-NEXT: 1 2 1.00 uxtb z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 uxth z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 uxth z0.s, p0/m, z0.s
-# CHECK-NEXT: 1 2 1.00 uxth z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 1.00 uxth z31.s, p7/m, z31.s
-# CHECK-NEXT: 1 2 1.00 uxtw z0.d, p0/m, z0.d
-# CHECK-NEXT: 1 2 1.00 uxtw z31.d, p7/m, z31.d
-# CHECK-NEXT: 1 2 1.00 uzp1 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 uzp1 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 uzp1 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 uzp1 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 uzp1 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 uzp1 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 uzp1 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 uzp1 z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 1.00 uzp2 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 uzp2 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 uzp2 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 uzp2 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 uzp2 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 uzp2 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 uzp2 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 uzp2 z31.s, z31.s, z31.s
-# CHECK-NEXT: 2 3 2.00 whilele p0.b, w30, wzr
-# CHECK-NEXT: 2 3 2.00 whilele p6.h, x28, x30
-# CHECK-NEXT: 2 3 2.00 whilelo p15.d, xzr, x30
-# CHECK-NEXT: 2 3 2.00 whilelo p3.b, x9, x7
-# CHECK-NEXT: 2 3 2.00 whilels p4.b, w4, w20
-# CHECK-NEXT: 2 3 2.00 whilels p0.h, w30, wzr
-# CHECK-NEXT: 2 3 2.00 whilelt p15.s, xzr, x30
-# CHECK-NEXT: 1 2 1.00 * U wrffr p0.b
-# CHECK-NEXT: 1 2 1.00 * U wrffr p15.b
-# CHECK-NEXT: 1 2 1.00 zip1 p0.b, p0.b, p0.b
-# CHECK-NEXT: 1 2 1.00 zip1 p0.d, p0.d, p0.d
-# CHECK-NEXT: 1 2 1.00 zip1 p0.h, p0.h, p0.h
-# CHECK-NEXT: 1 2 1.00 zip1 p0.s, p0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 zip1 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 zip1 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 zip1 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 zip1 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 zip1 z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 zip1 z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 zip1 z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 zip1 z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 zip1 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 zip1 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 zip1 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 zip1 z31.s, z31.s, z31.s
-# CHECK-NEXT: 1 2 1.00 zip2 p0.b, p0.b, p0.b
-# CHECK-NEXT: 1 2 1.00 zip2 p0.d, p0.d, p0.d
-# CHECK-NEXT: 1 2 1.00 zip2 p0.h, p0.h, p0.h
-# CHECK-NEXT: 1 2 1.00 zip2 p0.s, p0.s, p0.s
-# CHECK-NEXT: 1 2 1.00 zip2 p15.b, p15.b, p15.b
-# CHECK-NEXT: 1 2 1.00 zip2 p15.d, p15.d, p15.d
-# CHECK-NEXT: 1 2 1.00 zip2 p15.h, p15.h, p15.h
-# CHECK-NEXT: 1 2 1.00 zip2 p15.s, p15.s, p15.s
-# CHECK-NEXT: 1 2 0.50 zip2 z0.b, z0.b, z0.b
-# CHECK-NEXT: 1 2 0.50 zip2 z0.d, z0.d, z0.d
-# CHECK-NEXT: 1 2 0.50 zip2 z0.h, z0.h, z0.h
-# CHECK-NEXT: 1 2 0.50 zip2 z0.s, z0.s, z0.s
-# CHECK-NEXT: 1 2 0.50 zip2 z31.b, z31.b, z31.b
-# CHECK-NEXT: 1 2 0.50 zip2 z31.d, z31.d, z31.d
-# CHECK-NEXT: 1 2 0.50 zip2 z31.h, z31.h, z31.h
-# CHECK-NEXT: 1 2 0.50 zip2 z31.s, z31.s, z31.s
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_B abs z0.b, p0/m, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_D abs z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_H abs z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_S abs z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_B abs z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_D abs z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_H abs z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ABS_ZPmZ_S abs z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_B add z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_B add z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_B add z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_D add z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_D add z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_D add z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_D add z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_H add z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_H add z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_H add z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_H add z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_S add z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_S add z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_S add z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_S add z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_S add z0.s, z1.s, z2.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_B add z21.b, p5/m, z21.b, z10.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_B add z21.b, z10.b, z21.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_D add z21.d, p5/m, z21.d, z10.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_D add z21.d, z10.d, z21.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_H add z21.h, p5/m, z21.h, z10.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_H add z21.h, z10.h, z21.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_S add z21.s, p5/m, z21.s, z10.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_S add z21.s, z10.s, z21.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_B add z23.b, p3/m, z23.b, z13.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_B add z23.b, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_D add z23.d, p3/m, z23.d, z13.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_D add z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_H add z23.h, p3/m, z23.h, z13.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_H add z23.h, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_S add z23.s, p3/m, z23.s, z13.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_S add z23.s, z13.s, z8.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_B add z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_B add z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_B add z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_D add z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_D add z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_D add z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_H add z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_H add z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_H add z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZPmZ_S add z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZI_S add z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADD_ZZZ_S add z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDPL_XXI addpl sp, sp, #31
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDPL_XXI addpl x0, x0, #-32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDPL_XXI addpl x21, x21, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDPL_XXI addpl x23, x8, #-1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDVL_XXI addvl sp, sp, #31
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDVL_XXI addvl x0, x0, #-32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDVL_XXI addvl x21, x21, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ADDVL_XXI addvl x23, x8, #-1
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_D_1 adr z0.d, [z0.d, z0.d, lsl #1]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_D_2 adr z0.d, [z0.d, z0.d, lsl #2]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_D_3 adr z0.d, [z0.d, z0.d, lsl #3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_SXTW_ZZZ_D_1 adr z0.d, [z0.d, z0.d, sxtw #1]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_SXTW_ZZZ_D_2 adr z0.d, [z0.d, z0.d, sxtw #2]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_SXTW_ZZZ_D_3 adr z0.d, [z0.d, z0.d, sxtw #3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_SXTW_ZZZ_D_0 adr z0.d, [z0.d, z0.d, sxtw]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_UXTW_ZZZ_D_1 adr z0.d, [z0.d, z0.d, uxtw #1]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_UXTW_ZZZ_D_2 adr z0.d, [z0.d, z0.d, uxtw #2]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_UXTW_ZZZ_D_3 adr z0.d, [z0.d, z0.d, uxtw #3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_UXTW_ZZZ_D_0 adr z0.d, [z0.d, z0.d, uxtw]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_D_0 adr z0.d, [z0.d, z0.d]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_S_1 adr z0.s, [z0.s, z0.s, lsl #1]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_S_2 adr z0.s, [z0.s, z0.s, lsl #2]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_S_3 adr z0.s, [z0.s, z0.s, lsl #3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ADR_LSL_ZZZ_S_0 adr z0.s, [z0.s, z0.s]
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 AND_PPzPP and p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZZZ and z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZZZ and z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZPmZ_B and z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZPmZ_D and z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZPmZ_H and z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZPmZ_S and z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 AND_ZI and z5.b, z5.b, #0xf9
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ANDS_PPzPP ands p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ANDV_VPZ_B andv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ANDV_VPZ_D andv d0, p7, z31.d
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ANDV_VPZ_H andv h0, p7, z31.h
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ANDV_VPZ_S andv s0, p7, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_B asr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmZ_B asr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZPmZ_B asr z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_B asr z0.b, z0.b, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZZZ_B asr z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_D asr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmZ_D asr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_D asr z0.d, z0.d, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_H asr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmZ_H asr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZPmZ_H asr z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_H asr z0.h, z0.h, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZZZ_H asr z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_S asr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmZ_S asr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZPmZ_S asr z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_S asr z0.s, z0.s, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_WIDE_ZZZ_S asr z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_B asr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_B asr z31.b, z31.b, #8
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_D asr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_D asr z31.d, z31.d, #64
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_H asr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_H asr z31.h, z31.h, #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZPmI_S asr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASR_ZZI_S asr z31.s, z31.s, #32
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_B asrd z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_D asrd z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_H asrd z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_S asrd z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_B asrd z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_D asrd z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_H asrd z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRD_ZPmI_S asrd z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRR_ZPmZ_B asrr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRR_ZPmZ_D asrr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRR_ZPmZ_H asrr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 ASRR_ZPmZ_S asrr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 BFCVT_ZPmZ bfcvt z0.h, p0/m, z1.s
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 BFCVTNT_ZPmZ bfcvtnt z0.h, p0/m, z1.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 BFDOT_ZZZ bfdot z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 BFDOT_ZZI bfdot z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 BFDOT_ZZI bfdot z0.s, z1.h, z2.h[3]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALB_ZZZ bfmlalb z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALB_ZZZI bfmlalb z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALB_ZZZI bfmlalb z0.s, z1.h, z2.h[7]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALB_ZZZ bfmlalb z10.s, z21.h, z14.h
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALB_ZZZI bfmlalb z21.s, z14.h, z3.h[2]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALT_ZZZ bfmlalt z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALT_ZZZI bfmlalt z0.s, z1.h, z2.h[0]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALT_ZZZI bfmlalt z0.s, z1.h, z2.h[7]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALT_ZZZI bfmlalt z0.s, z1.h, z7.h[7]
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 BFMLALT_ZZZ bfmlalt z14.s, z10.h, z21.h
+# CHECK-NEXT: 1 5 0.50 3 V1UnitV,V1UnitV01 BFMMLA_ZZZ bfmmla z0.s, z1.h, z2.h
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 BIC_PPzPP bic p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 BIC_PPzPP bic p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZZZ bic z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZZZ bic z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZPmZ_B bic z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZPmZ_D bic z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZPmZ_H bic z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 BIC_ZPmZ_S bic z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BICS_PPzPP bics p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BICS_PPzPP bics p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKA_PPmP brka p0.b, p15/m, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKA_PPzP brka p0.b, p15/z, p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKAS_PPzP brkas p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKB_PPmP brkb p0.b, p15/m, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKB_PPzP brkb p0.b, p15/z, p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKBS_PPzP brkbs p0.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKN_PPzP brkn p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKN_PPzP brkn p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKNS_PPzP brkns p0.b, p15/z, p1.b, p0.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKNS_PPzP brkns p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKPA_PPzPP brkpa p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKPA_PPzPP brkpa p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKPAS_PPzPP brkpas p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKPAS_PPzPP brkpas p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKPB_PPzPP brkpb p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 BRKPB_PPzPP brkpb p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKPBS_PPzPP brkpbs p0.b, p15/z, p1.b, p2.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] BRKPBS_PPzPP brkpbs p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_VPZ_B clasta b0, p7, b0, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_VPZ_D clasta d0, p7, d0, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_VPZ_H clasta h0, p7, h0, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_VPZ_S clasta s0, p7, s0, z31.s
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_RPZ_B clasta w0, p7, w0, z31.b
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_RPZ_H clasta w0, p7, w0, z31.h
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_RPZ_S clasta w0, p7, w0, z31.s
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_RPZ_D clasta x0, p7, x0, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_ZPZ_B clasta z0.b, p7, z0.b, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_ZPZ_D clasta z0.d, p7, z0.d, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_ZPZ_H clasta z0.h, p7, z0.h, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTA_ZPZ_S clasta z0.s, p7, z0.s, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_VPZ_B clastb b0, p7, b0, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_VPZ_D clastb d0, p7, d0, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_VPZ_H clastb h0, p7, h0, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_VPZ_S clastb s0, p7, s0, z31.s
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_RPZ_B clastb w0, p7, w0, z31.b
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_RPZ_H clastb w0, p7, w0, z31.h
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_RPZ_S clastb w0, p7, w0, z31.s
+# CHECK-NEXT: 2 9 1.00 9 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_RPZ_D clastb x0, p7, x0, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_ZPZ_B clastb z0.b, p7, z0.b, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_ZPZ_D clastb z0.d, p7, z0.d, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_ZPZ_H clastb z0.h, p7, z0.h, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 CLASTB_ZPZ_S clastb z0.s, p7, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLS_ZPmZ_B cls z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLS_ZPmZ_D cls z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLS_ZPmZ_H cls z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLS_ZPmZ_S cls z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLZ_ZPmZ_B clz z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLZ_ZPmZ_D clz z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLZ_ZPmZ_H clz z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CLZ_ZPmZ_S clz z31.s, p7/m, z31.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_B cmpeq p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_B cmpeq p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZZ_B cmpeq p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_WIDE_PPzZZ_B cmpeq p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_D cmpeq p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_D cmpeq p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZZ_D cmpeq p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_H cmpeq p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_H cmpeq p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_WIDE_PPzZZ_H cmpeq p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZZ_H cmpeq p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_S cmpeq p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZI_S cmpeq p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_WIDE_PPzZZ_S cmpeq p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPEQ_PPzZZ_S cmpeq p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_B cmpge p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_B cmpge p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_B cmpge p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_WIDE_PPzZZ_B cmpge p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_B cmpge p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_D cmpge p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_D cmpge p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_D cmpge p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_D cmpge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_H cmpge p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_H cmpge p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_WIDE_PPzZZ_H cmpge p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_H cmpge p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_H cmpge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_S cmpge p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZI_S cmpge p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_WIDE_PPzZZ_S cmpge p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_S cmpge p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGE_PPzZZ_S cmpge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_B cmpgt p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_B cmpgt p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_B cmpgt p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_WIDE_PPzZZ_B cmpgt p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_B cmpgt p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_D cmpgt p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_D cmpgt p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_D cmpgt p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_D cmpgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_H cmpgt p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_H cmpgt p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_WIDE_PPzZZ_H cmpgt p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_H cmpgt p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_H cmpgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_S cmpgt p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZI_S cmpgt p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_WIDE_PPzZZ_S cmpgt p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_S cmpgt p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPGT_PPzZZ_S cmpgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_B cmphi p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_B cmphi p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_B cmphi p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_WIDE_PPzZZ_B cmphi p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_B cmphi p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_D cmphi p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_D cmphi p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_D cmphi p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_D cmphi p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_H cmphi p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_H cmphi p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_WIDE_PPzZZ_H cmphi p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_H cmphi p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_H cmphi p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_S cmphi p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZI_S cmphi p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_WIDE_PPzZZ_S cmphi p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_S cmphi p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHI_PPzZZ_S cmphi p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_B cmphs p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_B cmphs p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_B cmphs p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_WIDE_PPzZZ_B cmphs p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_B cmphs p0.b, p0/z, z1.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_D cmphs p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_D cmphs p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_D cmphs p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_D cmphs p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_H cmphs p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_H cmphs p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_WIDE_PPzZZ_H cmphs p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_H cmphs p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_H cmphs p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_S cmphs p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZI_S cmphs p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_WIDE_PPzZZ_S cmphs p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_S cmphs p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPHS_PPzZZ_S cmphs p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_B cmple p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_B cmple p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_WIDE_PPzZZ_B cmple p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_D cmple p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_D cmple p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_H cmple p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_H cmple p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_WIDE_PPzZZ_H cmple p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_S cmple p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_PPzZI_S cmple p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLE_WIDE_PPzZZ_S cmple p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_B cmplo p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_B cmplo p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_WIDE_PPzZZ_B cmplo p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_D cmplo p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_D cmplo p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_H cmplo p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_H cmplo p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_WIDE_PPzZZ_H cmplo p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_S cmplo p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_PPzZI_S cmplo p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLO_WIDE_PPzZZ_S cmplo p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_B cmpls p0.b, p0/z, z0.b, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_B cmpls p0.b, p0/z, z0.b, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_WIDE_PPzZZ_B cmpls p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_D cmpls p0.d, p0/z, z0.d, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_D cmpls p0.d, p0/z, z0.d, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_H cmpls p0.h, p0/z, z0.h, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_H cmpls p0.h, p0/z, z0.h, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_WIDE_PPzZZ_H cmpls p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_S cmpls p0.s, p0/z, z0.s, #0
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_PPzZI_S cmpls p0.s, p0/z, z0.s, #127
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLS_WIDE_PPzZZ_S cmpls p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_B cmplt p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_B cmplt p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_WIDE_PPzZZ_B cmplt p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_D cmplt p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_D cmplt p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_H cmplt p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_H cmplt p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_WIDE_PPzZZ_H cmplt p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_S cmplt p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_PPzZI_S cmplt p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPLT_WIDE_PPzZZ_S cmplt p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_B cmpne p0.b, p0/z, z0.b, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_B cmpne p0.b, p0/z, z0.b, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZZ_B cmpne p0.b, p0/z, z0.b, z0.b
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_WIDE_PPzZZ_B cmpne p0.b, p0/z, z0.b, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_D cmpne p0.d, p0/z, z0.d, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_D cmpne p0.d, p0/z, z0.d, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZZ_D cmpne p0.d, p0/z, z0.d, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_H cmpne p0.h, p0/z, z0.h, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_H cmpne p0.h, p0/z, z0.h, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_WIDE_PPzZZ_H cmpne p0.h, p0/z, z0.h, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZZ_H cmpne p0.h, p0/z, z0.h, z0.h
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_S cmpne p0.s, p0/z, z0.s, #-16
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZI_S cmpne p0.s, p0/z, z0.s, #15
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_WIDE_PPzZZ_S cmpne p0.s, p0/z, z0.s, z0.d
+# CHECK-NEXT: 2 4 1.00 4 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 CMPNE_PPzZZ_S cmpne p0.s, p0/z, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNOT_ZPmZ_B cnot z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNOT_ZPmZ_D cnot z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNOT_ZPmZ_H cnot z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNOT_ZPmZ_S cnot z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNT_ZPmZ_B cnt z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNT_ZPmZ_D cnt z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNT_ZPmZ_H cnt z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CNT_ZPmZ_S cnt z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTB_XPiI cntb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTB_XPiI cntb x0, #28
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTB_XPiI cntb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTB_XPiI cntb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTD_XPiI cntd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTD_XPiI cntd x0, #28
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTD_XPiI cntd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTD_XPiI cntd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTH_XPiI cnth x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTH_XPiI cnth x0, #28
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTH_XPiI cnth x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTH_XPiI cnth x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTP_XPP_B cntp x0, p15, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTP_XPP_D cntp x0, p15, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTP_XPP_H cntp x0, p15, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTP_XPP_S cntp x0, p15, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTW_XPiI cntw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTW_XPiI cntw x0, #28
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTW_XPiI cntw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 CNTW_XPiI cntw x0, pow2
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 COMPACT_ZPZ_D compact z31.d, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 COMPACT_ZPZ_S compact z31.s, p7, z31.s
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_B mov z31.b, p7/m, w0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_D mov z31.d, p7/m, sp
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_H mov z31.h, p7/m, w0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_S mov z31.s, p7/m, wsp
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMEQ_WW ctermeq w30, wzr
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMEQ_WW ctermeq wzr, w30
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMEQ_XX ctermeq x30, xzr
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMEQ_XX ctermeq xzr, x30
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMNE_WW ctermne w30, wzr
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMNE_WW ctermne wzr, w30
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMNE_XX ctermne x30, xzr
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 CTERMNE_XX ctermne xzr, x30
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECB_XPiI decb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECB_XPiI decb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECB_XPiI decb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECB_XPiI decb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECB_XPiI decb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECD_XPiI decd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECD_XPiI decd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECD_XPiI decd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECD_XPiI decd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECD_XPiI decd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECH_XPiI dech x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECH_XPiI dech x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECH_XPiI dech x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECH_XPiI dech x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECH_XPiI dech x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_B decp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_D decp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_H decp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_S decp x0, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_B decp xzr, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_D decp xzr, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_H decp xzr, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECP_XP_S decp xzr, p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 DECD_ZPiI decd z19.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 DECP_ZP_D decp z31.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 DECH_ZPiI dech z23.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 DECP_ZP_H decp z31.h, p15.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 DECP_ZP_S decp z31.s, p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 DECW_ZPiI decw z8.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECW_XPiI decw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECW_XPiI decw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECW_XPiI decw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECW_XPiI decw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 DECW_XPiI decw x0, vl1
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_B mov z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z0.d, #256
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z31.h, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z31.s, #512
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_B mov z0.b, w0
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_D mov z0.d, x0
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_H mov z31.h, wsp
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_S mov z31.s, wsp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI dupm z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI dupm z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI dupm z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI dupm z5.b, #0xf9
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 EOR_PPzPP eor p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZZZ eor z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZZZ eor z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZPmZ_B eor z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZPmZ_D eor z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZPmZ_H eor z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZPmZ_S eor z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EOR_ZI eor z5.b, z5.b, #0xf9
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] EORS_PPzPP eors p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] EORV_VPZ_B eorv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] EORV_VPZ_D eorv d0, p7, z31.d
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] EORV_VPZ_H eorv h0, p7, z31.h
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] EORV_VPZ_S eorv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EXT_ZZI ext z31.b, z31.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 EXT_ZZI ext z31.b, z31.b, z0.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABD_ZPmZ_D fabd z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABD_ZPmZ_H fabd z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABD_ZPmZ_S fabd z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABS_ZPmZ_D fabs z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABS_ZPmZ_H fabs z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FABS_ZPmZ_S fabs z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_D facge p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_D facge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_H facge p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_H facge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_S facge p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGE_PPzZZ_S facge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_D facgt p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_D facgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_H facgt p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_H facgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_S facgt p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FACGT_PPzZZ_S facgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_D fadd z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmZ_D fadd z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZZZ_D fadd z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_H fadd z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmZ_H fadd z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZZZ_H fadd z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_S fadd z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmZ_S fadd z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZZZ_S fadd z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_D fadd z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_H fadd z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FADD_ZPmI_S fadd z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 3 8 1.50 8 V1UnitV[3],V1UnitV01[3] FADDA_VPZ_D fadda d0, p7, d0, z31.d
+# CHECK-NEXT: 18 19 18.00 19 V1UnitV[18],V1UnitV0[18],V1UnitV01[18],V1UnitV02[18] FADDA_VPZ_H fadda h0, p7, h0, z31.h
+# CHECK-NEXT: 10 11 10.00 11 V1UnitV[10],V1UnitV0[10],V1UnitV01[10],V1UnitV02[10] FADDA_VPZ_S fadda s0, p7, s0, z31.s
+# CHECK-NEXT: 5 9 2.00 9 V1UnitV[5],V1UnitV01[4] FADDV_VPZ_D faddv d0, p7, z31.d
+# CHECK-NEXT: 6 13 3.00 13 V1UnitV[6],V1UnitV01[6] FADDV_VPZ_H faddv h0, p7, z31.h
+# CHECK-NEXT: 6 11 2.50 11 V1UnitV[6],V1UnitV01[5] FADDV_VPZ_S faddv s0, p7, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_D fcadd z0.d, p0/m, z0.d, z0.d, #90
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_H fcadd z0.h, p0/m, z0.h, z0.h, #90
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_S fcadd z0.s, p0/m, z0.s, z0.s, #90
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_D fcadd z31.d, p7/m, z31.d, z31.d, #270
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_H fcadd z31.h, p7/m, z31.h, z31.h, #270
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FCADD_ZPmZ_S fcadd z31.s, p7/m, z31.s, z31.s, #270
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZ0_D fcmeq p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZZ_D fcmeq p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZ0_H fcmeq p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZZ_H fcmeq p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZ0_S fcmeq p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMEQ_PPzZZ_S fcmeq p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZ0_D fcmge p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_D fcmge p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_D fcmge p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZ0_H fcmge p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_H fcmge p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_H fcmge p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZ0_S fcmge p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_S fcmge p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGE_PPzZZ_S fcmge p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZ0_D fcmgt p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_D fcmgt p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_D fcmgt p0.d, p0/z, z1.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZ0_H fcmgt p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_H fcmgt p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_H fcmgt p0.h, p0/z, z1.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZ0_S fcmgt p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_S fcmgt p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMGT_PPzZZ_S fcmgt p0.s, p0/z, z1.s, z0.s
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_D fcmla z0.d, p0/m, z0.d, z0.d, #0
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_D fcmla z0.d, p0/m, z1.d, z2.d, #90
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_H fcmla z0.h, p0/m, z0.h, z0.h, #0
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_H fcmla z0.h, p0/m, z1.h, z2.h, #90
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZZZI_H fcmla z0.h, z0.h, z0.h[0], #0
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_S fcmla z0.s, p0/m, z0.s, z0.s, #0
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_S fcmla z0.s, p0/m, z1.s, z2.s, #90
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZZZI_S fcmla z21.s, z10.s, z5.s[1], #90
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZZZI_S fcmla z23.s, z13.s, z8.s[0], #270
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_D fcmla z29.d, p7/m, z30.d, z31.d, #180
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_H fcmla z29.h, p7/m, z30.h, z31.h, #180
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_S fcmla z29.s, p7/m, z30.s, z31.s, #180
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_D fcmla z31.d, p7/m, z31.d, z31.d, #270
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_H fcmla z31.h, p7/m, z31.h, z31.h, #270
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZZZI_H fcmla z31.h, z31.h, z7.h[3], #270
+# CHECK-NEXT: 1 5 0.50 2 V1UnitV,V1UnitV01 FCMLA_ZPmZZ_S fcmla z31.s, p7/m, z31.s, z31.s, #270
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLE_PPzZ0_D fcmle p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLE_PPzZ0_H fcmle p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLE_PPzZ0_S fcmle p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLT_PPzZ0_D fcmlt p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLT_PPzZ0_H fcmlt p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMLT_PPzZ0_S fcmlt p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZ0_D fcmne p0.d, p0/z, z0.d, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZZ_D fcmne p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZ0_H fcmne p0.h, p0/z, z0.h, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZZ_H fcmne p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZ0_S fcmne p0.s, p0/z, z0.s, #0.0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMNE_PPzZZ_S fcmne p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMUO_PPzZZ_D fcmuo p0.d, p0/z, z0.d, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMUO_PPzZZ_H fcmuo p0.h, p0/z, z0.h, z1.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCMUO_PPzZZ_S fcmuo p0.s, p0/z, z0.s, z1.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVT_ZPmZ_HtoD fcvt z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVT_ZPmZ_StoD fcvt z0.d, p0/m, z0.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVT_ZPmZ_DtoH fcvt z0.h, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVT_ZPmZ_StoH fcvt z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVT_ZPmZ_DtoS fcvt z0.s, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVT_ZPmZ_HtoS fcvt z0.s, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZS_ZPmZ_DtoD fcvtzs z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZS_ZPmZ_HtoD fcvtzs z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZS_ZPmZ_StoD fcvtzs z0.d, p0/m, z0.s
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] FCVTZS_ZPmZ_HtoH fcvtzs z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZS_ZPmZ_DtoS fcvtzs z0.s, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVTZS_ZPmZ_HtoS fcvtzs z0.s, p0/m, z0.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVTZS_ZPmZ_StoS fcvtzs z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZU_ZPmZ_DtoD fcvtzu z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZU_ZPmZ_HtoD fcvtzu z0.d, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZU_ZPmZ_StoD fcvtzu z0.d, p0/m, z0.s
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] FCVTZU_ZPmZ_HtoH fcvtzu z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FCVTZU_ZPmZ_DtoS fcvtzu z0.s, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVTZU_ZPmZ_HtoS fcvtzu z0.s, p0/m, z0.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FCVTZU_ZPmZ_StoS fcvtzu z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 15 7.00 15 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FDIV_ZPmZ_D fdiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 13 10.00 13 V1UnitV[10],V1UnitV0[10],V1UnitV01[10],V1UnitV02[10] FDIV_ZPmZ_H fdiv z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 10 7.00 10 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FDIV_ZPmZ_S fdiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 15 7.00 15 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FDIVR_ZPmZ_D fdivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 13 10.00 13 V1UnitV[10],V1UnitV0[10],V1UnitV01[10],V1UnitV02[10] FDIVR_ZPmZ_H fdivr z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 10 7.00 10 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FDIVR_ZPmZ_S fdivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FEXPA_ZZ_D fexpa z0.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FEXPA_ZZ_H fexpa z0.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FEXPA_ZZ_S fexpa z0.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMAD_ZPmZZ_D fmad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMAD_ZPmZZ_H fmad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMAD_ZPmZZ_S fmad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_D fmax z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmZ_D fmax z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_H fmax z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmZ_H fmax z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_S fmax z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmZ_S fmax z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_D fmax z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_H fmax z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAX_ZPmI_S fmax z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_D fmaxnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmZ_D fmaxnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_H fmaxnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmZ_H fmaxnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_S fmaxnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmZ_S fmaxnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_D fmaxnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_H fmaxnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMAXNM_ZPmI_S fmaxnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 5 9 2.00 9 V1UnitV[5],V1UnitV01[4] FMAXNMV_VPZ_D fmaxnmv d0, p7, z31.d
+# CHECK-NEXT: 6 13 3.00 13 V1UnitV[6],V1UnitV01[6] FMAXNMV_VPZ_H fmaxnmv h0, p7, z31.h
+# CHECK-NEXT: 6 11 2.50 11 V1UnitV[6],V1UnitV01[5] FMAXNMV_VPZ_S fmaxnmv s0, p7, z31.s
+# CHECK-NEXT: 5 9 2.00 9 V1UnitV[5],V1UnitV01[4] FMAXV_VPZ_D fmaxv d0, p7, z31.d
+# CHECK-NEXT: 6 13 3.00 13 V1UnitV[6],V1UnitV01[6] FMAXV_VPZ_H fmaxv h0, p7, z31.h
+# CHECK-NEXT: 6 11 2.50 11 V1UnitV[6],V1UnitV01[5] FMAXV_VPZ_S fmaxv s0, p7, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_D fmin z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmZ_D fmin z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_H fmin z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmZ_H fmin z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_S fmin z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmZ_S fmin z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_D fmin z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_H fmin z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMIN_ZPmI_S fmin z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_D fminnm z0.d, p0/m, z0.d, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmZ_D fminnm z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_H fminnm z0.h, p0/m, z0.h, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmZ_H fminnm z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_S fminnm z0.s, p0/m, z0.s, #0.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmZ_S fminnm z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_D fminnm z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_H fminnm z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FMINNM_ZPmI_S fminnm z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 5 9 2.00 9 V1UnitV[5],V1UnitV01[4] FMINNMV_VPZ_D fminnmv d0, p7, z31.d
+# CHECK-NEXT: 6 13 3.00 13 V1UnitV[6],V1UnitV01[6] FMINNMV_VPZ_H fminnmv h0, p7, z31.h
+# CHECK-NEXT: 6 11 2.50 11 V1UnitV[6],V1UnitV01[5] FMINNMV_VPZ_S fminnmv s0, p7, z31.s
+# CHECK-NEXT: 5 9 2.00 9 V1UnitV[5],V1UnitV01[4] FMINV_VPZ_D fminv d0, p7, z31.d
+# CHECK-NEXT: 6 13 3.00 13 V1UnitV[6],V1UnitV01[6] FMINV_VPZ_H fminv h0, p7, z31.h
+# CHECK-NEXT: 6 11 2.50 11 V1UnitV[6],V1UnitV01[5] FMINV_VPZ_S fminv s0, p7, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZPmZZ_D fmla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZZZI_D fmla z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZPmZZ_H fmla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZZZI_H fmla z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZPmZZ_S fmla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLA_ZZZI_S fmla z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZPmZZ_D fmls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZZZI_D fmls z0.d, z1.d, z7.d[1]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZPmZZ_H fmls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZZZI_H fmls z0.h, z1.h, z7.h[7]
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZPmZZ_S fmls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMLS_ZZZI_S fmls z0.s, z1.s, z7.s[3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FDUP_ZI_D fmov z0.d, #-10.00000000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FDUP_ZI_D fmov z0.d, #0.12500000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FCPY_ZPmI_D fmov z0.d, p0/m, #-10.00000000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FCPY_ZPmI_D fmov z0.d, p0/m, #0.12500000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FDUP_ZI_H fmov z0.h, #-0.12500000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FCPY_ZPmI_H fmov z0.h, p0/m, #-0.12500000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FDUP_ZI_S fmov z0.s, #-0.12500000
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FCPY_ZPmI_S fmov z0.s, p0/m, #-0.12500000
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMSB_ZPmZZ_D fmsb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMSB_ZPmZZ_H fmsb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FMSB_ZPmZZ_S fmsb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_D fmul z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmZ_D fmul z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_D fmul z0.d, z0.d, z0.d[0]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZ_D fmul z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_H fmul z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmZ_H fmul z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_H fmul z0.h, z0.h, z0.h[0]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZ_H fmul z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_S fmul z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmZ_S fmul z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_S fmul z0.s, z0.s, z0.s[0]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZ_S fmul z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_D fmul z31.d, p7/m, z31.d, #2.0
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_D fmul z31.d, z31.d, z15.d[1]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_H fmul z31.h, p7/m, z31.h, #2.0
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_H fmul z31.h, z31.h, z7.h[7]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZPmI_S fmul z31.s, p7/m, z31.s, #2.0
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMUL_ZZZI_S fmul z31.s, z31.s, z7.s[3]
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMULX_ZPmZ_D fmulx z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMULX_ZPmZ_H fmulx z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FMULX_ZPmZ_S fmulx z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FNEG_ZPmZ_D fneg z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FNEG_ZPmZ_H fneg z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FNEG_ZPmZ_S fneg z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMAD_ZPmZZ_D fnmad z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMAD_ZPmZZ_H fnmad z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMAD_ZPmZZ_S fnmad z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLA_ZPmZZ_D fnmla z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLA_ZPmZZ_H fnmla z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLA_ZPmZZ_S fnmla z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLS_ZPmZZ_D fnmls z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLS_ZPmZZ_H fnmls z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMLS_ZPmZZ_S fnmls z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMSB_ZPmZZ_D fnmsb z0.d, p7/m, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMSB_ZPmZZ_H fnmsb z0.h, p7/m, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 2 V1UnitV,V1UnitV01 FNMSB_ZPmZZ_S fnmsb z0.s, p7/m, z1.s, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRECPE_ZZ_D frecpe z0.d, z31.d
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] FRECPE_ZZ_H frecpe z0.h, z31.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FRECPE_ZZ_S frecpe z0.s, z31.s
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRECPS_ZZZ_D frecps z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRECPS_ZZZ_H frecps z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRECPS_ZZZ_S frecps z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRECPX_ZPmZ_D frecpx z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRECPX_ZPmZ_H frecpx z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRECPX_ZPmZ_S frecpx z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTA_ZPmZ_D frinta z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTA_ZPmZ_H frinta z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTA_ZPmZ_S frinta z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTI_ZPmZ_D frinti z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTI_ZPmZ_H frinti z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTI_ZPmZ_S frinti z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTM_ZPmZ_D frintm z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTM_ZPmZ_H frintm z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTM_ZPmZ_S frintm z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTN_ZPmZ_D frintn z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTN_ZPmZ_H frintn z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTN_ZPmZ_S frintn z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTP_ZPmZ_D frintp z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTP_ZPmZ_H frintp z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTP_ZPmZ_S frintp z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTX_ZPmZ_D frintx z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTX_ZPmZ_H frintx z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTX_ZPmZ_S frintx z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTZ_ZPmZ_D frintz z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 6 1.00 6 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTZ_ZPmZ_H frintz z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRINTZ_ZPmZ_S frintz z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 FRSQRTE_ZZ_D frsqrte z0.d, z31.d
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] FRSQRTE_ZZ_H frsqrte z0.h, z31.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] FRSQRTE_ZZ_S frsqrte z0.s, z31.s
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRSQRTS_ZZZ_D frsqrts z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRSQRTS_ZZZ_H frsqrts z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 4 0.50 4 V1UnitV,V1UnitV01 FRSQRTS_ZZZ_S frsqrts z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FSCALE_ZPmZ_D fscale z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FSCALE_ZPmZ_H fscale z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FSCALE_ZPmZ_S fscale z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 16 7.00 16 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FSQRT_ZPmZ_D fsqrt z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 13 10.00 13 V1UnitV[10],V1UnitV0[10],V1UnitV01[10],V1UnitV02[10] FSQRT_ZPmZ_H fsqrt z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 10 7.00 10 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] FSQRT_ZPmZ_S fsqrt z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_D fsub z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmZ_D fsub z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZZZ_D fsub z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_H fsub z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmZ_H fsub z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZZZ_H fsub z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_S fsub z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmZ_S fsub z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZZZ_S fsub z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_D fsub z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_H fsub z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUB_ZPmI_S fsub z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_D fsubr z0.d, p0/m, z0.d, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmZ_D fsubr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_H fsubr z0.h, p0/m, z0.h, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmZ_H fsubr z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_S fsubr z0.s, p0/m, z0.s, #0.5
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmZ_S fsubr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_D fsubr z31.d, p7/m, z31.d, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_H fsubr z31.h, p7/m, z31.h, #1.0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 FSUBR_ZPmI_S fsubr z31.s, p7/m, z31.s, #1.0
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTMAD_ZZI_D ftmad z0.d, z0.d, z31.d, #7
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTMAD_ZZI_H ftmad z0.h, z0.h, z31.h, #7
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTMAD_ZZI_S ftmad z0.s, z0.s, z31.s, #7
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSMUL_ZZZ_D ftsmul z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSMUL_ZZZ_H ftsmul z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSMUL_ZZZ_S ftsmul z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSSEL_ZZZ_D ftssel z0.d, z1.d, z31.d
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSSEL_ZZZ_H ftssel z0.h, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.50 3 V1UnitV,V1UnitV01 FTSSEL_ZZZ_S ftssel z0.s, z1.s, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCB_XPiI incb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCB_XPiI incb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCB_XPiI incb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCB_XPiI incb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCB_XPiI incb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCD_XPiI incd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCD_XPiI incd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCD_XPiI incd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCD_XPiI incd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCD_XPiI incd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCD_ZPiI incd z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCD_ZPiI incd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCH_XPiI inch x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCH_XPiI inch x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCH_XPiI inch x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCH_XPiI inch x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCH_XPiI inch x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCH_ZPiI inch z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCH_ZPiI inch z0.h, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_B incp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_D incp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_H incp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_S incp x0, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_B incp xzr, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_D incp xzr, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_H incp xzr, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCP_XP_S incp xzr, p15.s
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 INCP_ZP_D incp z31.d, p15.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 INCP_ZP_H incp z31.h, p15.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 INCP_ZP_S incp z31.s, p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCW_XPiI incw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCW_XPiI incw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCW_XPiI incw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCW_XPiI incw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 INCW_XPiI incw x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCW_ZPiI incw z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INCW_ZPiI incw z0.s, all, mul #16
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_B index z0.b, #0, #0
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_II_D index z0.d, #0, #0
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_H index z0.h, #0, #0
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_H index z0.h, w0, w0
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_S index z0.s, #0, #0
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_B index z21.b, w10, w21
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_RR_D index z21.d, x10, x21
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_S index z21.s, w10, w21
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_B index z23.b, #13, w8
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_B index z23.b, w13, #8
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_IR_D index z23.d, #13, x8
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_RI_D index z23.d, x13, #8
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_H index z23.h, #13, w8
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_H index z23.h, w13, #8
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_S index z23.s, #13, w8
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_S index z23.s, w13, #8
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_B index z31.b, #-1, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_B index z31.b, #-1, wzr
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_B index z31.b, wzr, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_B index z31.b, wzr, wzr
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_II_D index z31.d, #-1, #-1
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_IR_D index z31.d, #-1, xzr
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_RI_D index z31.d, xzr, #-1
+# CHECK-NEXT: 4 8 2.00 8 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] INDEX_RR_D index z31.d, xzr, xzr
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_H index z31.h, #-1, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_H index z31.h, #-1, wzr
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_H index z31.h, wzr, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_H index z31.h, wzr, wzr
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 INDEX_II_S index z31.s, #-1, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_IR_S index z31.s, #-1, wzr
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RI_S index z31.s, wzr, #-1
+# CHECK-NEXT: 2 7 1.00 7 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INDEX_RR_S index z31.s, wzr, wzr
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_B insr z0.b, w0
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_D insr z0.d, x0
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_H insr z0.h, w0
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_S insr z0.s, w0
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZV_B insr z31.b, b31
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_B insr z31.b, wzr
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZV_D insr z31.d, d31
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_D insr z31.d, xzr
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZV_H insr z31.h, h31
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_H insr z31.h, wzr
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZV_S insr z31.s, s31
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 INSR_ZR_S insr z31.s, wzr
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_VPZ_B lasta b0, p7, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_VPZ_D lasta d0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_VPZ_H lasta h0, p7, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_VPZ_S lasta s0, p7, z31.s
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_RPZ_B lasta w0, p7, z31.b
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_RPZ_H lasta w0, p7, z31.h
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_RPZ_S lasta w0, p7, z31.s
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTA_RPZ_D lasta x0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_VPZ_B lastb b0, p7, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_VPZ_D lastb d0, p7, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_VPZ_H lastb h0, p7, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_VPZ_S lastb s0, p7, z31.s
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_RPZ_B lastb w0, p7, z31.b
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_RPZ_H lastb w0, p7, z31.h
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_RPZ_S lastb w0, p7, z31.s
+# CHECK-NEXT: 2 6 1.00 6 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LASTB_RPZ_D lastb x0, p7, z31.d
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B ld1b { z0.b }, p0/z, [sp, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B ld1b { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_IMM ld1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_D_IMM ld1b { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1B_D_IMM ld1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_H_IMM ld1b { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1B_S_SXTW ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1B_S_UXTW ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_S_IMM ld1b { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1B_S_IMM ld1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_IMM ld1b { z21.b }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_D_IMM ld1b { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1B_D_SXTW ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1B_D_UXTW ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_H_IMM ld1b { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_S_IMM ld1b { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_S ld1b { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_D ld1b { z23.d }, p3/z, [x13, x8]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_IMM ld1b { z31.b }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_D_IMM ld1b { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1B_D ld1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1B_D_IMM ld1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_H_IMM ld1b { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_S_IMM ld1b { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1B_S_IMM ld1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1B_H ld1b { z5.h }, p3/z, [x17, x16]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_SXTW_SCALED ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_UXTW_SCALED ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1D_IMM ld1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_IMM ld1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1D_IMM ld1d { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_SXTW ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_UXTW ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1D ld1d { z23.d }, p3/z, [sp, x8, lsl #3]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1D ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_SCALED ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1D_IMM ld1d { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D ld1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1D_IMM ld1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_SXTW_SCALED ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_UXTW_SCALED ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_D_IMM ld1h { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_IMM ld1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_IMM ld1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1H_S_SXTW ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1H_S_UXTW ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_S_IMM ld1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1H_S_IMM ld1h { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_D_IMM ld1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_SXTW ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_UXTW ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_IMM ld1h { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_S_IMM ld1h { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1H_S ld1h { z21.s }, p5/z, [x10, x21, lsl #1]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1H_D ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_SCALED ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_D_IMM ld1h { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D ld1h { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1H_D_IMM ld1h { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_IMM ld1h { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1H_S_IMM ld1h { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1H_S_SXTW_SCALED ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1H_S_UXTW_SCALED ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1H_S_IMM ld1h { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1H ld1h { z5.h }, p3/z, [sp, x16, lsl #1]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1H ld1h { z5.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_IMM ld1rb { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_D_IMM ld1rb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_H_IMM ld1rb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_S_IMM ld1rb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_IMM ld1rb { z31.b }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_D_IMM ld1rb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_H_IMM ld1rb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RB_S_IMM ld1rb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RD_IMM ld1rd { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RD_IMM ld1rd { z31.d }, p7/z, [sp, #504]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_D_IMM ld1rh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_IMM ld1rh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_S_IMM ld1rh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_D_IMM ld1rh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_IMM ld1rh { z31.h }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RH_S_IMM ld1rh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_B ld1rqb { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_B_IMM ld1rqb { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_B_IMM ld1rqb { z21.b }, p5/z, [x10, #112]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_B_IMM ld1rqb { z23.b }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_B_IMM ld1rqb { z31.b }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_D ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_D_IMM ld1rqd { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_D_IMM ld1rqd { z23.d }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_D_IMM ld1rqd { z23.d }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_D_IMM ld1rqd { z31.d }, p7/z, [sp, #-16]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1RQ_H ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_H_IMM ld1rqh { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_H_IMM ld1rqh { z23.h }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_H_IMM ld1rqh { z23.h }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_H_IMM ld1rqh { z31.h }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_W ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_W_IMM ld1rqw { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_W_IMM ld1rqw { z23.s }, p3/z, [x13, #-128]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_W_IMM ld1rqw { z23.s }, p3/z, [x13, #112]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RQ_W_IMM ld1rqw { z31.s }, p7/z, [sp, #-16]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_D_IMM ld1rsb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_H_IMM ld1rsb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_S_IMM ld1rsb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_D_IMM ld1rsb { z31.d }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_H_IMM ld1rsb { z31.h }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSB_S_IMM ld1rsb { z31.s }, p7/z, [sp, #63]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSH_D_IMM ld1rsh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSH_S_IMM ld1rsh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSH_D_IMM ld1rsh { z31.d }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSH_S_IMM ld1rsh { z31.s }, p7/z, [sp, #126]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSW_IMM ld1rsw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RSW_IMM ld1rsw { z31.d }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RW_D_IMM ld1rw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RW_IMM ld1rw { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RW_D_IMM ld1rw { z31.d }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1RW_IMM ld1rw { z31.s }, p7/z, [sp, #252]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_D_IMM ld1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SB_D_IMM ld1sb { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_H ld1sb { z0.h }, p0/z, [sp, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_H ld1sb { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_H_IMM ld1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1SB_S_SXTW ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_S_IMM ld1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1SB_S_IMM ld1sb { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_D_IMM ld1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SB_D_SXTW ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SB_D_UXTW ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_H_IMM ld1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_S_IMM ld1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_S ld1sb { z21.s }, p5/z, [x10, x21]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1SB_S_UXTW ld1sb { z23.s }, p5/z, [x17, z10.s, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_D ld1sb { z23.d }, p3/z, [x13, x8]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_D_IMM ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SB_D ld1sb { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SB_D_IMM ld1sb { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_H_IMM ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SB_S_IMM ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1SB_S_IMM ld1sb { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_SXTW_SCALED ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_UXTW_SCALED ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_D_IMM ld1sh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_IMM ld1sh { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1SH_S_SXTW ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1SH_S_UXTW ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_S_IMM ld1sh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1SH_S_IMM ld1sh { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_D_IMM ld1sh { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_SXTW ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_UXTW ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1SH_S ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_S_IMM ld1sh { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1SH_S ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LD1SH_D ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_SCALED ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_D_IMM ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D ld1sh { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SH_D_IMM ld1sh { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SH_S_IMM ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1SH_S_SXTW_SCALED ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1SH_S_UXTW_SCALED ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1SH_S_IMM ld1sh { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_SXTW_SCALED ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_UXTW_SCALED ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SW_D_IMM ld1sw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_IMM ld1sw { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SW_D_IMM ld1sw { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_SXTW ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_UXTW ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SW_D ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SW_D ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_SCALED ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1SW_D_IMM ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D ld1sw { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1SW_D_IMM ld1sw { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_SXTW_SCALED ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_UXTW_SCALED ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_D_IMM ld1w { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_IMM ld1w { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1W_SXTW ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * 9 V1UnitL,V1UnitV GLD1W_UXTW ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_IMM ld1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1W_IMM ld1w { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_D_IMM ld1w { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_SXTW ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_UXTW ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W ld1w { z21.s }, p5/z, [sp, x21, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_IMM ld1w { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W ld1w { z21.s }, p5/z, [x10, x21, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_D ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_SCALED ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_D_IMM ld1w { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D ld1w { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 4 9 0.67 * 9 V1UnitL[2],V1UnitV[2] GLD1W_D_IMM ld1w { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LD1W_IMM ld1w { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1W_SXTW_SCALED ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+# CHECK-NEXT: 4 11 0.67 * 11 V1UnitL[2],V1UnitV[2] GLD1W_UXTW_SCALED ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+# CHECK-NEXT: 2 11 0.33 * 11 V1UnitL,V1UnitV GLD1W_IMM ld1w { z31.s }, p7/z, [z31.s, #124]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2B ld2b { z0.b, z1.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2B_IMM ld2b { z0.b, z1.b }, p0/z, [x0]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2B_IMM ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2B_IMM ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2B ld2b { z5.b, z6.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2D ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2D_IMM ld2d { z0.d, z1.d }, p0/z, [x0]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2D_IMM ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2D_IMM ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2D ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2H ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2H_IMM ld2h { z0.h, z1.h }, p0/z, [x0]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2H_IMM ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2H_IMM ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2H ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2W ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2W_IMM ld2w { z0.s, z1.s }, p0/z, [x0]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2W_IMM ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
+# CHECK-NEXT: 4 8 1.00 * 8 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2W_IMM ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
+# CHECK-NEXT: 4 9 1.00 * 9 V1UnitL[2],V1UnitL01[2],V1UnitV[2],V1UnitV01[2] LD2W ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3B ld3b { z0.b - z2.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3B_IMM ld3b { z0.b - z2.b }, p0/z, [x0]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3B_IMM ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3B_IMM ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3B ld3b { z5.b - z7.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3D ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3D_IMM ld3d { z0.d - z2.d }, p0/z, [x0]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3D_IMM ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3D_IMM ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3D ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3H ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3H_IMM ld3h { z0.h - z2.h }, p0/z, [x0]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3H_IMM ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3H_IMM ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3H ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3W ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3W_IMM ld3w { z0.s - z2.s }, p0/z, [x0]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3W_IMM ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]
+# CHECK-NEXT: 6 11 1.50 * 11 V1UnitL[3],V1UnitL01[3],V1UnitV[3],V1UnitV01[3] LD3W_IMM ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]
+# CHECK-NEXT: 7 8 1.50 * 8 V1UnitI,V1UnitL[3],V1UnitL01[3],V1UnitS,V1UnitV[3],V1UnitV01[3] LD3W ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4B ld4b { z0.b - z3.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4B_IMM ld4b { z0.b - z3.b }, p0/z, [x0]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4B_IMM ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4B_IMM ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4B ld4b { z5.b - z8.b }, p3/z, [x17, x16]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4D ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4D_IMM ld4d { z0.d - z3.d }, p0/z, [x0]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4D_IMM ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4D_IMM ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4D ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4H ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4H_IMM ld4h { z0.h - z3.h }, p0/z, [x0]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4H_IMM ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4H_IMM ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4H ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4W ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4W_IMM ld4w { z0.s - z3.s }, p0/z, [x0]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4W_IMM ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]
+# CHECK-NEXT: 8 12 2.00 * 12 V1UnitL[4],V1UnitL01[4],V1UnitV[4],V1UnitV01[4] LD4W_IMM ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]
+# CHECK-NEXT: 10 13 2.00 * 13 V1UnitI[2],V1UnitL[4],V1UnitL01[4],V1UnitS[2],V1UnitV[4],V1UnitV01[4] LD4W ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_D ldff1b { z0.d }, p0/z, [x0, x0]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1B_D_IMM ldff1b { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_H ldff1b { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_S ldff1b { z0.s }, p0/z, [x0, x0]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1B_S_SXTW ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1B_S_UXTW ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1B_S_IMM ldff1b { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1B_D_SXTW ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1B_D_UXTW ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B ldff1b { z31.b }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1B_D ldff1b { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_D ldff1b { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1B_D_IMM ldff1b { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_H ldff1b { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1B_S ldff1b { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1B_S_IMM ldff1b { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1D ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_SXTW_SCALED ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_UXTW_SCALED ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_IMM ldff1d { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_SXTW ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_UXTW ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_SCALED ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D ldff1d { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1D ldff1d { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1D_IMM ldff1d { z31.d }, p7/z, [z31.d, #248]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H_D ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_SXTW_SCALED ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_UXTW_SCALED ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_IMM ldff1h { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H_S ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1H_S_SXTW ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1H_S_UXTW ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1H_S_IMM ldff1h { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_SXTW ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_UXTW ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_SCALED ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D ldff1h { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H_D ldff1h { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1H_D_IMM ldff1h { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H ldff1h { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1H_S_SXTW_SCALED ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1H_S_UXTW_SCALED ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1H_S ldff1h { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1H_S_IMM ldff1h { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_D ldff1sb { z0.d }, p0/z, [x0, x0]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SB_D_IMM ldff1sb { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_H ldff1sb { z0.h }, p0/z, [x0, x0]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_S ldff1sb { z0.s }, p0/z, [x0, x0]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1SB_S_SXTW ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1SB_S_UXTW ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1SB_S_IMM ldff1sb { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SB_D_SXTW ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SB_D_UXTW ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SB_D ldff1sb { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_D ldff1sb { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SB_D_IMM ldff1sb { z31.d }, p7/z, [z31.d, #31]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_H ldff1sb { z31.h }, p7/z, [sp]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SB_S ldff1sb { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1SB_S_IMM ldff1sb { z31.s }, p7/z, [z31.s, #31]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SH_D ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_SXTW_SCALED ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_UXTW_SCALED ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_IMM ldff1sh { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SH_S ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1SH_S_SXTW ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1SH_S_UXTW ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1SH_S_IMM ldff1sh { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_SXTW ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_UXTW ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_SCALED ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D ldff1sh { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SH_D ldff1sh { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SH_D_IMM ldff1sh { z31.d }, p7/z, [z31.d, #62]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1SH_S_SXTW_SCALED ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1SH_S_UXTW_SCALED ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
+# CHECK-NEXT: 2 7 0.50 * U 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SH_S ldff1sh { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1SH_S_IMM ldff1sh { z31.s }, p7/z, [z31.s, #62]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SW_D ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_SXTW_SCALED ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_UXTW_SCALED ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_IMM ldff1sw { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_SXTW ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_UXTW ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_SCALED ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D ldff1sw { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1SW_D ldff1sw { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1SW_D_IMM ldff1sw { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1W_D ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_SXTW_SCALED ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_UXTW_SCALED ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_IMM ldff1w { z0.d }, p0/z, [z0.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1W ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1W_SXTW ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
+# CHECK-NEXT: 2 9 0.33 * U 9 V1UnitL,V1UnitV GLDFF1W_UXTW ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1W_IMM ldff1w { z0.s }, p0/z, [z0.s]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_SXTW ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_UXTW ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_SCALED ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D ldff1w { z31.d }, p7/z, [sp, z31.d]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1W_D ldff1w { z31.d }, p7/z, [sp]
+# CHECK-NEXT: 4 9 0.67 * U 9 V1UnitL[2],V1UnitV[2] GLDFF1W_D_IMM ldff1w { z31.d }, p7/z, [z31.d, #124]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1W_SXTW_SCALED ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
+# CHECK-NEXT: 4 11 0.67 * U 11 V1UnitL[2],V1UnitV[2] GLDFF1W_UXTW_SCALED ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
+# CHECK-NEXT: 2 6 0.50 * U 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDFF1W ldff1w { z31.s }, p7/z, [sp]
+# CHECK-NEXT: 2 11 0.33 * U 11 V1UnitL,V1UnitV GLDFF1W_IMM ldff1w { z31.s }, p7/z, [z31.s, #124]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_IMM ldnf1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_D_IMM ldnf1b { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_H_IMM ldnf1b { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_S_IMM ldnf1b { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_IMM ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_D_IMM ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_H_IMM ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_S_IMM ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_IMM ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_D_IMM ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_H_IMM ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1B_S_IMM ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1D_IMM ldnf1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1D_IMM ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1D_IMM ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_D_IMM ldnf1h { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_IMM ldnf1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_S_IMM ldnf1h { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_D_IMM ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_IMM ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_S_IMM ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_D_IMM ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_IMM ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1H_S_IMM ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_D_IMM ldnf1sb { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_H_IMM ldnf1sb { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_S_IMM ldnf1sb { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_D_IMM ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_H_IMM ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_S_IMM ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_D_IMM ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_H_IMM ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SB_S_IMM ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_D_IMM ldnf1sh { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_S_IMM ldnf1sh { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_D_IMM ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_S_IMM ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_D_IMM ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SH_S_IMM ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SW_D_IMM ldnf1sw { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SW_D_IMM ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1SW_D_IMM ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_D_IMM ldnf1w { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_IMM ldnf1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_D_IMM ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_IMM ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_D_IMM ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 1 6 0.50 * U 6 V1UnitL,V1UnitL01 LDNF1W_IMM ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDNT1B_ZRR ldnt1b { z0.b }, p0/z, [x0, x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1B_ZRI ldnt1b { z0.b }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1B_ZRI ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1B_ZRI ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDNT1D_ZRR ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1D_ZRI ldnt1d { z0.d }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1D_ZRI ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1D_ZRI ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 7 0.50 * 7 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDNT1H_ZRR ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1H_ZRI ldnt1h { z0.h }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1H_ZRI ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1H_ZRI ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitL01,V1UnitS LDNT1W_ZRR ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1W_ZRI ldnt1w { z0.s }, p0/z, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1W_ZRI ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDNT1W_ZRI ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitM LDR_PXI ldr p0, [x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitM LDR_PXI ldr p5, [x10, #255, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitI,V1UnitL,V1UnitM LDR_PXI ldr p7, [x13, #-256, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDR_ZXI ldr z0, [x0]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDR_ZXI ldr z23, [x13, #255, mul vl]
+# CHECK-NEXT: 1 6 0.50 * 6 V1UnitL,V1UnitL01 LDR_ZXI ldr z31, [sp, #-256, mul vl]
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_B lsl z0.b, p0/m, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmZ_B lsl z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZPmZ_B lsl z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_B lsl z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZZZ_B lsl z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_D lsl z0.d, p0/m, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmZ_D lsl z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_D lsl z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_H lsl z0.h, p0/m, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmZ_H lsl z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZPmZ_H lsl z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_H lsl z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZZZ_H lsl z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_S lsl z0.s, p0/m, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmZ_S lsl z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZPmZ_S lsl z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_S lsl z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_WIDE_ZZZ_S lsl z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_B lsl z31.b, p0/m, z31.b, #7
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_B lsl z31.b, z31.b, #7
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_D lsl z31.d, p0/m, z31.d, #63
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_D lsl z31.d, z31.d, #63
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_H lsl z31.h, p0/m, z31.h, #15
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_H lsl z31.h, z31.h, #15
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZPmI_S lsl z31.s, p0/m, z31.s, #31
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSL_ZZI_S lsl z31.s, z31.s, #31
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSLR_ZPmZ_B lslr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSLR_ZPmZ_D lslr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSLR_ZPmZ_H lslr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSLR_ZPmZ_S lslr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_B lsr z0.b, p0/m, z0.b, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmZ_B lsr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZPmZ_B lsr z0.b, p0/m, z0.b, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_B lsr z0.b, z0.b, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZZZ_B lsr z0.b, z1.b, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_D lsr z0.d, p0/m, z0.d, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmZ_D lsr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_D lsr z0.d, z0.d, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_H lsr z0.h, p0/m, z0.h, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmZ_H lsr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZPmZ_H lsr z0.h, p0/m, z0.h, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_H lsr z0.h, z0.h, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZZZ_H lsr z0.h, z1.h, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_S lsr z0.s, p0/m, z0.s, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmZ_S lsr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZPmZ_S lsr z0.s, p0/m, z0.s, z1.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_S lsr z0.s, z0.s, #1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_WIDE_ZZZ_S lsr z0.s, z1.s, z2.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_B lsr z31.b, p0/m, z31.b, #8
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_B lsr z31.b, z31.b, #8
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_D lsr z31.d, p0/m, z31.d, #64
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_D lsr z31.d, z31.d, #64
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_H lsr z31.h, p0/m, z31.h, #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_H lsr z31.h, z31.h, #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZPmI_S lsr z31.s, p0/m, z31.s, #32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSR_ZZI_S lsr z31.s, z31.s, #32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSRR_ZPmZ_B lsrr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSRR_ZPmZ_D lsrr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSRR_ZPmZ_H lsrr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 LSRR_ZPmZ_S lsrr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MAD_ZPmZZ_B mad z17.b, p7/m, z4.b, z5.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MAD_ZPmZZ_H mad z29.h, p4/m, z31.h, z18.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MAD_ZPmZZ_S mad z7.s, p4/m, z5.s, z29.s
+# CHECK-NEXT: 2 5 2.00 2 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MAD_ZPmZZ_D mad z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLA_ZPmZZ_B mla z1.b, p0/m, z3.b, z3.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLA_ZPmZZ_H mla z21.h, p2/m, z31.h, z30.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLA_ZPmZZ_S mla z24.s, p3/m, z11.s, z9.s
+# CHECK-NEXT: 2 5 2.00 2 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MLA_ZPmZZ_D mla z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLS_ZPmZZ_B mls z11.b, p1/m, z28.b, z6.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLS_ZPmZZ_H mls z31.h, p0/m, z25.h, z24.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MLS_ZPmZZ_S mls z1.s, p5/m, z7.s, z13.s
+# CHECK-NEXT: 2 5 2.00 2 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MLS_ZPmZZ_D mls z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 ORR_PPzPP mov p0.b, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 SEL_PPPP mov p0.b, p0/m, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 AND_PPzPP mov p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 ORR_PPzPP mov p15.b, p15.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 SEL_PPPP mov p15.b, p15/m, p15.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 AND_PPzPP mov p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_B mov z0.b, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_B mov z0.b, b0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_B mov z0.b, p0/m, b0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_B mov z0.b, p0/m, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_B mov z0.b, p0/z, #127
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_B mov z0.b, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.d, #0xe0000000000003ff
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.d, #0xffffffffffff7fff
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.d, #32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_D mov z0.d, d0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_D mov z0.d, p0/m, d0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_D mov z0.d, p0/m, x0
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_D mov z0.d, x0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZZZ mov z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z0.h, #-256
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z0.h, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z0.h, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.h, #32767
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_H mov z0.h, h0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_H mov z0.h, p0/m, h0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_H mov z0.h, p0/m, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_H mov z0.h, p0/z, #32512
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_H mov z0.h, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_Q mov z0.q, q0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.s, #0xffff7fff
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUPM_ZI mov z0.s, #32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_S mov z0.s, p0/m, s0
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_S mov z0.s, p0/m, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_S mov z0.s, s0
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_S mov z0.s, w0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z21.d, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z21.d, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z21.d, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z21.d, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_D mov z21.d, p0/z, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_D mov z21.d, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_D mov z21.d, p0/z, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_D mov z21.d, p0/z, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_D mov z21.d, p15/m, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_D mov z21.d, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z21.h, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z21.h, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z21.h, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z21.h, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_H mov z21.h, p0/z, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_H mov z21.h, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_H mov z21.h, p0/z, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_H mov z21.h, p0/z, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_H mov z21.h, p15/m, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_H mov z21.h, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z21.s, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z21.s, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z21.s, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z21.s, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_S mov z21.s, p0/z, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_S mov z21.s, p0/z, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_S mov z21.s, p0/z, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_S mov z21.s, p0/z, #32512
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_S mov z21.s, p15/m, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_S mov z21.s, p15/m, #-32768
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_B mov z31.b, p15/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_B mov z31.b, p7/m, b31
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 MOVPRFX_ZZ movprfx z31, z6
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_B mov z31.b, p7/m, wsp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 MOVPRFX_ZPmZ_B movprfx z31.b, p0/m, z4.b
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_B mov z31.b, p0/m, wsp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_B mov z31.b, z31.b[63]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_D mov z31.d, p15/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_D mov z31.d, p7/m, d31
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 MOVPRFX_ZPzZ_D movprfx z31.d, p7/z, z6.d
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_D mov z31.d, p7/m, sp
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_D mov z31.d, sp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZZZ mov z31.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_D mov z31.d, z31.d[7]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_H mov z31.h, p15/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_H mov z31.h, p7/m, h31
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_H mov z31.h, p7/m, wsp
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_H mov z31.h, wsp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_H mov z31.h, z31.h[31]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_S mov z31.s, p15/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmV_S mov z31.s, p7/m, s31
+# CHECK-NEXT: 2 5 1.00 5 V1UnitI,V1UnitM,V1UnitM0,V1UnitV,V1UnitV01 CPY_ZPmR_S mov z31.s, p7/m, wsp
+# CHECK-NEXT: 1 3 1.00 3 V1UnitI,V1UnitM,V1UnitM0 DUP_ZR_S mov z31.s, wsp
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_S mov z31.s, z31.s[15]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_B mov z5.b, #-1
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_B mov z5.b, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_B mov z5.b, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_B mov z5.b, p0/z, #-1
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_B mov z5.b, p0/z, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPzI_B mov z5.b, p0/z, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 CPY_ZPmI_B mov z5.b, p15/m, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_D mov z5.d, #-6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_H mov z5.h, #-6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZZI_Q mov z5.q, z17.q[3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 DUP_ZI_S mov z5.s, #-6
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ORRS_PPzPP movs p0.b, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ANDS_PPzPP movs p0.b, p0/z, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ORRS_PPzPP movs p15.b, p15.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ANDS_PPzPP movs p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 0.07 U 1 MRS mrs x3, ID_AA64ZFR0_EL1
+# CHECK-NEXT: 1 1 0.07 U 1 MRS mrs x3, ZCR_EL1
+# CHECK-NEXT: 1 1 0.07 U 1 MRS mrs x3, ZCR_EL12
+# CHECK-NEXT: 1 1 0.07 U 1 MRS mrs x3, ZCR_EL2
+# CHECK-NEXT: 1 1 0.07 U 1 MRS mrs x3, ZCR_EL3
+# CHECK-NEXT: 1 1 0.07 U 1 MSR msr ZCR_EL1, x3
+# CHECK-NEXT: 2 5 2.00 2 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MSB_ZPmZZ_D msb z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MSB_ZPmZZ_B msb z18.b, p1/m, z27.b, z0.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MSB_ZPmZZ_H msb z27.h, p5/m, z23.h, z1.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MSB_ZPmZZ_S msb z26.s, p2/m, z0.s, z2.s
+# CHECK-NEXT: 1 1 0.07 U 1 MSR msr ZCR_EL12, x3
+# CHECK-NEXT: 1 1 0.07 U 1 MSR msr ZCR_EL2, x3
+# CHECK-NEXT: 1 1 0.07 U 1 MSR msr ZCR_EL3, x3
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZPmZ_B mul z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MUL_ZPmZ_D mul z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZPmZ_H mul z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZPmZ_S mul z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_B mul z31.b, z31.b, #-128
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_B mul z31.b, z31.b, #127
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MUL_ZI_D mul z31.d, z31.d, #-128
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] MUL_ZI_D mul z31.d, z31.d, #127
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_H mul z31.h, z31.h, #-128
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_H mul z31.h, z31.h, #127
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_S mul z31.s, z31.s, #-128
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 MUL_ZI_S mul z31.s, z31.s, #127
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 NAND_PPzPP nand p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 NAND_PPzPP nand p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] NANDS_PPzPP nands p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] NANDS_PPzPP nands p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_B neg z0.b, p0/m, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_D neg z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_H neg z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_S neg z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_B neg z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_D neg z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_H neg z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NEG_ZPmZ_S neg z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 NOR_PPzPP nor p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 NOR_PPzPP nor p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] NORS_PPzPP nors p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] NORS_PPzPP nors p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 EOR_PPzPP not p0.b, p0/z, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 EOR_PPzPP not p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NOT_ZPmZ_B not z31.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NOT_ZPmZ_D not z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NOT_ZPmZ_H not z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 NOT_ZPmZ_S not z31.s, p7/m, z31.s
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] EORS_PPzPP nots p0.b, p0/z, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] EORS_PPzPP nots p15.b, p15/z, p15.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 ORN_PPzPP orn p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 ORN_PPzPP orn p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ORNS_PPzPP orns p0.b, p0/z, p0.b, p0.b
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ORNS_PPzPP orns p15.b, p15/z, p15.b, p15.b
+# CHECK-NEXT: 1 1 1.00 1 V1UnitI,V1UnitM,V1UnitM0 ORR_PPzPP orr p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z0.d, z0.d, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z0.d, z0.d, #0xfffffffffffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z0.s, z0.s, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z0.s, z0.s, #0xfffffff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZZZ orr z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z23.h, z23.h, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z23.h, z23.h, #0xfff9
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZPmZ_B orr z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZPmZ_D orr z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZPmZ_H orr z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZPmZ_S orr z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z5.b, z5.b, #0x6
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ORR_ZI orr z5.b, z5.b, #0xf9
+# CHECK-NEXT: 2 2 2.00 2 V1UnitI[2],V1UnitM[2],V1UnitM0[2] ORRS_PPzPP orrs p0.b, p0/z, p0.b, p1.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ORV_VPZ_B orv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ORV_VPZ_D orv d0, p7, z31.d
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ORV_VPZ_H orv h0, p7, z31.h
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV01[4] ORV_VPZ_S orv s0, p7, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PFALSE pfalse p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PFIRST_B pfirst p0.b, p15, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PFIRST_B pfirst p15.b, p15, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PNEXT_B pnext p0.b, p15, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PNEXT_D pnext p0.d, p15, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PNEXT_H pnext p0.h, p15, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PNEXT_S pnext p0.s, p15, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PNEXT_B pnext p15.b, p15, p15.b
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_PRI prfb #14, p5, [x21]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_PRR prfb pldl1keep, p7, [x4, x9]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_S_UXTW_SCALED prfb pldl3strm, p4, [x3, z15.s, uxtw]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_D_UXTW_SCALED prfb pldl1strm, p7, [x28, z4.d, uxtw]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_D_SCALED prfb pstl3keep, p2, [x18, z19.d]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_S_PZI prfb pstl3keep, p1, [z28.s]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFB_D_PZI prfb pstl2strm, p5, [z25.d]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_PRI prfd pstl3strm, p3, [x21]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_PRR prfd pstl2keep, p3, [x24, x24, lsl #3]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_S_SXTW_SCALED prfd pstl1strm, p3, [x27, z27.s, sxtw #3]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_D_UXTW_SCALED prfd pstl1keep, p0, [x21, z2.d, uxtw #3]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_D_SCALED prfd pldl1strm, p7, [x22, z22.d, lsl #3]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_S_PZI prfd pldl2strm, p1, [z2.s]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFD_D_PZI prfd #15, p1, [z17.d]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_PRI prfh pldl2strm, p3, [x17]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_PRR prfh pstl2keep, p1, [x28, x9, lsl #1]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_S_UXTW_SCALED prfh pldl1strm, p6, [x0, z10.s, uxtw #1]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_D_UXTW_SCALED prfh pldl3keep, p7, [x24, z21.d, uxtw #1]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_D_SCALED prfh pstl1strm, p5, [x10, z6.d, lsl #1]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_S_PZI prfh pldl3strm, p6, [z0.s]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFH_D_PZI prfh pstl2keep, p2, [z21.d]
+# CHECK-NEXT: 1 4 0.33 U 4 V1UnitL PRFMui prfm pldl1strm, [x5]
+# CHECK-NEXT: 1 4 0.33 U 4 V1UnitL PRFMroX prfm pldl1keep, [x25, x16]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_PRI prfw pldl2strm, p2, [x4]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_PRR prfw pstl1keep, p4, [x18, x21, lsl #2]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_S_UXTW_SCALED prfw pldl2strm, p0, [x15, z6.s, uxtw #2]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_D_SXTW_SCALED prfw pstl2keep, p0, [x27, z18.d, sxtw #2]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_D_SCALED prfw pstl2keep, p3, [x19, z8.d, lsl #2]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_S_PZI prfw #7, p7, [z27.s]
+# CHECK-NEXT: 1 4 0.50 * * U 4 V1UnitL,V1UnitL01 PRFW_D_PZI prfw #7, p1, [z20.d]
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTEST_PP ptest p15, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTEST_PP ptest p15, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_B ptrue p0.b, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_D ptrue p0.d, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_H ptrue p0.h, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p0.s, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_B ptrue p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_D ptrue p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_H ptrue p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #15
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #17
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #18
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #19
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #20
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #21
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #22
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #23
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #24
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #25
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #26
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #27
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, #28
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, mul3
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, mul4
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl128
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl256
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl3
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl4
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl5
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl6
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl64
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl7
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PTRUE_S ptrue p7.s, vl8
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_B ptrues p0.b, pow2
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_D ptrues p0.d, pow2
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_H ptrues p0.h, pow2
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p0.s, pow2
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_B ptrues p15.b
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_D ptrues p15.d
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_H ptrues p15.h
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p15.s
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #14
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #15
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #16
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #17
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #18
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #19
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #20
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #21
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #22
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #23
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #24
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #25
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #26
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #27
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, #28
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, mul3
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, mul4
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl1
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl128
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl16
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl2
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl256
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl3
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl32
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl4
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl5
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl6
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl64
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl7
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] PTRUES_S ptrues p7.s, vl8
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PUNPKHI_PP punpkhi p0.h, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PUNPKHI_PP punpkhi p15.h, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PUNPKLO_PP punpklo p0.h, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 PUNPKLO_PP punpklo p15.h, p15.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 RBIT_ZPmZ_B rbit z0.b, p7/m, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 RBIT_ZPmZ_D rbit z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 RBIT_ZPmZ_H rbit z0.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 RBIT_ZPmZ_S rbit z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 * U 2 V1UnitI,V1UnitM,V1UnitM0 RDFFR_P rdffr p0.b
+# CHECK-NEXT: 2 3 2.00 * U 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] RDFFR_PPz rdffr p0.b, p0/z
+# CHECK-NEXT: 1 2 1.00 * U 2 V1UnitI,V1UnitM,V1UnitM0 RDFFR_P rdffr p15.b
+# CHECK-NEXT: 2 3 2.00 * U 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] RDFFR_PPz rdffr p15.b, p15/z
+# CHECK-NEXT: 1 4 0.50 U 4 V1UnitI,V1UnitM RDFFRS_PPz rdffrs p0.b, p0/z
+# CHECK-NEXT: 1 4 0.50 U 4 V1UnitI,V1UnitM RDFFRS_PPz rdffrs p15.b, p15/z
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 RDVLI_XI rdvl x0, #0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 RDVLI_XI rdvl x21, #-32
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 RDVLI_XI rdvl x23, #31
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 RDVLI_XI rdvl xzr, #-1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 REV_PP_H rev p1.h, p2.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REV_ZZ_B rev z0.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REV_ZZ_D rev z0.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REV_ZZ_H rev z0.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REV_ZZ_S rev z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVB_ZPmZ_D revb z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVB_ZPmZ_H revb z0.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVB_ZPmZ_S revb z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVH_ZPmZ_D revh z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVH_ZPmZ_S revh z0.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 REVW_ZPmZ_D revw z0.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SABD_ZPmZ_B sabd z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SABD_ZPmZ_D sabd z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SABD_ZPmZ_H sabd z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SABD_ZPmZ_S sabd z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] SADDV_VPZ_B saddv d0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SADDV_VPZ_H saddv d0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SADDV_VPZ_S saddv d0, p7, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SCVTF_ZPmZ_DtoD scvtf z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SCVTF_ZPmZ_StoD scvtf z18.d, p3/m, z16.s
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] SCVTF_ZPmZ_HtoH scvtf z0.h, p0/m, z0.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] SCVTF_ZPmZ_StoH scvtf z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SCVTF_ZPmZ_DtoH scvtf z18.h, p1/m, z14.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SCVTF_ZPmZ_DtoS scvtf z0.s, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] SCVTF_ZPmZ_StoS scvtf z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 20 7.00 20 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] SDIV_ZPmZ_D sdiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 12 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] SDIV_ZPmZ_S sdiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 20 7.00 20 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] SDIVR_ZPmZ_D sdivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 12 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] SDIVR_ZPmZ_S sdivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 1.00 1 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SDOT_ZZZI_D sdot z0.d, z1.h, z15.h[1]
+# CHECK-NEXT: 1 4 1.00 1 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SDOT_ZZZ_D sdot z0.d, z1.h, z31.h
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 SDOT_ZZZ_S sdot z0.s, z1.b, z31.b
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 SDOT_ZZZI_S sdot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_B sel z23.b, p11, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_D sel z23.d, p11, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_H sel z23.h, p11, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SEL_ZPZZ_S sel z23.s, p11, z13.s, z8.s
+# CHECK-NEXT: 1 2 1.00 * U 2 V1UnitI,V1UnitM,V1UnitM0 SETFFR setffr
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_B smax z0.b, z0.b, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_D smax z0.d, z0.d, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_H smax z0.h, z0.h, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_S smax z0.s, z0.s, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZPmZ_B smax z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_B smax z31.b, z31.b, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZPmZ_D smax z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_D smax z31.d, z31.d, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZPmZ_H smax z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_H smax z31.h, z31.h, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZPmZ_S smax z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMAX_ZI_S smax z31.s, z31.s, #127
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] SMAXV_VPZ_B smaxv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SMAXV_VPZ_H smaxv h0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SMAXV_VPZ_S smaxv s0, p7, z31.s
+# CHECK-NEXT: 2 8 0.50 8 V1UnitV[2],V1UnitV01 SMAXV_VPZ_D smaxv d24, p5, z24.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_B smin z0.b, z0.b, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_D smin z0.d, z0.d, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_H smin z0.h, z0.h, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_S smin z0.s, z0.s, #-128
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZPmZ_B smin z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_B smin z31.b, z31.b, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZPmZ_D smin z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_D smin z31.d, z31.d, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZPmZ_H smin z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_H smin z31.h, z31.h, #127
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZPmZ_S smin z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SMIN_ZI_S smin z31.s, z31.s, #127
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] SMINV_VPZ_B sminv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SMINV_VPZ_H sminv h0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] SMINV_VPZ_S sminv s0, p7, z31.s
+# CHECK-NEXT: 2 8 0.50 8 V1UnitV[2],V1UnitV01 SMINV_VPZ_D sminv d17, p2, z18.d
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 SMMLA_ZZZ smmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SMULH_ZPmZ_B smulh z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] SMULH_ZPmZ_D smulh z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SMULH_ZPmZ_H smulh z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SMULH_ZPmZ_S smulh z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SPLICE_ZPZ_B splice z31.b, p7, z31.b, z31.b
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SPLICE_ZPZ_D splice z31.d, p7, z31.d, z31.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SPLICE_ZPZ_H splice z31.h, p7, z31.h, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SPLICE_ZPZ_S splice z31.s, p7, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_B sqadd z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZZZ_B sqadd z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_D sqadd z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_D sqadd z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZZZ_D sqadd z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_H sqadd z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_H sqadd z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZZZ_H sqadd z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_S sqadd z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_S sqadd z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZZZ_S sqadd z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_B sqadd z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_D sqadd z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_H sqadd z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQADD_ZI_S sqadd z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiI sqdecb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiI sqdecb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiI sqdecb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiI sqdecb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiI sqdecb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiWdI sqdecb x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiWdI sqdecb x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiWdI sqdecb x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECB_XPiWdI sqdecb x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiI sqdecd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiI sqdecd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiI sqdecd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiI sqdecd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiI sqdecd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiWdI sqdecd x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiWdI sqdecd x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiWdI sqdecd x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECD_XPiWdI sqdecd x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECD_ZPiI sqdecd z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECD_ZPiI sqdecd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECD_ZPiI sqdecd z0.d, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECD_ZPiI sqdecd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiI sqdech x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiI sqdech x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiI sqdech x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiI sqdech x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiI sqdech x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiWdI sqdech x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiWdI sqdech x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiWdI sqdech x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECH_XPiWdI sqdech x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECH_ZPiI sqdech z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECH_ZPiI sqdech z0.h, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECH_ZPiI sqdech z0.h, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECH_ZPiI sqdech z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XP_B sqdecp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XP_D sqdecp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XP_H sqdecp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XP_S sqdecp x0, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XPWd_B sqdecp xzr, p15.b, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XPWd_D sqdecp xzr, p15.d, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XPWd_H sqdecp xzr, p15.h, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECP_XPWd_S sqdecp xzr, p15.s, wzr
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQDECP_ZP_D sqdecp z0.d, p0.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQDECP_ZP_H sqdecp z0.h, p0.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQDECP_ZP_S sqdecp z0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiI sqdecw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiI sqdecw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiI sqdecw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiI sqdecw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiI sqdecw x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiWdI sqdecw x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiWdI sqdecw x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiWdI sqdecw x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQDECW_XPiWdI sqdecw x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECW_ZPiI sqdecw z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECW_ZPiI sqdecw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECW_ZPiI sqdecw z0.s, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQDECW_ZPiI sqdecw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiI sqincb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiI sqincb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiI sqincb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiI sqincb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiI sqincb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiWdI sqincb x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiWdI sqincb x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiWdI sqincb x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCB_XPiWdI sqincb x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiI sqincd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiI sqincd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiI sqincd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiI sqincd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiI sqincd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiWdI sqincd x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiWdI sqincd x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiWdI sqincd x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCD_XPiWdI sqincd x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCD_ZPiI sqincd z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCD_ZPiI sqincd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCD_ZPiI sqincd z0.d, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCD_ZPiI sqincd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiI sqinch x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiI sqinch x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiI sqinch x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiI sqinch x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiI sqinch x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiWdI sqinch x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiWdI sqinch x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiWdI sqinch x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCH_XPiWdI sqinch x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCH_ZPiI sqinch z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCH_ZPiI sqinch z0.h, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCH_ZPiI sqinch z0.h, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCH_ZPiI sqinch z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XP_B sqincp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XP_D sqincp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XP_H sqincp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XP_S sqincp x0, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XPWd_B sqincp xzr, p15.b, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XPWd_D sqincp xzr, p15.d, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XPWd_H sqincp xzr, p15.h, wzr
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCP_XPWd_S sqincp xzr, p15.s, wzr
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQINCP_ZP_D sqincp z0.d, p0.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQINCP_ZP_H sqincp z0.h, p0.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 SQINCP_ZP_S sqincp z0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiI sqincw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiI sqincw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiI sqincw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiI sqincw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiI sqincw x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiWdI sqincw x0, w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiWdI sqincw x0, w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiWdI sqincw x0, w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 SQINCW_XPiWdI sqincw x0, w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCW_ZPiI sqincw z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCW_ZPiI sqincw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCW_ZPiI sqincw z0.s, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 SQINCW_ZPiI sqincw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_B sqsub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZZZ_B sqsub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_D sqsub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_D sqsub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZZZ_D sqsub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_H sqsub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_H sqsub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZZZ_H sqsub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_S sqsub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_S sqsub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZZZ_S sqsub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_B sqsub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_D sqsub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_H sqsub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SQSUB_ZI_S sqsub z31.s, z31.s, #65280
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B st1b { z0.b }, p0, [x0, x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_IMM st1b { z0.b }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_D st1b { z0.d }, p0, [x0, x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1B_D_SXTW st1b { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1B_D_UXTW st1b { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1B_D st1b { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_D_IMM st1b { z0.d }, p0, [x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1B_D_IMM st1b { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_H st1b { z0.h }, p0, [x0, x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_H_IMM st1b { z0.h }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_S st1b { z0.s }, p0, [x0, x0]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1B_S_SXTW st1b { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1B_S_UXTW st1b { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_S_IMM st1b { z0.s }, p0, [x0]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1B_S_IMM st1b { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_IMM st1b { z21.b }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_D_IMM st1b { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_H_IMM st1b { z21.h }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_S_IMM st1b { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_IMM st1b { z31.b }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_D_IMM st1b { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1B_D_IMM st1b { z31.d }, p7, [z31.d, #31]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_H_IMM st1b { z31.h }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1B_S_IMM st1b { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1B_S_IMM st1b { z31.s }, p7, [z31.s, #31]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1D st1d { z0.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_SCALED st1d { z0.d }, p0, [x0, z0.d, lsl #3]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_SXTW_SCALED st1d { z0.d }, p0, [x0, z0.d, sxtw #3]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_SXTW st1d { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_UXTW_SCALED st1d { z0.d }, p0, [x0, z0.d, uxtw #3]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_UXTW st1d { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D st1d { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1D_IMM st1d { z0.d }, p0, [x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_IMM st1d { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1D_IMM st1d { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1D_IMM st1d { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1D_IMM st1d { z31.d }, p7, [z31.d, #248]
+# CHECK-NEXT: 3 2 0.50 * 2 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV ST1H_D st1h { z0.d }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_SCALED st1h { z0.d }, p0, [x0, z0.d, lsl #1]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_SXTW_SCALED st1h { z0.d }, p0, [x0, z0.d, sxtw #1]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_SXTW st1h { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_UXTW_SCALED st1h { z0.d }, p0, [x0, z0.d, uxtw #1]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_UXTW st1h { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D st1h { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_D_IMM st1h { z0.d }, p0, [x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_IMM st1h { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 3 2 0.50 * 2 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV ST1H st1h { z0.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_IMM st1h { z0.h }, p0, [x0]
+# CHECK-NEXT: 3 2 0.50 * 2 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV ST1H_S st1h { z0.s }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_SXTW_SCALED st1h { z0.s }, p0, [x0, z0.s, sxtw #1]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_SXTW st1h { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_UXTW_SCALED st1h { z0.s }, p0, [x0, z0.s, uxtw #1]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_UXTW st1h { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_S_IMM st1h { z0.s }, p0, [x0]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_IMM st1h { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_D_IMM st1h { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_IMM st1h { z21.h }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_S_IMM st1h { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_D_IMM st1h { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1H_D_IMM st1h { z31.d }, p7, [z31.d, #62]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_IMM st1h { z31.h }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1H_S_IMM st1h { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1H_S_IMM st1h { z31.s }, p7, [z31.s, #62]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_D st1w { z0.d }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_SCALED st1w { z0.d }, p0, [x0, z0.d, lsl #2]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_SXTW_SCALED st1w { z0.d }, p0, [x0, z0.d, sxtw #2]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_SXTW st1w { z0.d }, p0, [x0, z0.d, sxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_UXTW_SCALED st1w { z0.d }, p0, [x0, z0.d, uxtw #2]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_UXTW st1w { z0.d }, p0, [x0, z0.d, uxtw]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D st1w { z0.d }, p0, [x0, z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_D_IMM st1w { z0.d }, p0, [x0]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_IMM st1w { z0.d }, p7, [z0.d]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W st1w { z0.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_SXTW_SCALED st1w { z0.s }, p0, [x0, z0.s, sxtw #2]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_SXTW st1w { z0.s }, p0, [x0, z0.s, sxtw]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_UXTW_SCALED st1w { z0.s }, p0, [x0, z0.s, uxtw #2]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_UXTW st1w { z0.s }, p0, [x0, z0.s, uxtw]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_IMM st1w { z0.s }, p0, [x0]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_IMM st1w { z0.s }, p7, [z0.s]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_D_IMM st1w { z21.d }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_IMM st1w { z21.s }, p5, [x10, #5, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_D_IMM st1w { z31.d }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 2 6 0.50 * 6 V1UnitL,V1UnitL01,V1UnitV SST1W_D_IMM st1w { z31.d }, p7, [z31.d, #124]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV ST1W_IMM st1w { z31.s }, p7, [sp, #-1, mul vl]
+# CHECK-NEXT: 4 10 1.00 * 10 V1UnitL[2],V1UnitL01[2],V1UnitV[2] SST1W_IMM st1w { z31.s }, p7, [z31.s, #124]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2B st2b { z0.b, z1.b }, p0, [x0, x0]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2B_IMM st2b { z0.b, z1.b }, p0, [x0]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2B_IMM st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2B_IMM st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2B st2b { z5.b, z6.b }, p3, [x17, x16]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2D st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2D_IMM st2d { z0.d, z1.d }, p0, [x0]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2D_IMM st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2D_IMM st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2D st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 3 4 0.50 * 4 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV ST2H st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2H_IMM st2h { z0.h, z1.h }, p0, [x0]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2H_IMM st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2H_IMM st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 3 4 0.50 * 4 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV ST2H st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2W st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2W_IMM st2w { z0.s, z1.s }, p0, [x0]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2W_IMM st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2W_IMM st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]
+# CHECK-NEXT: 2 4 0.50 * 4 V1UnitL,V1UnitL01,V1UnitV ST2W st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3B st3b { z0.b - z2.b }, p0, [x0, x0]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3B_IMM st3b { z0.b - z2.b }, p0, [x0]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3B_IMM st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3B_IMM st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3B st3b { z5.b - z7.b }, p3, [x17, x16]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3D st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3D_IMM st3d { z0.d - z2.d }, p0, [x0]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3D_IMM st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3D_IMM st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3D st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3H st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3H_IMM st3h { z0.h - z2.h }, p0, [x0]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3H_IMM st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3H_IMM st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3H st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3W st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3W_IMM st3w { z0.s - z2.s }, p0, [x0]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3W_IMM st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]
+# CHECK-NEXT: 10 7 2.50 * 7 V1UnitL[5],V1UnitL01[5],V1UnitV[5] ST3W_IMM st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]
+# CHECK-NEXT: 15 7 2.50 * 7 V1UnitI[5],V1UnitL[5],V1UnitL01[5],V1UnitS[5],V1UnitV[5] ST3W st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4B st4b { z0.b - z3.b }, p0, [x0, x0]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4B_IMM st4b { z0.b - z3.b }, p0, [x0]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4B_IMM st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4B_IMM st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4B st4b { z5.b - z8.b }, p3, [x17, x16]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4D st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4D_IMM st4d { z0.d - z3.d }, p0, [x0]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4D_IMM st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4D_IMM st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4D st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4H st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4H_IMM st4h { z0.h - z3.h }, p0, [x0]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4H_IMM st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4H_IMM st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4H st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4W st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4W_IMM st4w { z0.s - z3.s }, p0, [x0]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4W_IMM st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]
+# CHECK-NEXT: 18 19 4.50 * 19 V1UnitL[9],V1UnitL01[9],V1UnitV[9] ST4W_IMM st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]
+# CHECK-NEXT: 27 11 4.50 * 11 V1UnitI[9],V1UnitL[9],V1UnitL01[9],V1UnitS[9],V1UnitV[9] ST4W st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1B_ZRR stnt1b { z0.b }, p0, [x0, x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1B_ZRI stnt1b { z0.b }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1B_ZRI stnt1b { z21.b }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1B_ZRI stnt1b { z23.b }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1D_ZRR stnt1d { z0.d }, p0, [x0, x0, lsl #3]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1D_ZRI stnt1d { z0.d }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1D_ZRI stnt1d { z21.d }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1D_ZRI stnt1d { z23.d }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 3 2 0.50 * 2 V1UnitI,V1UnitL,V1UnitL01,V1UnitS,V1UnitV STNT1H_ZRR stnt1h { z0.h }, p0, [x0, x0, lsl #1]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1H_ZRI stnt1h { z0.h }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1H_ZRI stnt1h { z21.h }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1H_ZRI stnt1h { z23.h }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1W_ZRR stnt1w { z0.s }, p0, [x0, x0, lsl #2]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1W_ZRI stnt1w { z0.s }, p0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1W_ZRI stnt1w { z21.s }, p5, [x10, #7, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STNT1W_ZRI stnt1w { z23.s }, p3, [x13, #-8, mul vl]
+# CHECK-NEXT: 1 1 0.50 * 1 V1UnitL,V1UnitL01 STR_PXI str p0, [x0]
+# CHECK-NEXT: 1 1 0.50 * 1 V1UnitL,V1UnitL01 STR_PXI str p15, [sp, #-256, mul vl]
+# CHECK-NEXT: 1 1 0.50 * 1 V1UnitL,V1UnitL01 STR_PXI str p5, [x10, #255, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STR_ZXI str z0, [x0]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STR_ZXI str z21, [x10, #-256, mul vl]
+# CHECK-NEXT: 2 2 0.50 * 2 V1UnitL,V1UnitL01,V1UnitV STR_ZXI str z31, [sp, #255, mul vl]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_B sub z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_B sub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_B sub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_D sub z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_D sub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_D sub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_D sub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_H sub z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_H sub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_H sub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_H sub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_S sub z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_S sub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_S sub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_S sub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_B sub z21.b, p5/m, z21.b, z10.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_B sub z21.b, z10.b, z21.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_D sub z21.d, p5/m, z21.d, z10.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_D sub z21.d, z10.d, z21.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_H sub z21.h, p5/m, z21.h, z10.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_H sub z21.h, z10.h, z21.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_S sub z21.s, p5/m, z21.s, z10.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_S sub z21.s, z10.s, z21.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_B sub z23.b, p3/m, z23.b, z13.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_B sub z23.b, z13.b, z8.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_D sub z23.d, p3/m, z23.d, z13.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_D sub z23.d, z13.d, z8.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_H sub z23.h, p3/m, z23.h, z13.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_H sub z23.h, z13.h, z8.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_S sub z23.s, p3/m, z23.s, z13.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_S sub z23.s, z13.s, z8.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_B sub z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_B sub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_B sub z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_D sub z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_D sub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_D sub z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_H sub z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_H sub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_H sub z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZPmZ_S sub z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZI_S sub z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUB_ZZZ_S sub z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZPmZ_B subr z0.b, p0/m, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_B subr z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZPmZ_D subr z0.d, p0/m, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_D subr z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_D subr z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZPmZ_H subr z0.h, p0/m, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_H subr z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_H subr z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZPmZ_S subr z0.s, p0/m, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_S subr z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_S subr z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_B subr z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_D subr z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_H subr z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUBR_ZI_S subr z31.s, z31.s, #65280
+# CHECK-NEXT: 1 3 0.25 1 V1UnitV SUDOT_ZZZI sudot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKHI_ZZ_D sunpkhi z31.d, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKHI_ZZ_H sunpkhi z31.h, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKHI_ZZ_S sunpkhi z31.s, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKLO_ZZ_D sunpklo z31.d, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKLO_ZZ_H sunpklo z31.h, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 SUNPKLO_ZZ_S sunpklo z31.s, z31.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_D sxtb z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_H sxtb z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_S sxtb z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_D sxtb z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_H sxtb z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTB_ZPmZ_S sxtb z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTH_ZPmZ_D sxth z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTH_ZPmZ_S sxth z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTH_ZPmZ_D sxth z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTH_ZPmZ_S sxth z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTW_ZPmZ_D sxtw z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 SXTW_ZPmZ_D sxtw z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TBL_ZZZ_B tbl z31.b, { z31.b }, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TBL_ZZZ_D tbl z31.d, { z31.d }, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TBL_ZZZ_H tbl z31.h, { z31.h }, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TBL_ZZZ_S tbl z31.s, { z31.s }, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN1_PPP_B trn1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN1_PPP_D trn1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN1_PPP_H trn1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN1_PPP_S trn1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN1_ZZZ_B trn1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN1_ZZZ_D trn1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN1_ZZZ_H trn1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN1_ZZZ_S trn1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN2_PPP_B trn2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN2_PPP_D trn2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN2_PPP_H trn2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 TRN2_PPP_S trn2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN2_ZZZ_B trn2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN2_ZZZ_D trn2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN2_ZZZ_H trn2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 TRN2_ZZZ_S trn2 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UABD_ZPmZ_B uabd z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UABD_ZPmZ_D uabd z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UABD_ZPmZ_H uabd z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UABD_ZPmZ_S uabd z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] UADDV_VPZ_B uaddv d0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UADDV_VPZ_H uaddv d0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UADDV_VPZ_S uaddv d0, p7, z31.s
+# CHECK-NEXT: 2 8 0.50 8 V1UnitV[2],V1UnitV01 UADDV_VPZ_D uaddv d28, p6, z6.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UCVTF_ZPmZ_DtoD ucvtf z0.d, p0/m, z0.d
+# CHECK-NEXT: 4 6 4.00 6 V1UnitV[4],V1UnitV0[4],V1UnitV01[4],V1UnitV02[4] UCVTF_ZPmZ_HtoH ucvtf z0.h, p0/m, z0.h
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] UCVTF_ZPmZ_StoH ucvtf z0.h, p0/m, z0.s
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UCVTF_ZPmZ_DtoH ucvtf z30.h, p2/m, z24.d
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UCVTF_ZPmZ_DtoS ucvtf z0.s, p0/m, z0.d
+# CHECK-NEXT: 2 4 2.00 4 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] UCVTF_ZPmZ_StoS ucvtf z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 20 7.00 20 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] UDIV_ZPmZ_D udiv z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 12 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] UDIV_ZPmZ_S udiv z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 20 7.00 20 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] UDIVR_ZPmZ_D udivr z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 12 7.00 12 V1UnitV[7],V1UnitV0[7],V1UnitV01[7],V1UnitV02[7] UDIVR_ZPmZ_S udivr z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 4 1.00 1 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UDOT_ZZZI_D udot z0.d, z1.h, z15.h[1]
+# CHECK-NEXT: 1 4 1.00 1 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UDOT_ZZZ_D udot z0.d, z1.h, z31.h
+# CHECK-NEXT: 1 3 1.00 3 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UCVTF_ZPmZ_StoD ucvtf z24.d, p5/m, z9.s
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 UDOT_ZZZ_S udot z0.s, z1.b, z31.b
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 UDOT_ZZZI_S udot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZI_B umax z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZPmZ_B umax z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZI_B umax z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZPmZ_D umax z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZPmZ_H umax z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMAX_ZPmZ_S umax z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] UMAXV_VPZ_B umaxv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UMAXV_VPZ_H umaxv h0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UMAXV_VPZ_S umaxv s0, p7, z31.s
+# CHECK-NEXT: 2 8 0.50 8 V1UnitV[2],V1UnitV01 UMAXV_VPZ_D umaxv d11, p4, z11.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZI_B umin z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZPmZ_B umin z31.b, p7/m, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZI_B umin z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZPmZ_D umin z31.d, p7/m, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZPmZ_H umin z31.h, p7/m, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZPmZ_S umin z31.s, p7/m, z31.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UMIN_ZI_S umin z21.s, z21.s, #139
+# CHECK-NEXT: 5 14 2.00 14 V1UnitV[5],V1UnitV0,V1UnitV1[2],V1UnitV01[3],V1UnitV02,V1UnitV13[3] UMINV_VPZ_B uminv b0, p7, z31.b
+# CHECK-NEXT: 4 12 2.00 12 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UMINV_VPZ_H uminv h0, p7, z31.h
+# CHECK-NEXT: 4 10 2.00 10 V1UnitV[4],V1UnitV1[2],V1UnitV01[3],V1UnitV13[2] UMINV_VPZ_S uminv s0, p7, z31.s
+# CHECK-NEXT: 2 8 0.50 8 V1UnitV[2],V1UnitV01 UMINV_VPZ_D uminv d24, p5, z29.d
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 UMMLA_ZZZ ummla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UMULH_ZPmZ_B umulh z0.b, p7/m, z0.b, z31.b
+# CHECK-NEXT: 2 5 2.00 5 V1UnitV[2],V1UnitV0[2],V1UnitV01[2],V1UnitV02[2] UMULH_ZPmZ_D umulh z0.d, p7/m, z0.d, z31.d
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UMULH_ZPmZ_H umulh z0.h, p7/m, z0.h, z31.h
+# CHECK-NEXT: 1 4 1.00 4 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UMULH_ZPmZ_S umulh z0.s, p7/m, z0.s, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_B uqadd z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZZZ_B uqadd z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_D uqadd z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_D uqadd z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZZZ_D uqadd z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_H uqadd z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_H uqadd z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZZZ_H uqadd z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_S uqadd z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_S uqadd z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZZZ_S uqadd z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_B uqadd z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_D uqadd z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_H uqadd z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQADD_ZI_S uqadd z31.s, z31.s, #65280
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_WPiI uqdecb w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_WPiI uqdecb w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_WPiI uqdecb w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_WPiI uqdecb w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_XPiI uqdecb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_XPiI uqdecb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_XPiI uqdecb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_XPiI uqdecb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECB_XPiI uqdecb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_WPiI uqdecd w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_WPiI uqdecd w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_WPiI uqdecd w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_WPiI uqdecd w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_XPiI uqdecd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_XPiI uqdecd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_XPiI uqdecd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_XPiI uqdecd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECD_XPiI uqdecd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECD_ZPiI uqdecd z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECD_ZPiI uqdecd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECD_ZPiI uqdecd z0.d, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECD_ZPiI uqdecd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_WPiI uqdech w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_WPiI uqdech w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_WPiI uqdech w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_WPiI uqdech w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_XPiI uqdech x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_XPiI uqdech x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_XPiI uqdech x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_XPiI uqdech x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECH_XPiI uqdech x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECH_ZPiI uqdech z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECH_ZPiI uqdech z0.h, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECH_ZPiI uqdech z0.h, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECH_ZPiI uqdech z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_WP_B uqdecp wzr, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_WP_D uqdecp wzr, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_WP_H uqdecp wzr, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_WP_S uqdecp wzr, p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_XP_B uqdecp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_XP_D uqdecp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_XP_H uqdecp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECP_XP_S uqdecp x0, p0.s
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQDECP_ZP_D uqdecp z0.d, p0.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQDECP_ZP_H uqdecp z0.h, p0.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQDECP_ZP_S uqdecp z0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_WPiI uqdecw w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_WPiI uqdecw w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_WPiI uqdecw w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_WPiI uqdecw w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_XPiI uqdecw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_XPiI uqdecw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_XPiI uqdecw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_XPiI uqdecw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQDECW_XPiI uqdecw x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECW_ZPiI uqdecw z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECW_ZPiI uqdecw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECW_ZPiI uqdecw z0.s, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQDECW_ZPiI uqdecw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_WPiI uqincb w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_WPiI uqincb w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_WPiI uqincb w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_WPiI uqincb w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_XPiI uqincb x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_XPiI uqincb x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_XPiI uqincb x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_XPiI uqincb x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCB_XPiI uqincb x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_WPiI uqincd w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_WPiI uqincd w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_WPiI uqincd w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_WPiI uqincd w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_XPiI uqincd x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_XPiI uqincd x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_XPiI uqincd x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_XPiI uqincd x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCD_XPiI uqincd x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCD_ZPiI uqincd z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCD_ZPiI uqincd z0.d, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCD_ZPiI uqincd z0.d, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCD_ZPiI uqincd z0.d, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_WPiI uqinch w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_WPiI uqinch w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_WPiI uqinch w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_WPiI uqinch w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_XPiI uqinch x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_XPiI uqinch x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_XPiI uqinch x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_XPiI uqinch x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCH_XPiI uqinch x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCH_ZPiI uqinch z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCH_ZPiI uqinch z0.h, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCH_ZPiI uqinch z0.h, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCH_ZPiI uqinch z0.h, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_WP_B uqincp wzr, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_WP_D uqincp wzr, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_WP_H uqincp wzr, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_WP_S uqincp wzr, p15.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_XP_B uqincp x0, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_XP_D uqincp x0, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_XP_H uqincp x0, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCP_XP_S uqincp x0, p0.s
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQINCP_ZP_D uqincp z0.d, p0.d
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQINCP_ZP_H uqincp z0.h, p0.h
+# CHECK-NEXT: 3 7 2.00 7 V1UnitI[2],V1UnitM[2],V1UnitM0[2],V1UnitV,V1UnitV01 UQINCP_ZP_S uqincp z0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_WPiI uqincw w0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_WPiI uqincw w0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_WPiI uqincw w0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_WPiI uqincw w0, pow2, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_XPiI uqincw x0
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_XPiI uqincw x0, #14
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_XPiI uqincw x0, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_XPiI uqincw x0, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UQINCW_XPiI uqincw x0, vl1
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCW_ZPiI uqincw z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCW_ZPiI uqincw z0.s, all, mul #16
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCW_ZPiI uqincw z0.s, pow2
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV0,V1UnitV01,V1UnitV02 UQINCW_ZPiI uqincw z0.s, pow2, mul #16
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_B uqsub z0.b, z0.b, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZZZ_B uqsub z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_D uqsub z0.d, z0.d, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_D uqsub z0.d, z0.d, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZZZ_D uqsub z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_H uqsub z0.h, z0.h, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_H uqsub z0.h, z0.h, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZZZ_H uqsub z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_S uqsub z0.s, z0.s, #0
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_S uqsub z0.s, z0.s, #0, lsl #8
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZZZ_S uqsub z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_B uqsub z31.b, z31.b, #255
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_D uqsub z31.d, z31.d, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_H uqsub z31.h, z31.h, #65280
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UQSUB_ZI_S uqsub z31.s, z31.s, #65280
+# CHECK-NEXT: 1 3 0.25 1 V1UnitV USDOT_ZZZ usdot z0.s, z1.b, z31.b
+# CHECK-NEXT: 1 3 0.25 1 V1UnitV USDOT_ZZZI usdot z0.s, z1.b, z7.b[3]
+# CHECK-NEXT: 1 3 0.50 1 V1UnitV,V1UnitV01 USMMLA_ZZZ usmmla z0.s, z1.b, z2.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKHI_ZZ_D uunpkhi z31.d, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKHI_ZZ_H uunpkhi z31.h, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKHI_ZZ_S uunpkhi z31.s, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKLO_ZZ_D uunpklo z31.d, z31.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKLO_ZZ_H uunpklo z31.h, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UUNPKLO_ZZ_S uunpklo z31.s, z31.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_D uxtb z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_H uxtb z0.h, p0/m, z0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_S uxtb z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_D uxtb z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_H uxtb z31.h, p7/m, z31.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTB_ZPmZ_S uxtb z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTH_ZPmZ_D uxth z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTH_ZPmZ_S uxth z0.s, p0/m, z0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTH_ZPmZ_D uxth z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTH_ZPmZ_S uxth z31.s, p7/m, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTW_ZPmZ_D uxtw z0.d, p0/m, z0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitV,V1UnitV1,V1UnitV01,V1UnitV13 UXTW_ZPmZ_D uxtw z31.d, p7/m, z31.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP1_PPP_B uzp1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP1_PPP_D uzp1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP1_PPP_H uzp1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP1_PPP_S uzp1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP1_ZZZ_B uzp1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP1_ZZZ_D uzp1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP1_ZZZ_H uzp1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP1_ZZZ_S uzp1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP2_PPP_B uzp2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP2_PPP_D uzp2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP2_PPP_H uzp2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 UZP2_PPP_S uzp2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP2_ZZZ_B uzp2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP2_ZZZ_D uzp2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP2_ZZZ_H uzp2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 UZP2_ZZZ_S uzp2 z31.s, z31.s, z31.s
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELE_PWW_B whilele p0.b, w30, wzr
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELE_PXX_H whilele p6.h, x28, x30
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELO_PXX_D whilelo p15.d, xzr, x30
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELO_PXX_B whilelo p3.b, x9, x7
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELS_PWW_B whilels p4.b, w4, w20
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELS_PWW_H whilels p0.h, w30, wzr
+# CHECK-NEXT: 2 3 2.00 3 V1UnitI[2],V1UnitM[2],V1UnitM0[2] WHILELT_PXX_S whilelt p15.s, xzr, x30
+# CHECK-NEXT: 1 2 1.00 * U 2 V1UnitI,V1UnitM,V1UnitM0 WRFFR wrffr p0.b
+# CHECK-NEXT: 1 2 1.00 * U 2 V1UnitI,V1UnitM,V1UnitM0 WRFFR wrffr p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_B zip1 p0.b, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_D zip1 p0.d, p0.d, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_H zip1 p0.h, p0.h, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_S zip1 p0.s, p0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_B zip1 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_D zip1 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_H zip1 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP1_PPP_S zip1 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_B zip1 z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_D zip1 z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_H zip1 z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_S zip1 z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_B zip1 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_D zip1 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_H zip1 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP1_ZZZ_S zip1 z31.s, z31.s, z31.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_B zip2 p0.b, p0.b, p0.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_D zip2 p0.d, p0.d, p0.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_H zip2 p0.h, p0.h, p0.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_S zip2 p0.s, p0.s, p0.s
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_B zip2 p15.b, p15.b, p15.b
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_D zip2 p15.d, p15.d, p15.d
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_H zip2 p15.h, p15.h, p15.h
+# CHECK-NEXT: 1 2 1.00 2 V1UnitI,V1UnitM,V1UnitM0 ZIP2_PPP_S zip2 p15.s, p15.s, p15.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_B zip2 z0.b, z0.b, z0.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_D zip2 z0.d, z0.d, z0.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_H zip2 z0.h, z0.h, z0.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_S zip2 z0.s, z0.s, z0.s
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_B zip2 z31.b, z31.b, z31.b
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_D zip2 z31.d, z31.d, z31.d
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_H zip2 z31.h, z31.h, z31.h
+# CHECK-NEXT: 1 2 0.50 2 V1UnitV,V1UnitV01 ZIP2_ZZZ_S zip2 z31.s, z31.s, z31.s
# CHECK: Resources:
# CHECK-NEXT: [0.0] - V1UnitB
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
new file mode 100644
index 0000000000000..1e0e90c741c37
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/instruction-tables-tests.s
@@ -0,0 +1,415 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables < %s | FileCheck %s -check-prefixes=ALL,ISN
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISNB
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNBE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal < %s | FileCheck %s -check-prefixes=ALL,ISN
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISNB
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=normal -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISNBE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none < %s | FileCheck %s -check-prefixes=ALL
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-barriers < %s | FileCheck %s -check-prefixes=ALL,NISB
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-encoding < %s | FileCheck %s -check-prefixes=ALL,NISE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=none -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,NISBE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full < %s | FileCheck %s -check-prefixes=ALL,ISF
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-barriers < %s | FileCheck %s -check-prefixes=ALL,ISFB
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISFE
+# RUN: llvm-mca -march=riscv64 -mcpu=sifive-u74 -mattr=+v -instruction-tables=full -show-barriers -show-encoding < %s | FileCheck %s -check-prefixes=ALL,ISFBE
+
+ vsetvli a3, a2, e16, m1, tu, mu // Comment
+ vlm.v v4, (a1)
+
+# NISB: Iterations: 100
+# NISB-NEXT: Instructions: 200
+# NISB-NEXT: Total Cycles: 404
+# NISB-NEXT: Total uOps: 200
+
+# NISBE: Iterations: 100
+# NISBE-NEXT: Instructions: 200
+# NISBE-NEXT: Total Cycles: 404
+# NISBE-NEXT: Total uOps: 200
+
+# NISE: Iterations: 100
+# NISE-NEXT: Instructions: 200
+# NISE-NEXT: Total Cycles: 404
+# NISE-NEXT: Total uOps: 200
+
+# ISF: Resources:
+# ISF-NEXT: [0] - SiFive7FDiv:1
+# ISF-NEXT: [1] - SiFive7IDiv:1
+# ISF-NEXT: [2] - SiFive7PipeA:1
+# ISF-NEXT: [3] - SiFive7PipeAB:2 SiFive7PipeA, SiFive7PipeB
+# ISF-NEXT: [4] - SiFive7PipeB:1
+# ISF-NEXT: [5] - SiFive7VA:1
+# ISF-NEXT: [6] - SiFive7VCQ:1
+# ISF-NEXT: [7] - SiFive7VL:1
+# ISF-NEXT: [8] - SiFive7VS:1
+
+# ISFB: Resources:
+# ISFB-NEXT: [0] - SiFive7FDiv:1
+# ISFB-NEXT: [1] - SiFive7IDiv:1
+# ISFB-NEXT: [2] - SiFive7PipeA:1
+# ISFB-NEXT: [3] - SiFive7PipeAB:2 SiFive7PipeA, SiFive7PipeB
+# ISFB-NEXT: [4] - SiFive7PipeB:1
+# ISFB-NEXT: [5] - SiFive7VA:1
+# ISFB-NEXT: [6] - SiFive7VCQ:1
+# ISFB-NEXT: [7] - SiFive7VL:1
+# ISFB-NEXT: [8] - SiFive7VS:1
+
+# ISFBE: Resources:
+# ISFBE-NEXT: [0] - SiFive7FDiv:1
+# ISFBE-NEXT: [1] - SiFive7IDiv:1
+# ISFBE-NEXT: [2] - SiFive7PipeA:1
+# ISFBE-NEXT: [3] - SiFive7PipeAB:2 SiFive7PipeA, SiFive7PipeB
+# ISFBE-NEXT: [4] - SiFive7PipeB:1
+# ISFBE-NEXT: [5] - SiFive7VA:1
+# ISFBE-NEXT: [6] - SiFive7VCQ:1
+# ISFBE-NEXT: [7] - SiFive7VL:1
+# ISFBE-NEXT: [8] - SiFive7VS:1
+
+# ISFE: Resources:
+# ISFE-NEXT: [0] - SiFive7FDiv:1
+# ISFE-NEXT: [1] - SiFive7IDiv:1
+# ISFE-NEXT: [2] - SiFive7PipeA:1
+# ISFE-NEXT: [3] - SiFive7PipeAB:2 SiFive7PipeA, SiFive7PipeB
+# ISFE-NEXT: [4] - SiFive7PipeB:1
+# ISFE-NEXT: [5] - SiFive7VA:1
+# ISFE-NEXT: [6] - SiFive7VCQ:1
+# ISFE-NEXT: [7] - SiFive7VL:1
+# ISFE-NEXT: [8] - SiFive7VS:1
+
+# ISN: Instruction Info:
+# ISN-NEXT: [1]: #uOps
+# ISN-NEXT: [2]: Latency
+# ISN-NEXT: [3]: RThroughput
+# ISN-NEXT: [4]: MayLoad
+# ISN-NEXT: [5]: MayStore
+# ISN-NEXT: [6]: HasSideEffects (U)
+
+# ISNB: Instruction Info:
+# ISNB-NEXT: [1]: #uOps
+# ISNB-NEXT: [2]: Latency
+# ISNB-NEXT: [3]: RThroughput
+# ISNB-NEXT: [4]: MayLoad
+# ISNB-NEXT: [5]: MayStore
+# ISNB-NEXT: [6]: HasSideEffects (U)
+# ISNB-NEXT: [7]: LoadBarrier
+# ISNB-NEXT: [8]: StoreBarrier
+
+# ISNBE: Instruction Info:
+# ISNBE-NEXT: [1]: #uOps
+# ISNBE-NEXT: [2]: Latency
+# ISNBE-NEXT: [3]: RThroughput
+# ISNBE-NEXT: [4]: MayLoad
+# ISNBE-NEXT: [5]: MayStore
+# ISNBE-NEXT: [6]: HasSideEffects (U)
+# ISNBE-NEXT: [7]: LoadBarrier
+# ISNBE-NEXT: [8]: StoreBarrier
+# ISNBE-NEXT: [9]: Encoding Size
+
+# ISNE: Instruction Info:
+# ISNE-NEXT: [1]: #uOps
+# ISNE-NEXT: [2]: Latency
+# ISNE-NEXT: [3]: RThroughput
+# ISNE-NEXT: [4]: MayLoad
+# ISNE-NEXT: [5]: MayStore
+# ISNE-NEXT: [6]: HasSideEffects (U)
+# ISNE-NEXT: [7]: Encoding Size
+
+# NISB: Dispatch Width: 2
+# NISB-NEXT: uOps Per Cycle: 0.50
+# NISB-NEXT: IPC: 0.50
+# NISB-NEXT: Block RThroughput: 3.0
+
+# NISBE: Dispatch Width: 2
+# NISBE-NEXT: uOps Per Cycle: 0.50
+# NISBE-NEXT: IPC: 0.50
+# NISBE-NEXT: Block RThroughput: 3.0
+
+# NISE: Dispatch Width: 2
+# NISE-NEXT: uOps Per Cycle: 0.50
+# NISE-NEXT: IPC: 0.50
+# NISE-NEXT: Block RThroughput: 3.0
+
+# ISF: Instruction Info:
+# ISF-NEXT: [1]: #uOps
+# ISF-NEXT: [2]: Latency
+# ISF-NEXT: [3]: RThroughput
+# ISF-NEXT: [4]: MayLoad
+# ISF-NEXT: [5]: MayStore
+# ISF-NEXT: [6]: HasSideEffects (U)
+# ISF-NEXT: [7]: Bypass Latency
+# ISF-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# ISF-NEXT: [9]: LLVM Opcode Name
+
+# ISFB: Instruction Info:
+# ISFB-NEXT: [1]: #uOps
+# ISFB-NEXT: [2]: Latency
+# ISFB-NEXT: [3]: RThroughput
+# ISFB-NEXT: [4]: MayLoad
+# ISFB-NEXT: [5]: MayStore
+# ISFB-NEXT: [6]: HasSideEffects (U)
+# ISFB-NEXT: [7]: Bypass Latency
+# ISFB-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# ISFB-NEXT: [9]: LLVM Opcode Name
+# ISFB-NEXT: [10]: LoadBarrier
+# ISFB-NEXT: [11]: StoreBarrier
+
+# ISFBE: Instruction Info:
+# ISFBE-NEXT: [1]: #uOps
+# ISFBE-NEXT: [2]: Latency
+# ISFBE-NEXT: [3]: RThroughput
+# ISFBE-NEXT: [4]: MayLoad
+# ISFBE-NEXT: [5]: MayStore
+# ISFBE-NEXT: [6]: HasSideEffects (U)
+# ISFBE-NEXT: [7]: Bypass Latency
+# ISFBE-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# ISFBE-NEXT: [9]: LLVM Opcode Name
+# ISFBE-NEXT: [10]: LoadBarrier
+# ISFBE-NEXT: [11]: StoreBarrier
+# ISFBE-NEXT: [12]: Encoding Size
+
+# ISFE: Instruction Info:
+# ISFE-NEXT: [1]: #uOps
+# ISFE-NEXT: [2]: Latency
+# ISFE-NEXT: [3]: RThroughput
+# ISFE-NEXT: [4]: MayLoad
+# ISFE-NEXT: [5]: MayStore
+# ISFE-NEXT: [6]: HasSideEffects (U)
+# ISFE-NEXT: [7]: Bypass Latency
+# ISFE-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# ISFE-NEXT: [9]: LLVM Opcode Name
+# ISFE-NEXT: [10]: Encoding Size
+
+# ISN: [1] [2] [3] [4] [5] [6] Instructions:
+# ISN-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
+# ISN-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+
+# NISB: Instruction Info:
+# NISB-NEXT: [1]: #uOps
+# NISB-NEXT: [2]: Latency
+# NISB-NEXT: [3]: RThroughput
+# NISB-NEXT: [4]: MayLoad
+# NISB-NEXT: [5]: MayStore
+# NISB-NEXT: [6]: HasSideEffects (U)
+# NISB-NEXT: [7]: LoadBarrier
+# NISB-NEXT: [8]: StoreBarrier
+
+# NISBE: Instruction Info:
+# NISBE-NEXT: [1]: #uOps
+# NISBE-NEXT: [2]: Latency
+# NISBE-NEXT: [3]: RThroughput
+# NISBE-NEXT: [4]: MayLoad
+# NISBE-NEXT: [5]: MayStore
+# NISBE-NEXT: [6]: HasSideEffects (U)
+# NISBE-NEXT: [7]: LoadBarrier
+# NISBE-NEXT: [8]: StoreBarrier
+# NISBE-NEXT: [9]: Encoding Size
+
+# NISE: Instruction Info:
+# NISE-NEXT: [1]: #uOps
+# NISE-NEXT: [2]: Latency
+# NISE-NEXT: [3]: RThroughput
+# NISE-NEXT: [4]: MayLoad
+# NISE-NEXT: [5]: MayStore
+# NISE-NEXT: [6]: HasSideEffects (U)
+# NISE-NEXT: [7]: Encoding Size
+
+# ISF: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# ISF-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
+# ISF-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
+
+# ISFB: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# ISFB-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI vsetvli a3, a2, e16, m1, tu, mu // Comment
+# ISFB-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V vlm.v v4, (a1)
+
+# ISFBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Encodings: Instructions:
+# ISFBE-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
+# ISFBE-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
+
+# ISFE: [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] Encodings: Instructions:
+# ISFE-NEXT: 1 3 1.00 U 1 SiFive7PipeA,SiFive7PipeAB VSETVLI 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu // Comment
+# ISFE-NEXT: 1 4 3.00 * 4 SiFive7VCQ,SiFive7VL[1,3] VLM_V 4 07 82 b5 02 vlm.v v4, (a1)
+
+# ISNB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
+# ISNB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
+# ISNB-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+
+# ISNBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
+# ISNBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
+# ISNBE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+
+# ISNE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
+# ISNE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
+# ISNE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+
+# NISB: [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
+# NISB-NEXT: 1 3 1.00 U vsetvli a3, a2, e16, m1, tu, mu
+# NISB-NEXT: 1 4 3.00 * vlm.v v4, (a1)
+
+# NISBE: [1] [2] [3] [4] [5] [6] [7] [8] [9] Encodings: Instructions:
+# NISBE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
+# NISBE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+
+# NISE: [1] [2] [3] [4] [5] [6] [7] Encodings: Instructions:
+# NISE-NEXT: 1 3 1.00 U 4 d7 76 86 00 vsetvli a3, a2, e16, m1, tu, mu
+# NISE-NEXT: 1 4 3.00 * 4 07 82 b5 02 vlm.v v4, (a1)
+
+# ISN: Resources:
+# ISN-NEXT: [0] - SiFive7FDiv
+# ISN-NEXT: [1] - SiFive7IDiv
+# ISN-NEXT: [2] - SiFive7PipeA
+# ISN-NEXT: [3] - SiFive7PipeB
+# ISN-NEXT: [4] - SiFive7VA
+# ISN-NEXT: [5] - SiFive7VCQ
+# ISN-NEXT: [6] - SiFive7VL
+# ISN-NEXT: [7] - SiFive7VS
+
+# ISF: Resources:
+# ISF-NEXT: [0] - SiFive7FDiv
+# ISF-NEXT: [1] - SiFive7IDiv
+# ISF-NEXT: [2] - SiFive7PipeA
+# ISF-NEXT: [3] - SiFive7PipeB
+# ISF-NEXT: [4] - SiFive7VA
+# ISF-NEXT: [5] - SiFive7VCQ
+# ISF-NEXT: [6] - SiFive7VL
+# ISF-NEXT: [7] - SiFive7VS
+
+# ISFB: Resources:
+# ISFB-NEXT: [0] - SiFive7FDiv
+# ISFB-NEXT: [1] - SiFive7IDiv
+# ISFB-NEXT: [2] - SiFive7PipeA
+# ISFB-NEXT: [3] - SiFive7PipeB
+# ISFB-NEXT: [4] - SiFive7VA
+# ISFB-NEXT: [5] - SiFive7VCQ
+# ISFB-NEXT: [6] - SiFive7VL
+# ISFB-NEXT: [7] - SiFive7VS
+
+# ISFBE: Resources:
+# ISFBE-NEXT: [0] - SiFive7FDiv
+# ISFBE-NEXT: [1] - SiFive7IDiv
+# ISFBE-NEXT: [2] - SiFive7PipeA
+# ISFBE-NEXT: [3] - SiFive7PipeB
+# ISFBE-NEXT: [4] - SiFive7VA
+# ISFBE-NEXT: [5] - SiFive7VCQ
+# ISFBE-NEXT: [6] - SiFive7VL
+# ISFBE-NEXT: [7] - SiFive7VS
+
+# ISFE: Resources:
+# ISFE-NEXT: [0] - SiFive7FDiv
+# ISFE-NEXT: [1] - SiFive7IDiv
+# ISFE-NEXT: [2] - SiFive7PipeA
+# ISFE-NEXT: [3] - SiFive7PipeB
+# ISFE-NEXT: [4] - SiFive7VA
+# ISFE-NEXT: [5] - SiFive7VCQ
+# ISFE-NEXT: [6] - SiFive7VL
+# ISFE-NEXT: [7] - SiFive7VS
+
+# ISNB: Resources:
+# ISNB-NEXT: [0] - SiFive7FDiv
+# ISNB-NEXT: [1] - SiFive7IDiv
+# ISNB-NEXT: [2] - SiFive7PipeA
+# ISNB-NEXT: [3] - SiFive7PipeB
+# ISNB-NEXT: [4] - SiFive7VA
+# ISNB-NEXT: [5] - SiFive7VCQ
+# ISNB-NEXT: [6] - SiFive7VL
+# ISNB-NEXT: [7] - SiFive7VS
+
+# ISNBE: Resources:
+# ISNBE-NEXT: [0] - SiFive7FDiv
+# ISNBE-NEXT: [1] - SiFive7IDiv
+# ISNBE-NEXT: [2] - SiFive7PipeA
+# ISNBE-NEXT: [3] - SiFive7PipeB
+# ISNBE-NEXT: [4] - SiFive7VA
+# ISNBE-NEXT: [5] - SiFive7VCQ
+# ISNBE-NEXT: [6] - SiFive7VL
+# ISNBE-NEXT: [7] - SiFive7VS
+
+# ISNE: Resources:
+# ISNE-NEXT: [0] - SiFive7FDiv
+# ISNE-NEXT: [1] - SiFive7IDiv
+# ISNE-NEXT: [2] - SiFive7PipeA
+# ISNE-NEXT: [3] - SiFive7PipeB
+# ISNE-NEXT: [4] - SiFive7VA
+# ISNE-NEXT: [5] - SiFive7VCQ
+# ISNE-NEXT: [6] - SiFive7VL
+# ISNE-NEXT: [7] - SiFive7VS
+
+# NISB: Resources:
+# NISB-NEXT: [0] - SiFive7FDiv
+# NISB-NEXT: [1] - SiFive7IDiv
+# NISB-NEXT: [2] - SiFive7PipeA
+# NISB-NEXT: [3] - SiFive7PipeB
+# NISB-NEXT: [4] - SiFive7VA
+# NISB-NEXT: [5] - SiFive7VCQ
+# NISB-NEXT: [6] - SiFive7VL
+# NISB-NEXT: [7] - SiFive7VS
+
+# NISBE: Resources:
+# NISBE-NEXT: [0] - SiFive7FDiv
+# NISBE-NEXT: [1] - SiFive7IDiv
+# NISBE-NEXT: [2] - SiFive7PipeA
+# NISBE-NEXT: [3] - SiFive7PipeB
+# NISBE-NEXT: [4] - SiFive7VA
+# NISBE-NEXT: [5] - SiFive7VCQ
+# NISBE-NEXT: [6] - SiFive7VL
+# NISBE-NEXT: [7] - SiFive7VS
+
+# NISE: Resources:
+# NISE-NEXT: [0] - SiFive7FDiv
+# NISE-NEXT: [1] - SiFive7IDiv
+# NISE-NEXT: [2] - SiFive7PipeA
+# NISE-NEXT: [3] - SiFive7PipeB
+# NISE-NEXT: [4] - SiFive7VA
+# NISE-NEXT: [5] - SiFive7VCQ
+# NISE-NEXT: [6] - SiFive7VL
+# NISE-NEXT: [7] - SiFive7VS
+
+# ISN: Resource pressure per iteration:
+# ISN-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISN-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISF: Resource pressure per iteration:
+# ISF-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISF-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISFB: Resource pressure per iteration:
+# ISFB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISFB-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISFBE: Resource pressure per iteration:
+# ISFBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISFBE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISFE: Resource pressure per iteration:
+# ISFE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISFE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISNB: Resource pressure per iteration:
+# ISNB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISNB-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISNBE: Resource pressure per iteration:
+# ISNBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISNBE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ISNE: Resource pressure per iteration:
+# ISNE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# ISNE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# NISB: Resource pressure per iteration:
+# NISB-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# NISB-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# NISBE: Resource pressure per iteration:
+# NISBE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# NISBE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# NISE: Resource pressure per iteration:
+# NISE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# NISE-NEXT: - - 1.00 - - 1.00 3.00 -
+
+# ALL: Resource pressure by instruction:
+# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# ALL-NEXT: - - 1.00 - - - - - vsetvli a3, a2, e16, m1, tu, mu
+# ALL-NEXT: - - - - - 1.00 3.00 - vlm.v v4, (a1)
diff --git a/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp b/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
index fea0c9b8455c4..c708ab8647734 100644
--- a/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
+++ b/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp
@@ -12,15 +12,42 @@
//===----------------------------------------------------------------------===//
#include "Views/InstructionInfoView.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/JSON.h"
+#include "llvm/Support/WithColor.h"
namespace llvm {
namespace mca {
+void InstructionInfoView::getComment(raw_ostream &OS, const MCInst &MCI) const {
+ StringRef S = MCI.getLoc().getPointer();
+ size_t Pos = 0, PosCmt = 0;
+
+ // Recognized comments are after assembly instructions on the same line.
+ // It is usefull to add in comment scheduling information from architecture
+ // specification.
+ // '#' comment mark is not supported by llvm-mca
+
+ if (Pos = S.find("\n"); Pos != StringRef::npos) {
+ StringRef InstrStr = S.take_front(Pos);
+ // C style comment
+ if (((PosCmt = InstrStr.find("/*")) != StringRef::npos) &&
+ ((Pos = InstrStr.find("*/")) != StringRef::npos)) {
+ OS << InstrStr.substr(PosCmt, Pos);
+ return;
+ }
+ // C++ style comment
+ if ((PosCmt = InstrStr.find("//")) != StringRef::npos) {
+ OS << InstrStr.substr(PosCmt);
+ }
+ }
+}
+
void InstructionInfoView::printView(raw_ostream &OS) const {
std::string Buffer;
raw_string_ostream TempStream(Buffer);
+ formatted_raw_ostream FOS(TempStream);
ArrayRef<llvm::MCInst> Source = getSource();
if (!Source.size())
@@ -29,82 +56,132 @@ void InstructionInfoView::printView(raw_ostream &OS) const {
IIVDVec IIVD(Source.size());
collectData(IIVD);
- TempStream << "\n\nInstruction Info:\n";
- TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
- << "[4]: MayLoad\n[5]: MayStore\n[6]: HasSideEffects (U)\n";
+ if (PrintFullInfo) {
+ FOS << "\n\nResources:\n";
+ const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
+ for (unsigned I = 1, ResourceIndex = 0, E = SM.getNumProcResourceKinds();
+ I < E; ++I) {
+ const MCProcResourceDesc &ProcResource = *SM.getProcResource(I);
+ unsigned NumUnits = ProcResource.NumUnits;
+ // Skip invalid resources with zero units.
+ if (!NumUnits)
+ continue;
+
+ FOS << '[' << ResourceIndex << ']';
+ FOS.PadToColumn(6);
+ FOS << "- " << ProcResource.Name << ':' << NumUnits;
+ if (ProcResource.SubUnitsIdxBegin) {
+ FOS.PadToColumn(20);
+ for (unsigned U = 0; U < NumUnits; ++U) {
+ FOS << SM.getProcResource(ProcResource.SubUnitsIdxBegin[U])->Name;
+ if ((U + 1) < NumUnits)
+ FOS << ", ";
+ }
+ }
+ FOS << '\n';
+ ResourceIndex++;
+ }
+ }
+
+ SmallVector<unsigned, 16> Paddings = {0, 7, 14, 21, 28, 35, 42};
+ SmallVector<StringRef, 16> Fields = {"#uOps", "Latency",
+ "RThroughput", "MayLoad",
+ "MayStore", "HasSideEffects (U)"};
+ SmallVector<StringRef, 8> EndFields;
+ unsigned LastPadding = Paddings.back();
+ if (PrintFullInfo) {
+ Fields.push_back("Bypass Latency");
+ // Reserving 7 chars for
+ Paddings.push_back(LastPadding += 7);
+ Fields.push_back("Resources (<Name> | <Name>[<ReleaseAtCycle>] | "
+ "<Name>[<AcquireAtCycle>,<ReleaseAtCycle])");
+ Paddings.push_back(LastPadding += 43);
+ Fields.push_back("LLVM Opcode Name");
+ Paddings.push_back(LastPadding += 27);
+ }
if (PrintBarriers) {
- TempStream << "[7]: LoadBarrier\n[8]: StoreBarrier\n";
+ Fields.push_back("LoadBarrier");
+ Paddings.push_back(LastPadding += 7);
+ Fields.push_back("StoreBarrier");
+ Paddings.push_back(LastPadding += 7);
}
if (PrintEncodings) {
- if (PrintBarriers) {
- TempStream << "[9]: Encoding Size\n";
- TempStream << "\n[1] [2] [3] [4] [5] [6] [7] [8] "
- << "[9] Encodings: Instructions:\n";
- } else {
- TempStream << "[7]: Encoding Size\n";
- TempStream << "\n[1] [2] [3] [4] [5] [6] [7] "
- << "Encodings: Instructions:\n";
- }
- } else {
- if (PrintBarriers) {
- TempStream << "\n[1] [2] [3] [4] [5] [6] [7] [8] "
- << "Instructions:\n";
- } else {
- TempStream << "\n[1] [2] [3] [4] [5] [6] "
- << "Instructions:\n";
- }
+ Fields.push_back("Encoding Size");
+ Paddings.push_back(LastPadding += 7);
+ EndFields.push_back("Encodings:");
+ Paddings.push_back(LastPadding += 30);
}
+ EndFields.push_back("Instructions:");
- for (const auto &[Index, IIVDEntry, Inst] : enumerate(IIVD, Source)) {
- TempStream << ' ' << IIVDEntry.NumMicroOpcodes << " ";
- if (IIVDEntry.NumMicroOpcodes < 10)
- TempStream << " ";
- else if (IIVDEntry.NumMicroOpcodes < 100)
- TempStream << ' ';
- TempStream << IIVDEntry.Latency << " ";
- if (IIVDEntry.Latency < 10)
- TempStream << " ";
- else if (IIVDEntry.Latency < 100)
- TempStream << ' ';
+ FOS << "\n\nInstruction Info:\n";
+ for (unsigned i = 0, N = Fields.size(); i < N; i++)
+ FOS << "[" << i + 1 << "]: " << Fields[i] << "\n";
+ FOS << "\n";
+
+ for (unsigned i = 0, N = Paddings.size(); i < N; i++) {
+ if (Paddings[i])
+ FOS.PadToColumn(Paddings[i]);
+ if (i < Fields.size())
+ FOS << "[" << i + 1 << "]";
+ else
+ FOS << EndFields[i - Fields.size()];
+ }
+ FOS << "\n";
+ for (const auto &[Index, IIVDEntry, Inst] : enumerate(IIVD, Source)) {
+ FOS.PadToColumn(Paddings[0] + 1);
+ FOS << IIVDEntry.NumMicroOpcodes;
+ FOS.PadToColumn(Paddings[1] + 1);
+ FOS << IIVDEntry.Latency;
+ FOS.PadToColumn(Paddings[2]);
if (IIVDEntry.RThroughput) {
double RT = *IIVDEntry.RThroughput;
- TempStream << format("%.2f", RT) << ' ';
- if (RT < 10.0)
- TempStream << " ";
- else if (RT < 100.0)
- TempStream << ' ';
+ FOS << format("%.2f", RT);
} else {
- TempStream << " - ";
+ FOS << " -";
+ }
+ FOS.PadToColumn(Paddings[3] + 1);
+ FOS << (IIVDEntry.mayLoad ? "*" : " ");
+ FOS.PadToColumn(Paddings[4] + 1);
+ FOS << (IIVDEntry.mayStore ? "*" : " ");
+ FOS.PadToColumn(Paddings[5] + 1);
+ FOS << (IIVDEntry.hasUnmodeledSideEffects ? "U" : " ");
+ unsigned LastPaddingIdx = 5;
+
+ if (PrintFullInfo) {
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
+ FOS << IIVDEntry.Bypass;
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
+ FOS << IIVDEntry.Resources;
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
+ FOS << IIVDEntry.OpcodeName;
}
- TempStream << (IIVDEntry.mayLoad ? " * " : " ");
- TempStream << (IIVDEntry.mayStore ? " * " : " ");
- TempStream << (IIVDEntry.hasUnmodeledSideEffects ? " U " : " ");
if (PrintBarriers) {
- TempStream << (LoweredInsts[Index]->isALoadBarrier() ? " * "
- : " ");
- TempStream << (LoweredInsts[Index]->isAStoreBarrier() ? " * "
- : " ");
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
+ FOS << (LoweredInsts[Index]->isALoadBarrier() ? "*" : " ");
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
+ FOS << (LoweredInsts[Index]->isAStoreBarrier() ? "*" : " ");
}
if (PrintEncodings) {
StringRef Encoding(CE.getEncoding(Index));
unsigned EncodingSize = Encoding.size();
- TempStream << " " << EncodingSize
- << (EncodingSize < 10 ? " " : " ");
- TempStream.flush();
- formatted_raw_ostream FOS(TempStream);
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1] + 1);
+ FOS << EncodingSize;
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
for (unsigned i = 0, e = Encoding.size(); i != e; ++i)
FOS << format("%02x ", (uint8_t)Encoding[i]);
- FOS.PadToColumn(30);
- FOS.flush();
}
-
- TempStream << printInstructionString(Inst) << '\n';
+ FOS.PadToColumn(Paddings[LastPaddingIdx += 1]);
+ FOS << printInstructionString(Inst);
+ if (PrintFullInfo) {
+ FOS << "\t";
+ getComment(FOS, Inst);
+ }
+ FOS << '\n';
}
- TempStream.flush();
OS << Buffer;
}
@@ -141,6 +218,37 @@ void InstructionInfoView::collectData(
IIVDEntry.mayLoad = MCDesc.mayLoad();
IIVDEntry.mayStore = MCDesc.mayStore();
IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
+
+ if (PrintFullInfo) {
+ // Get latency with bypass
+ IIVDEntry.Bypass =
+ IIVDEntry.Latency - MCSchedModel::getBypassDelayCycles(STI, SCDesc);
+ IIVDEntry.OpcodeName = MCII.getName(Inst.getOpcode());
+ raw_string_ostream TempStream(IIVDEntry.Resources);
+ const MCWriteProcResEntry *Index = STI.getWriteProcResBegin(&SCDesc);
+ const MCWriteProcResEntry *Last = STI.getWriteProcResEnd(&SCDesc);
+ ListSeparator LS(",");
+ for (; Index != Last; ++Index) {
+ if (!Index->ReleaseAtCycle)
+ continue;
+ const MCProcResourceDesc *MCProc =
+ SM.getProcResource(Index->ProcResourceIdx);
+ if (Index->ReleaseAtCycle > 1) {
+ // Output ReleaseAtCycle between [] if not 1 (default)
+ // This is to be able to evaluate throughput.
+ // See getReciprocalThroughput in MCSchedule.cpp
+ if (Index->AcquireAtCycle > 0)
+ TempStream << LS
+ << format("%s[%d,%d]", MCProc->Name,
+ Index->AcquireAtCycle, Index->ReleaseAtCycle);
+ else
+ TempStream << LS
+ << format("%s[%d]", MCProc->Name, Index->ReleaseAtCycle);
+ } else {
+ TempStream << LS << MCProc->Name;
+ }
+ }
+ }
}
}
diff --git a/llvm/tools/llvm-mca/Views/InstructionInfoView.h b/llvm/tools/llvm-mca/Views/InstructionInfoView.h
index 3befafda90a38..34c6fec46a6d5 100644
--- a/llvm/tools/llvm-mca/Views/InstructionInfoView.h
+++ b/llvm/tools/llvm-mca/Views/InstructionInfoView.h
@@ -56,6 +56,7 @@ class InstructionInfoView : public InstructionView {
CodeEmitter &CE;
bool PrintEncodings;
bool PrintBarriers;
+ bool PrintFullInfo;
using UniqueInst = std::unique_ptr<Instruction>;
ArrayRef<UniqueInst> LoweredInsts;
const InstrumentManager &IM;
@@ -65,28 +66,39 @@ class InstructionInfoView : public InstructionView {
struct InstructionInfoViewData {
unsigned NumMicroOpcodes = 0;
+ // Latency + ForwardingDelayCycles: negative ReadAdvance
unsigned Latency = 0;
+ // ReadAvance Bypasses cycles: Latency - ReadAdvance (positive value)
+ unsigned Bypass = 0;
std::optional<double> RThroughput = 0.0;
bool mayLoad = false;
bool mayStore = false;
bool hasUnmodeledSideEffects = false;
+ StringRef OpcodeName = "";
+ std::string Resources = "";
};
using IIVDVec = SmallVector<InstructionInfoViewData, 16>;
/// Place the data into the array of InstructionInfoViewData IIVD.
void collectData(MutableArrayRef<InstructionInfoViewData> IIVD) const;
+ /// Extract comment (//, /* */) from the source assembly placed just after
+ /// instruction.
+ void getComment(raw_ostream &OS, const llvm::MCInst &Inst) const;
+
public:
InstructionInfoView(const llvm::MCSubtargetInfo &ST,
const llvm::MCInstrInfo &II, CodeEmitter &C,
bool ShouldPrintEncodings, llvm::ArrayRef<llvm::MCInst> S,
llvm::MCInstPrinter &IP,
ArrayRef<UniqueInst> LoweredInsts,
- bool ShouldPrintBarriers, const InstrumentManager &IM,
+ bool ShouldPrintBarriers, bool ShouldPrintFullInfo,
+ const InstrumentManager &IM,
const InstToInstrumentsT &InstToInstruments)
: InstructionView(ST, IP, S), MCII(II), CE(C),
PrintEncodings(ShouldPrintEncodings),
- PrintBarriers(ShouldPrintBarriers), LoweredInsts(LoweredInsts), IM(IM),
+ PrintBarriers(ShouldPrintBarriers), PrintFullInfo(ShouldPrintFullInfo),
+ LoweredInsts(LoweredInsts), IM(IM),
InstToInstruments(InstToInstruments) {}
void printView(llvm::raw_ostream &OS) const override;
diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp
index cc5d4f5fa05de..e2eb21058c2d6 100644
--- a/llvm/tools/llvm-mca/llvm-mca.cpp
+++ b/llvm/tools/llvm-mca/llvm-mca.cpp
@@ -225,10 +225,29 @@ static cl::opt<unsigned> StoreQueueSize("squeue",
cl::desc("Size of the store queue"),
cl::cat(ToolOptions), cl::init(0));
-static cl::opt<bool>
- PrintInstructionTables("instruction-tables",
- cl::desc("Print instruction tables"),
- cl::cat(ToolOptions), cl::init(false));
+enum class InstructionTablesType { NONE, NORMAL, FULL };
+
+static cl::opt<enum InstructionTablesType> InstructionTablesOption(
+ "instruction-tables", cl::desc("Print instruction tables"),
+ cl::values(clEnumValN(InstructionTablesType::NONE, "none",
+ "Do not print instruction tables"),
+ clEnumValN(InstructionTablesType::NORMAL, "normal",
+ "Print instruction tables"),
+ clEnumValN(InstructionTablesType::NORMAL, "", ""),
+ clEnumValN(InstructionTablesType::FULL, "full",
+ "Print instruction tables with additional"
+ " information: bypass latency, LLVM opcode,"
+ " used resources")),
+ cl::cat(ToolOptions), cl::init(InstructionTablesType::NONE),
+ cl::ValueOptional);
+
+static bool shouldPrintInstructionTables(enum InstructionTablesType ITType) {
+ return InstructionTablesOption == ITType;
+}
+
+static bool shouldPrintInstructionTables() {
+ return !shouldPrintInstructionTables(InstructionTablesType::NONE);
+}
static cl::opt<bool> PrintInstructionInfoView(
"instruction-info",
@@ -662,9 +681,9 @@ int main(int argc, char **argv) {
NonEmptyRegions++;
mca::CircularSourceMgr S(LoweredSequence,
- PrintInstructionTables ? 1 : Iterations);
+ shouldPrintInstructionTables() ? 1 : Iterations);
- if (PrintInstructionTables) {
+ if (shouldPrintInstructionTables()) {
// Create a pipeline, stages, and a printer.
auto P = std::make_unique<mca::Pipeline>();
P->appendStage(std::make_unique<mca::EntryStage>(S));
@@ -680,10 +699,14 @@ int main(int argc, char **argv) {
if (PrintInstructionInfoView) {
Printer.addView(std::make_unique<mca::InstructionInfoView>(
*STI, *MCII, CE, ShowEncoding, Insts, *IP, LoweredSequence,
- ShowBarriers, *IM, InstToInstruments));
+ ShowBarriers,
+ shouldPrintInstructionTables(InstructionTablesType::FULL), *IM,
+ InstToInstruments));
}
- Printer.addView(
- std::make_unique<mca::ResourcePressureView>(*STI, *IP, Insts));
+
+ if (PrintResourcePressureView)
+ Printer.addView(
+ std::make_unique<mca::ResourcePressureView>(*STI, *IP, Insts));
if (!runPipeline(*P))
return 1;
@@ -757,7 +780,7 @@ int main(int argc, char **argv) {
if (PrintInstructionInfoView)
Printer.addView(std::make_unique<mca::InstructionInfoView>(
*STI, *MCII, CE, ShowEncoding, Insts, *IP, LoweredSequence,
- ShowBarriers, *IM, InstToInstruments));
+ ShowBarriers, /*ShouldPrintFullInfo=*/false, *IM, InstToInstruments));
// Fetch custom Views that are to be placed after the InstructionInfoView.
// Refer to the comment paired with the CB->getStartViews(*IP, Insts); line
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