[llvm] [MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs (PR #132704)

[Min-Yih Hsu via llvm-commits]

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@@ -0,0 +1,452 @@
+//==- MipsScheduleI6400.td - I6400 Scheduling Definitions --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+def MipsI6400Model : SchedMachineModel {
+  int IssueWidth = 2;         // 2x dispatched per cycle
+  int MicroOpBufferSize = 48; // min(48, 48, 64)
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mshockwave wrote:

> It should be out-of-order.

The description of this PR says "...MIPS i6400 and i6500, an in-order MIPS64R6 processor...". And I don't think the SMT feature of this core count as out-of-order in the context of LLVM scheduling model.

https://github.com/llvm/llvm-project/pull/132704