[llvm] [llvm-exegesis][AArch64] Disable pauth and ldgm as unsupported instructions (PR #132346)

[David Green via llvm-commits]

================
@@ -35,6 +35,14 @@ const ExegesisTarget *ExegesisTarget::lookup(Triple TT) {
   return nullptr;
 }
 
+static bool isPointerAuthOpcode(unsigned Opcode) {
+  return (Opcode >= 1648 && Opcode <= 1667); // AUT instruction class range
----------------
davemgreen wrote:

My understanding of it is that when the AUT instructions were originally added they purely modified the values of registers, corrupting the top bits which then cause the return to fault when the register is used. So on a machine like Grace I which does not have FEAT_FPAC they work OK. It seems to produce a file that looks like this, and produces a sensible looking latency result similar to the optimization guide:
```
       0:       f81f0ff4        str     x20, [sp, #-16]!                        
       4:       d280000d        mov     x13, #0x0                       // #0   
       8:       d2800014        mov     x20, #0x0                       // #0   
       c:       dac11a8d        autda   x13, x20                                
      10:       dac11a8d        autda   x13, x20                                
...
    9c44:       dac11a8d        autda   x13, x20               
    9c48:       dac11a8d        autda   x13, x20               
    9c4c:       f84107f4        ldr     x20, [sp], #16         
    9c50:       d65f03c0        ret                            
```

AUTIASP also works fine for me, as x30 (LR) is spilled and reloaded around the snippet.

FEAT_FPAC changes the instructions so that they fault immediately when the check fails. So a cpu with that feature (#132368 ;)) might then hit the segfault you are seeing.

So maybe we can check that the current CPU has FEAT_FPAC, and disable them only then?

https://github.com/llvm/llvm-project/pull/132346