[llvm] [SLP] Fix incorrect convert when interchangeable instruction is used. (PR #132887)

[Han-Kuan Chen via llvm-commits]

https://github.com/HanKuanChen created https://github.com/llvm/llvm-project/pull/132887

If the Converter has AltOp, that means I should be converted to AltOp
instead of MainOp (which is AltOp in BinOpSameOpcodeHelper).

>From bad293e3dd641e2b8e9c64141c860cf6df708fb9 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Mon, 24 Mar 2025 21:03:48 -0700
Subject: [PATCH 1/2] [SLP] Pre-commit test.

---
 .../X86/BinOpSameOpcodeHelper.ll              | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll

diff --git a/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll b/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
new file mode 100644
index 0000000000000..c90d7e7f332f3
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -passes=slp-vectorizer -S %s | FileCheck %s
+
+define void @test() {
+entry:
+  %0 = mul i64 0, 0
+  %1 = lshr i64 %0, 0
+  %2 = sub i64 0, 1
+  %3 = lshr i64 %2, 0
+  %umin120 = call i64 @llvm.umin.i64(i64 %1, i64 %3)
+  %4 = sub i64 0, 0
+  %5 = lshr i64 %4, 0
+  %umin122 = call i64 @llvm.umin.i64(i64 %umin120, i64 %5)
+  %6 = add i64 0, 1
+  %7 = lshr i64 %6, 0
+  %umin123 = call i64 @llvm.umin.i64(i64 %umin122, i64 %7)
+  %umin124 = call i64 @llvm.umin.i64(i64 %umin123, i64 0)
+  ret void
+}
+
+declare i64 @llvm.umin.i64(i64, i64)

>From 120fb178cb3aaf9b491c2edd277ff70b4d7cef62 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Mon, 24 Mar 2025 22:56:49 -0700
Subject: [PATCH 2/2] [SLP] Fix incorrect convert when interchangeable
 instruction is used.

If the Converter has AltOp, that means I should be converted to AltOp
instead of MainOp (which is AltOp in BinOpSameOpcodeHelper).
---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp   |  9 +++------
 .../SLPVectorizer/X86/BinOpSameOpcodeHelper.ll    | 15 +++++++++++++++
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 72e18be9fe71e..6d96aedc5ff9f 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -1094,12 +1094,9 @@ class BinOpSameOpcodeHelper {
   unsigned getAltOpcode() const {
     return hasAltOp() ? AltOp.getOpcode() : getMainOpcode();
   }
-  SmallVector<Value *> getMainOperand(Instruction *I) const {
+  SmallVector<Value *> getOperand(Instruction *I) const {
     return MainOp.getOperand(I);
   }
-  SmallVector<Value *> getAltOperand(Instruction *I) const {
-    return AltOp.getOperand(I);
-  }
 };
 
 bool isConvertible(Instruction *I, Instruction *MainOp, Instruction *AltOp) {
@@ -1126,8 +1123,8 @@ convertTo(Instruction *I, Instruction *MainOp, Instruction *AltOp) {
   assert(I->isBinaryOp() && "Cannot convert the instruction.");
   BinOpSameOpcodeHelper Converter(I);
   if (Converter.add(I) && Converter.add(MainOp) && !Converter.hasAltOp())
-    return std::make_pair(MainOp, Converter.getMainOperand(MainOp));
-  return std::make_pair(AltOp, Converter.getAltOperand(AltOp));
+    return std::make_pair(MainOp, Converter.getOperand(MainOp));
+  return std::make_pair(AltOp, Converter.getOperand(AltOp));
 }
 
 /// Main data required for vectorization of instructions.
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll b/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
index c90d7e7f332f3..6f27555aeb3f1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/BinOpSameOpcodeHelper.ll
@@ -2,6 +2,21 @@
 ; RUN: opt -mtriple=x86_64-unknown-linux-gnu -passes=slp-vectorizer -S %s | FileCheck %s
 
 define void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = lshr i64 0, 0
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 0, 1
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP1]], 0
+; CHECK-NEXT:    [[UMIN120:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP0]], i64 [[TMP2]])
+; CHECK-NEXT:    [[TMP3:%.*]] = sub i64 0, 0
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i64 [[TMP3]], 0
+; CHECK-NEXT:    [[UMIN122:%.*]] = call i64 @llvm.umin.i64(i64 [[UMIN120]], i64 [[TMP4]])
+; CHECK-NEXT:    [[TMP5:%.*]] = add i64 0, 1
+; CHECK-NEXT:    [[TMP6:%.*]] = lshr i64 [[TMP5]], 0
+; CHECK-NEXT:    [[UMIN123:%.*]] = call i64 @llvm.umin.i64(i64 [[UMIN122]], i64 [[TMP6]])
+; CHECK-NEXT:    [[UMIN124:%.*]] = call i64 @llvm.umin.i64(i64 [[UMIN123]], i64 0)
+; CHECK-NEXT:    ret void
+;
 entry:
   %0 = mul i64 0, 0
   %1 = lshr i64 %0, 0