[llvm] [LoongArch] Pre-commit tests for vector shift (PR #132702)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 24 18:06:38 PDT 2025
https://github.com/tangaac updated https://github.com/llvm/llvm-project/pull/132702
>From 3463f2fa7082b3af8c37ed1f6f570b814dc0b728 Mon Sep 17 00:00:00 2001
From: tangaac <tangyan01 at loongson.cn>
Date: Mon, 24 Mar 2025 17:36:30 +0800
Subject: [PATCH 1/2] Pre-commit tests for vector shift
---
.../LoongArch/lsx/vec-shuffle-bit-shift.ll | 274 ++++++++
.../LoongArch/lsx/vec-shuffle-byte-shift.ll | 645 ++++++++++++++++++
2 files changed, 919 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
new file mode 100644
index 0000000000000..147a4c549c236
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
@@ -0,0 +1,274 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_h_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_h_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_h_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_w_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 16, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 16, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_w_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 16, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 16, i32 13, i32 14, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_w_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_w_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 8, i32 3, i32 8, i32 5, i32 8, i32 7, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_w_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_w_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_w_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_w_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_d_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 0, i32 1, i32 2, i32 8, i32 4, i32 5, i32 6>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_d_16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI12_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI12_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_24(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI13_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI13_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <4 x i32> @shuffle_to_vslli_d_32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI14_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI14_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 poison>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_to_vsrli_d_32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI15_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI15_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_40(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_40:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI16_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI16_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_40(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_40:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI17_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI17_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vslli_d_48(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_48:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI18_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI18_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 8, i32 8, i32 8, i32 0, i32 8, i32 8, i32 8, i32 4>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_to_vsrli_d_48(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_48:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI19_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI19_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32><i32 3, i32 8, i32 8, i32 8, i32 7, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vslli_d_56(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vslli_d_56:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI20_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI20_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_to_vsrli_d_56(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_to_vsrli_d_56:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI21_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI21_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
\ No newline at end of file
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
new file mode 100644
index 0000000000000..a37dbb3267ab4
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
@@ -0,0 +1,645 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_2(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_4(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_5(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_6(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_7(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_9(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_10(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_11(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_11:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_12(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_13(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_13:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI12_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI12_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_14(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_14:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI13_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI13_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_left_shift_15(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_left_shift_15:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI14_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI14_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_2(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI15_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI15_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_4(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI16_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI16_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_6(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI17_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI17_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_8(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI18_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI18_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_10(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI19_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI19_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_12(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI20_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI20_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_left_shift_14(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_left_shift_14:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI21_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI21_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0>
+ ret <8 x i16> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_left_shift_4(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_left_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI22_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI22_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_left_shift_8(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_left_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI23_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI23_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 4, i32 0, i32 1>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_left_shift_12(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_left_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI24_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI24_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
+ ret <4 x i32> %shuffle
+}
+
+define <2 x i64> @shuffle_2i64_byte_left_shift_8(<2 x i64> %a) nounwind {
+; CHECK-LABEL: shuffle_2i64_byte_left_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vpackev.d $vr0, $vr1, $vr0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> <i32 2, i32 0>
+ ret <2 x i64> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI26_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI26_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_2(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI27_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI27_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI28_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI28_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_4(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI29_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI29_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_5(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI30_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI30_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_6(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI31_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI31_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_7(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI32_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI32_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI33_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI33_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_9(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI34_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI34_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_10(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI35_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI35_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_11(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_11:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI36_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI36_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_12(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI37_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI37_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_13(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_13:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI38_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI38_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_14(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_14:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI39_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI39_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @shuffle_16i8_byte_right_shift_15(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_byte_right_shift_15:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI40_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI40_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_2(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI41_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI41_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_4(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI42_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI42_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_6(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI43_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI43_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_8(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI44_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI44_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_10(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_10:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI45_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI45_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_12(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI46_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI46_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_8i16_byte_right_shift_14(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_byte_right_shift_14:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI47_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI47_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+ ret <8 x i16> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_right_shift_4(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_right_shift_4:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI48_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI48_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_right_shift_8(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_right_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI49_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI49_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @shuffle_4i32_byte_right_shift_12(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_byte_right_shift_12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI50_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI50_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 3, i32 4, i32 4, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <2 x i64> @shuffle_2i64_byte_right_shift_8(<2 x i64> %a) nounwind {
+; CHECK-LABEL: shuffle_2i64_byte_right_shift_8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI51_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI51_0)
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vshuf.d $vr1, $vr0, $vr2
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> <i32 1, i32 2>
+ ret <2 x i64> %shuffle
+}
\ No newline at end of file
>From dbeae50abd8dacf12b186688a96ddac51dd4b391 Mon Sep 17 00:00:00 2001
From: tangaac <tangyan01 at loongson.cn>
Date: Tue, 25 Mar 2025 08:54:00 +0800
Subject: [PATCH 2/2] update test
---
.../LoongArch/lsx/vec-shuffle-bit-shift.ll | 2 +-
.../LoongArch/lsx/vec-shuffle-byte-shift.ll | 418 +++++++++---------
2 files changed, 210 insertions(+), 210 deletions(-)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
index 147a4c549c236..b590103511847 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
@@ -271,4 +271,4 @@ define <16 x i8> @shuffle_to_vsrli_d_56(<16 x i8> %a) nounwind {
; CHECK-NEXT: ret
%shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32><i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
index a37dbb3267ab4..8156239f81963 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
@@ -1,645 +1,645 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
-define <16 x i8> @shuffle_16i8_byte_left_shift_1(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_1:
+define <16 x i8> @shuffle_16i8_vbsll_v_1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_1:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI0_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_2(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_2:
+define <16 x i8> @shuffle_16i8_vbsll_v_2(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_3(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_3:
+define <16 x i8> @shuffle_16i8_vbsll_v_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_3:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_4(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_4:
+define <16 x i8> @shuffle_16i8_vbsll_v_4(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI3_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_5(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_5:
+define <16 x i8> @shuffle_16i8_vbsll_v_5(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_5:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI4_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_6(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_6:
+define <16 x i8> @shuffle_16i8_vbsll_v_6(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_6:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_7(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_7:
+define <16 x i8> @shuffle_16i8_vbsll_v_7(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_7:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI6_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_8(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_8:
+define <16 x i8> @shuffle_16i8_vbsll_v_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_9(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_9:
+define <16 x i8> @shuffle_16i8_vbsll_v_9(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_9:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI8_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_10(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_10:
+define <16 x i8> @shuffle_16i8_vbsll_v_10(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_10:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI9_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_11(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_11:
+define <16 x i8> @shuffle_16i8_vbsll_v_11(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_11:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI10_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_12(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_12:
+define <16 x i8> @shuffle_16i8_vbsll_v_12(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_13(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_13:
+define <16 x i8> @shuffle_16i8_vbsll_v_13(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_13:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI12_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI12_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_14(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_14:
+define <16 x i8> @shuffle_16i8_vbsll_v_14(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_14:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI13_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI13_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_left_shift_15(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_left_shift_15:
+define <16 x i8> @shuffle_16i8_vbsll_v_15(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsll_v_15:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI14_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI14_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0>
ret <16 x i8> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_2(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_2:
+define <8 x i16> @shuffle_8i16_vbsll_v_2(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI15_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI15_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_4(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_4:
+define <8 x i16> @shuffle_8i16_vbsll_v_4(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI16_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI16_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_6(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_6:
+define <8 x i16> @shuffle_8i16_vbsll_v_6(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_6:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI17_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI17_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_8(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_8:
+define <8 x i16> @shuffle_8i16_vbsll_v_8(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI18_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI18_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_10(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_10:
+define <8 x i16> @shuffle_8i16_vbsll_v_10(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_10:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI19_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI19_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_12(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_12:
+define <8 x i16> @shuffle_8i16_vbsll_v_12(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI20_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI20_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0, i32 1>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_left_shift_14(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_left_shift_14:
+define <8 x i16> @shuffle_8i16_vbsll_v_14(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsll_v_14:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI21_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI21_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 0>
ret <8 x i16> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_left_shift_4(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_left_shift_4:
+define <4 x i32> @shuffle_4i32_vbsll_v_4(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsll_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI22_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI22_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
ret <4 x i32> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_left_shift_8(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_left_shift_8:
+define <4 x i32> @shuffle_4i32_vbsll_v_8(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsll_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI23_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI23_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 4, i32 0, i32 1>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 4, i32 0, i32 1>
ret <4 x i32> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_left_shift_12(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_left_shift_12:
+define <4 x i32> @shuffle_4i32_vbsll_v_12(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsll_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI24_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI24_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 4, i32 4, i32 0>
ret <4 x i32> %shuffle
}
-define <2 x i64> @shuffle_2i64_byte_left_shift_8(<2 x i64> %a) nounwind {
-; CHECK-LABEL: shuffle_2i64_byte_left_shift_8:
+define <2 x i64> @shuffle_2i64_vbsll_v_8(<2 x i64> %a) nounwind {
+; CHECK-LABEL: shuffle_2i64_vbsll_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vpackev.d $vr0, $vr1, $vr0
+; CHECK-NEXT: vpackev.d $vr0, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> <i32 2, i32 0>
+ %shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 2, i32 0>
ret <2 x i64> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_1(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_1:
+define <16 x i8> @shuffle_16i8_vbsrl_v_1(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_1:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI26_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI26_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_2(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_2:
+define <16 x i8> @shuffle_16i8_vbsrl_v_2(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI27_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI27_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_3(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_3:
+define <16 x i8> @shuffle_16i8_vbsrl_v_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_3:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI28_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI28_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_4(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_4:
+define <16 x i8> @shuffle_16i8_vbsrl_v_4(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI29_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI29_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_5(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_5:
+define <16 x i8> @shuffle_16i8_vbsrl_v_5(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_5:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI30_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI30_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_6(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_6:
+define <16 x i8> @shuffle_16i8_vbsrl_v_6(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_6:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI31_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI31_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_7(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_7:
+define <16 x i8> @shuffle_16i8_vbsrl_v_7(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_7:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI32_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI32_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_8(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_8:
+define <16 x i8> @shuffle_16i8_vbsrl_v_8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI33_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI33_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_9(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_9:
+define <16 x i8> @shuffle_16i8_vbsrl_v_9(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_9:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI34_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI34_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_10(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_10:
+define <16 x i8> @shuffle_16i8_vbsrl_v_10(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_10:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI35_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI35_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_11(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_11:
+define <16 x i8> @shuffle_16i8_vbsrl_v_11(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_11:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI36_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI36_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_12(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_12:
+define <16 x i8> @shuffle_16i8_vbsrl_v_12(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI37_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI37_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_13(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_13:
+define <16 x i8> @shuffle_16i8_vbsrl_v_13(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_13:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI38_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI38_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_14(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_14:
+define <16 x i8> @shuffle_16i8_vbsrl_v_14(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_14:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI39_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI39_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <16 x i8> @shuffle_16i8_byte_right_shift_15(<16 x i8> %a) nounwind {
-; CHECK-LABEL: shuffle_16i8_byte_right_shift_15:
+define <16 x i8> @shuffle_16i8_vbsrl_v_15(<16 x i8> %a) nounwind {
+; CHECK-LABEL: shuffle_16i8_vbsrl_v_15:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI40_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI40_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr2, $vr1
+; CHECK-NEXT: vshuf.b $vr0, $vr2, $vr0, $vr1
; CHECK-NEXT: ret
- %shuffle = shufflevector <16 x i8> zeroinitializer, <16 x i8> %a, <16 x i32> <i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> zeroinitializer, <16 x i32> <i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_2(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_2:
+define <8 x i16> @shuffle_8i16_vbsrl_v_2(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_2:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI41_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI41_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_4(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_4:
+define <8 x i16> @shuffle_8i16_vbsrl_v_4(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI42_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI42_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_6(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_6:
+define <8 x i16> @shuffle_8i16_vbsrl_v_6(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_6:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI43_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI43_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_8(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_8:
+define <8 x i16> @shuffle_8i16_vbsrl_v_8(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI44_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI44_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_10(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_10:
+define <8 x i16> @shuffle_8i16_vbsrl_v_10(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_10:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI45_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI45_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_12(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_12:
+define <8 x i16> @shuffle_8i16_vbsrl_v_12(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI46_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI46_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <8 x i16> @shuffle_8i16_byte_right_shift_14(<8 x i16> %a) nounwind {
-; CHECK-LABEL: shuffle_8i16_byte_right_shift_14:
+define <8 x i16> @shuffle_8i16_vbsrl_v_14(<8 x i16> %a) nounwind {
+; CHECK-LABEL: shuffle_8i16_vbsrl_v_14:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI47_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI47_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.h $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 7, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
ret <8 x i16> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_right_shift_4(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_right_shift_4:
+define <4 x i32> @shuffle_4i32_vbsrl_v_4(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsrl_v_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI48_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI48_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
ret <4 x i32> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_right_shift_8(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_right_shift_8:
+define <4 x i32> @shuffle_4i32_vbsrl_v_8(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsrl_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI49_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI49_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
ret <4 x i32> %shuffle
}
-define <4 x i32> @shuffle_4i32_byte_right_shift_12(<4 x i32> %a) nounwind {
-; CHECK-LABEL: shuffle_4i32_byte_right_shift_12:
+define <4 x i32> @shuffle_4i32_vbsrl_v_12(<4 x i32> %a) nounwind {
+; CHECK-LABEL: shuffle_4i32_vbsrl_v_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI50_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI50_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.w $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.w $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 3, i32 4, i32 4, i32 4>
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> <i32 3, i32 4, i32 4, i32 4>
ret <4 x i32> %shuffle
}
-define <2 x i64> @shuffle_2i64_byte_right_shift_8(<2 x i64> %a) nounwind {
-; CHECK-LABEL: shuffle_2i64_byte_right_shift_8:
+define <2 x i64> @shuffle_2i64_vbsrl_v_8(<2 x i64> %a) nounwind {
+; CHECK-LABEL: shuffle_2i64_vbsrl_v_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI51_0)
; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI51_0)
; CHECK-NEXT: vrepli.b $vr2, 0
-; CHECK-NEXT: vshuf.d $vr1, $vr0, $vr2
+; CHECK-NEXT: vshuf.d $vr1, $vr2, $vr0
; CHECK-NEXT: vori.b $vr0, $vr1, 0
; CHECK-NEXT: ret
- %shuffle = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> <i32 1, i32 2>
+ %shuffle = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2>
ret <2 x i64> %shuffle
-}
\ No newline at end of file
+}
More information about the llvm-commits
mailing list