[llvm] [ms] [llvm-ml] Allow PTR casting of registers to their own size (PR #132751)

[Saleem Abdulrasool via llvm-commits]

================
@@ -2577,14 +2584,37 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
   return false;
 }
 
+uint16_t RegSizeInBits(const MCRegisterInfo &MRI, MCRegister RegNo) {
+  if (X86MCRegisterClasses[X86::GR8RegClassID].contains(RegNo))
+    return 8;
+  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(RegNo))
+    return 16;
+  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(RegNo))
+    return 32;
+  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
+    return 64;
+  if (X86MCRegisterClasses[X86::RFP80RegClassID].contains(RegNo))
+    return 80;
+  if (X86MCRegisterClasses[X86::VR128RegClassID].contains(RegNo))
+    return 128;
+  if (X86MCRegisterClasses[X86::VR128XRegClassID].contains(RegNo))
+    return 128;
----------------
compnerd wrote:

Does it make sense to merge these two?

```suggestion
  if (X86MCRegisterClasses[X86::VR128RegClassID].contains(RegNo) || 
      X86MCRegisterClasses[X86::VR128XRegClassID].contains(RegNo))
    return 128;
```

https://github.com/llvm/llvm-project/pull/132751