[llvm] 06e2fd9 - [AArch64] Regenerate complex-int-to-fp.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 24 13:35:27 PDT 2025
Author: David Green
Date: 2025-03-24T20:35:22Z
New Revision: 06e2fd962af063d4c0abb854a7adf770178c8dbd
URL: https://github.com/llvm/llvm-project/commit/06e2fd962af063d4c0abb854a7adf770178c8dbd
DIFF: https://github.com/llvm/llvm-project/commit/06e2fd962af063d4c0abb854a7adf770178c8dbd.diff
LOG: [AArch64] Regenerate complex-int-to-fp.ll. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/complex-int-to-fp.ll b/llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
index 506e5e59a3529..ec504b4782547 100644
--- a/llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
+++ b/llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
@@ -1,9 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
-; CHECK: autogen_SD19655
-; CHECK: scvtf
-; CHECK: ret
define void @autogen_SD19655(ptr %addr, ptr %addrfloat) {
+; CHECK-LABEL: autogen_SD19655:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: scvtf.2d v0, v0
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: str d0, [x1]
+; CHECK-NEXT: ret
%T = load <2 x i64>, ptr %addr
%F = sitofp <2 x i64> %T to <2 x float>
store <2 x float> %F, ptr %addrfloat
@@ -12,38 +17,44 @@ define void @autogen_SD19655(ptr %addr, ptr %addrfloat) {
define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i32_to_v2f64:
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
-; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
-; CHECK-NEXT: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll.2d v0, v0, #0
+; CHECK-NEXT: scvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <2 x i32> %v to <2 x double>
ret <2 x double> %conv
}
define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
-; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
-; CHECK-NEXT: ret
+; CHECK-LABEL: test_unsigned_v2i32_to_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll.2d v0, v0, #0
+; CHECK-NEXT: ucvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <2 x i32> %v to <2 x double>
ret <2 x double> %conv
}
define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i16_to_v2f64:
-; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
-; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
-; CHECK: scvtf.2d v0, [[VAL64]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #16
+; CHECK-NEXT: sshr.2s v0, v0, #16
+; CHECK-NEXT: sshll.2d v0, v0, #0
+; CHECK-NEXT: scvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <2 x i16> %v to <2 x double>
ret <2 x double> %conv
}
define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
-; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
-; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
-; CHECK: ucvtf.2d v0, [[VAL64]]
+; CHECK-LABEL: test_unsigned_v2i16_to_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ushll.2d v0, v0, #0
+; CHECK-NEXT: ucvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <2 x i16> %v to <2 x double>
ret <2 x double> %conv
@@ -51,20 +62,24 @@ define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnon
define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i8_to_v2f64:
-; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
-; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
-; CHECK: scvtf.2d v0, [[VAL64]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: sshll.2d v0, v0, #0
+; CHECK-NEXT: scvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <2 x i8> %v to <2 x double>
ret <2 x double> %conv
}
define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
-; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
-; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
-; CHECK: ucvtf.2d v0, [[VAL64]]
+; CHECK-LABEL: test_unsigned_v2i8_to_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ushll.2d v0, v0, #0
+; CHECK-NEXT: ucvtf.2d v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <2 x i8> %v to <2 x double>
ret <2 x double> %conv
@@ -72,16 +87,20 @@ define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone
define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i64_to_v2f32:
-; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
-; CHECK: fcvtn v0.2s, [[VAL64]].2d
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf.2d v0, v0
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%conv = sitofp <2 x i64> %v to <2 x float>
ret <2 x float> %conv
}
define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i64_to_v2f32
-; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0
-; CHECK: fcvtn v0.2s, [[VAL64]].2d
+; CHECK-LABEL: test_unsigned_v2i64_to_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.2d v0, v0
+; CHECK-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%conv = uitofp <2 x i64> %v to <2 x float>
ret <2 x float> %conv
@@ -89,18 +108,22 @@ define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone
define <2 x float> @test_signed_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i16_to_v2f32:
-; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
-; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
-; CHECK: scvtf.2s v0, [[VAL32]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #16
+; CHECK-NEXT: sshr.2s v0, v0, #16
+; CHECK-NEXT: scvtf.2s v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <2 x i16> %v to <2 x float>
ret <2 x float> %conv
}
define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i16_to_v2f32
-; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
-; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ucvtf.2s v0, [[VAL32]]
+; CHECK-LABEL: test_unsigned_v2i16_to_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ucvtf.2s v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <2 x i16> %v to <2 x float>
ret <2 x float> %conv
@@ -108,18 +131,22 @@ define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone
define <2 x float> @test_signed_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v2i8_to_v2f32:
-; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
-; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
-; CHECK: scvtf.2s v0, [[VAL32]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: scvtf.2s v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <2 x i8> %v to <2 x float>
ret <2 x float> %conv
}
define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v2i8_to_v2f32
-; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
-; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ucvtf.2s v0, [[VAL32]]
+; CHECK-LABEL: test_unsigned_v2i8_to_v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d1, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v1
+; CHECK-NEXT: ucvtf.2s v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <2 x i8> %v to <2 x float>
ret <2 x float> %conv
@@ -127,17 +154,21 @@ define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v4i16_to_v4f32:
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
-; CHECK: scvtf.4s v0, [[VAL32]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: scvtf.4s v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <4 x i16> %v to <4 x float>
ret <4 x float> %conv
}
define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
-; CHECK: ucvtf.4s v0, [[VAL32]]
+; CHECK-LABEL: test_unsigned_v4i16_to_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: ucvtf.4s v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <4 x i16> %v to <4 x float>
ret <4 x float> %conv
@@ -145,19 +176,23 @@ define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone
define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
; CHECK-LABEL: test_signed_v4i8_to_v4f32:
-; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
-; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
-; CHECK: scvtf.4s v0, [[VAL32]]
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.4h v0, v0, #8
+; CHECK-NEXT: sshr.4h v0, v0, #8
+; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: scvtf.4s v0, v0
+; CHECK-NEXT: ret
%conv = sitofp <4 x i8> %v to <4 x float>
ret <4 x float> %conv
}
define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
-; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
-; CHECK: bic.4h v0, #255, lsl #8
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
-; CHECK: ucvtf.4s v0, [[VAL32]]
+; CHECK-LABEL: test_unsigned_v4i8_to_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: ucvtf.4s v0, v0
+; CHECK-NEXT: ret
%conv = uitofp <4 x i8> %v to <4 x float>
ret <4 x float> %conv
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