[llvm] 4fb9650 - [clang][docs] Release Note for RISC-V qci-(no)nest

[Sam Elliott via llvm-commits]

Author: Sam Elliott
Date: 2025-03-24T13:04:00-07:00
New Revision: 4fb9650b21fc038ca044ac1ca7fcd5be0b44194a

URL: https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a
DIFF: https://github.com/llvm/llvm-project/commit/4fb9650b21fc038ca044ac1ca7fcd5be0b44194a.diff

LOG: [clang][docs] Release Note for RISC-V qci-(no)nest

These were omitted from the original PR (#129957)

Added: 
    

Modified: 
    clang/docs/ReleaseNotes.rst
    llvm/docs/ReleaseNotes.md

Removed: 
    


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diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 40d6785bd2f85..f919b66dd0e41 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -425,6 +425,11 @@ RISC-V Support
 
 - Add support for `-mtune=generic-ooo` (a generic out-of-order model).
 
+- Adds support for `__attribute__((interrupt("qci-nest")))` and
+  `__attribute__((interrupt("qci-nonest")))`. These use instructions from
+  Qualcomm's `Xqciint` extension to save and restore some GPRs in interrupt
+  service routines.
+
 CUDA/HIP Language Changes
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 

diff  --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 1e39f761ecdad..774d86afb44fa 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -147,6 +147,9 @@ Changes to the RISC-V Backend
 * Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions)
   extension.
 * Adds experimental assembler support for Zvqdotq.
+* Adds Support for Qualcomm's `qci-nest` and `qci-nonest` interrupt types, which
+  use instructions from `Xqciint` to save and restore some GPRs during interrupt
+  handlers.
 
 Changes to the WebAssembly Backend
 ----------------------------------