[llvm] [RISCV] Add vector hasAndNot to enable optimizations (PR #132438)

[Craig Topper via llvm-commits]

topperc wrote:

> > Non blocking for this patch, but make sure you check the codegen for the fixed vector case too. We sometimes hit different lowering paths for fixed and scalable and I only see a scalable test changing here.
> 
> Thanks for pointing that out! Indeed there's a problem with fixed vectors here:
> 
> ```
> +define <8 x i8> @not_signbit_mask_v8i8(<8 x i8> %a, <8 x i8> %b) {
> +; CHECK-LABEL: not_signbit_mask_v8i8:
> +; CHECK:       # %bb.0:
> +; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
> +; CHECK-NEXT:    vmsgt.vi v0, v8, -1
> +; CHECK-NEXT:    vmv.v.i v8, 0
> +; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
> +; CHECK-NEXT:    ret
> +;
> +; CHECK-ZVKB-LABEL: not_signbit_mask_v8i8:
> +; CHECK-ZVKB:       # %bb.0:
> +; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
> +; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 7
> +; CHECK-ZVKB-NEXT:    vnot.v v8, v8
> +; CHECK-ZVKB-NEXT:    vand.vv v8, v8, v9
> +; CHECK-ZVKB-NEXT:    ret
> +  %cond = icmp sgt <8 x i8> %a, splat (i8 -1)
> +  %r = select <8 x i1> %cond, <8 x i8> %b, <8 x i8> zeroinitializer
> +  ret <8 x i8> %r
> +}
> ```
> 
> I'll debug it tomorrow.
> 
> I don't see any fixed vector tests for `vandn`. Is `vandn-sdnode.ll` the right file to add these in?

We usually put fixed vectors in tests starting with `fixed-vectors-`. I think and/or/xor are in ../llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll. Since vandn requires a different extension we can create fixed-vectors-vandn.ll

https://github.com/llvm/llvm-project/pull/132438