[llvm] Add RISC-V support information to readme (PR #132699)

[Min-Yih Hsu via llvm-commits]

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@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISCV
+  * Supported extensions: compressed, atomic, multiply-divide, initial vector instructions.
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mshockwave wrote:

could you use the formal extension names (e.g. C, A, M, ...)

https://github.com/llvm/llvm-project/pull/132699