[llvm] e56ba37 - [RISCV] Remove the mucounteren alternate name for CSR 0x320. (#132498)

[via llvm-commits]

Author: Craig Topper
Date: 2025-03-24T09:47:21-07:00
New Revision: e56ba37bfff37b0ffa88e811fbcb10a1dfe0f42e

URL: https://github.com/llvm/llvm-project/commit/e56ba37bfff37b0ffa88e811fbcb10a1dfe0f42e
DIFF: https://github.com/llvm/llvm-project/commit/e56ba37bfff37b0ffa88e811fbcb10a1dfe0f42e.diff

LOG: [RISCV] Remove the mucounteren alternate name for CSR 0x320. (#132498)

This is the old name for 0x320 from privilege spec 1.9. It has different
semantics than mcountinhibit that is at that address now.

It doesn't look like binutils supports this name anymore so I don't
think llvm should.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSystemOperands.td
    llvm/test/MC/RISCV/machine-csr-names.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 1d2849d2a7a62..23388c7575e86 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -301,8 +301,6 @@ foreach i = 3...31 in
 // Machine Counter Setup
 //===----------------------------------------------------------------------===//
 def : SysReg<"mcountinhibit", 0x320>;
-let isAltName = 1 in
-def : SysReg<"mucounteren", 0x320>;
 
 // mhpmevent3-mhpmevent31 at 0x323-0x33F.
 foreach i = 3...31 in

diff  --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
index 0d2ea25fac0bc..0a76636f060e6 100644
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -2036,20 +2036,6 @@ csrrs t1, mcountinhibit, zero
 # uimm12
 csrrs t2, 0x320, zero
 
-# mucounteren
-# name
-# CHECK-INST: csrrs t1, mcountinhibit, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x32]
-# CHECK-INST-ALIAS: csrr t1, mcountinhibit
-# uimm12
-# CHECK-INST: csrrs t2, mcountinhibit, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
-# CHECK-INST-ALIAS: csrr t2, mcountinhibit
-# name
-csrrs t1, mucounteren, zero
-# uimm12
-csrrs t2, 0x320, zero
-
 # mhpmevent3
 # name
 # CHECK-INST: csrrs t1, mhpmevent3, zero