[llvm] [RISCV] Add vector hasAndNot to enable optimizations (PR #132438)

[Craig Topper via llvm-commits]

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@@ -2580,9 +2580,9 @@ define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale
 ; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:
 ; CHECK-ZVKB:       # %bb.0:
 ; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-ZVKB-NEXT:    vmsgt.vi v0, v8, -1
-; CHECK-ZVKB-NEXT:    vmv.v.i v8, 0
-; CHECK-ZVKB-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVKB-NEXT:    vsra.vi v8, v8, 7
+; CHECK-ZVKB-NEXT:    vnot.v v8, v8
+; CHECK-ZVKB-NEXT:    vand.vv v8, v8, v9
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topperc wrote:

> @topperc Thanks. I added your latter change. It affects no other test. Or do you prefer it as a separate PR or to work on it yourself?

It can be part of this PR. I don't have test case without this PR.

I think type legalization sign extends immediates that are multiples of a byte. But this immediate was created at a different type and didn't get sign extended.

https://github.com/llvm/llvm-project/pull/132438