[llvm] [MC] Account for AcquireAtCycle in getReciprocalThroughput (PR #132653)

[Min-Yih Hsu via llvm-commits]

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@@ -96,19 +96,22 @@ int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
 double
 MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                       const MCSchedClassDesc &SCDesc) {
-  std::optional<double> Throughput;
+  std::optional<double> MinThroughput;
   const MCSchedModel &SM = STI.getSchedModel();
   const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
   const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
   for (; I != E; ++I) {
-    if (!I->ReleaseAtCycle)
+    if (!I->ReleaseAtCycle || I->ReleaseAtCycle == I->AcquireAtCycle)
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mshockwave wrote:

> does `I->ReleaseAtCycle == I->AcquireAtCycle` actually happen?

It's allowed: https://github.com/llvm/llvm-project/blob/70c325bf6a1d3d801957e8714178c833156a72e3/llvm/lib/CodeGen/MachineScheduler.cpp#L4647

And it indeed happens: https://github.com/llvm/llvm-project/blob/70c325bf6a1d3d801957e8714178c833156a72e3/llvm/lib/Target/AArch64/AArch64SchedA510.td#L507
(the second template argument is ReleaseAtCycle, with AcquireAtCycle left to be default value of 0)

It's not clear to me why they (CortexA510) want both ReleaseAtCycle and AcquireAtCycle to be zero. Maybe they want to exclude these instructions completely from MachineScheduler.

https://github.com/llvm/llvm-project/pull/132653