[llvm] [RISCV][VLOPT] Look through PHI instructions (PR #132236)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 24 06:10:27 PDT 2025
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/132236
>From 2513c597fe77945b6c4bbe6c0e570c8ca4458fa5 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 08:15:19 -0700
Subject: [PATCH 1/7] [RISCV][VLOPT] Look through PHI instructions
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 7 ++
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 84 ++++++++++++++++++++++
2 files changed, 91 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index c36a1e9adccb0..61f43e2e72b13 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1340,6 +1340,13 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
continue;
}
+ if (UserMI.isPHI()) {
+ LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
+ Worklist.insert(&PhiUse);
+ continue;
+ }
+
auto VLOp = getMinimumVLForUser(UserOp);
if (!VLOp)
return std::nullopt;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index d42feeca9dbcc..dfc4dd84c72b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -368,3 +368,87 @@ body: |
%y:vr = COPY %x
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
...
+---
+name: phi
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: phi
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
+ ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ bb.0:
+ %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ BNE $noreg, $noreg, %bb.2
+ bb.1:
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ bb.2:
+ %y:vr = PHI %w, %bb.0, %x, %bb.1
+ %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+...
+---
+name: phi_user_invalid_sew
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: phi_user_invalid_sew
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
+ ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
+ bb.0:
+ %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ BNE $noreg, $noreg, %bb.2
+ bb.1:
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ bb.2:
+ %y:vr = PHI %w, %bb.0, %x, %bb.1
+ %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
+...
+---
+name: phi_different_incoming_sew
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: phi_different_incoming_sew
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
+ ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ bb.0:
+ %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ BNE $noreg, $noreg, %bb.2
+ bb.1:
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
+ bb.2:
+ %y:vr = PHI %w, %bb.0, %x, %bb.1
+ %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+...
>From d6462da5dde7d38604bd5783e609ec8392eaf74c Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 08:21:12 -0700
Subject: [PATCH 2/7] fixup! clang-format
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 61f43e2e72b13..80ae0fd3d9304 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1342,8 +1342,8 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
if (UserMI.isPHI()) {
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
- Worklist.insert(&PhiUse);
+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
+ Worklist.insert(&PhiUse);
continue;
}
>From 25edefa62daa85bf08d4a01a187ae709b2b22b4e Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 08:41:58 -0700
Subject: [PATCH 3/7] fixup! handle phi loop
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 3 ++-
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 24 ++++++++++++++++++++++
patch.diff | 21 +++++++++++++++++++
3 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 patch.diff
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 80ae0fd3d9304..e3e5b4e3442da 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1323,6 +1323,7 @@ std::optional<MachineOperand>
RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
std::optional<MachineOperand> CommonVL;
SmallSetVector<MachineOperand *, 8> Worklist;
+ SmallPtrSet<const MachineInstr *, 4> PHISeen;
for (auto &UserOp : MRI->use_operands(MI.getOperand(0).getReg()))
Worklist.insert(&UserOp);
@@ -1340,7 +1341,7 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
continue;
}
- if (UserMI.isPHI()) {
+ if (UserMI.isPHI() && PHISeen.insert(&UserMI).second) {
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
Worklist.insert(&PhiUse);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index dfc4dd84c72b2..939f70811ebf7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -452,3 +452,27 @@ body: |
%y:vr = PHI %w, %bb.0, %x, %bb.1
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
...
+---
+name: phi_cycle
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: phi_cycle
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %y, %bb.1
+ ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: PseudoBR %bb.1
+ bb.0:
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ bb.1:
+ %y:vr = PHI %x, %bb.0, %y, %bb.1
+ %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ PseudoBR %bb.1
+...
+
diff --git a/patch.diff b/patch.diff
new file mode 100644
index 0000000000000..0f7b3299c155c
--- /dev/null
+++ b/patch.diff
@@ -0,0 +1,21 @@
+commit d6462da5dde7d38604bd5783e609ec8392eaf74c
+Author: Michael Maitland <michaeltmaitland at gmail.com>
+Date: Thu Mar 20 08:21:12 2025 -0700
+
+ fixup! clang-format
+
+diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+index 61f43e2e72b1..80ae0fd3d930 100644
+--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
++++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+@@ -1342,8 +1342,8 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
+
+ if (UserMI.isPHI()) {
+ LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
+- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
+- Worklist.insert(&PhiUse);
++ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
++ Worklist.insert(&PhiUse);
+ continue;
+ }
+
>From b1345f6699da55fdd909dc0b97490a2bfed702fa Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 10:42:13 -0700
Subject: [PATCH 4/7] fixup! improve phi cycle logic
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 +++++-
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 2 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index e3e5b4e3442da..7952d68665688 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1343,8 +1343,12 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
if (UserMI.isPHI() && PHISeen.insert(&UserMI).second) {
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg())) {
+ // If UserMI has a PHI cycle, don't analyze it.
+ if (PhiUse.getParent() == &UserMI)
+ continue;
Worklist.insert(&PhiUse);
+ }
continue;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 939f70811ebf7..c90621cdc5cc9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -460,7 +460,7 @@ body: |
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
>From b392433922183a2193f1c6318b05363491d4f09d Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 10:54:31 -0700
Subject: [PATCH 5/7] fixup! add another test
---
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 27 ++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index c90621cdc5cc9..6343afc6bac62 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -453,10 +453,10 @@ body: |
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
...
---
-name: phi_cycle
+name: phi_cycle_direct
tracksRegLiveness: true
body: |
- ; CHECK-LABEL: name: phi_cycle
+ ; CHECK-LABEL: name: phi_cycle_direct
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
@@ -475,4 +475,27 @@ body: |
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
PseudoBR %bb.1
...
+---
+name: phi_cycle_indirect
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: phi_cycle_indirect
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %z, %bb.1
+ ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ ; CHECK-NEXT: PseudoBR %bb.1
+ bb.0:
+ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+ bb.1:
+ %y:vr = PHI %x, %bb.0, %z, %bb.1
+ %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
+ PseudoBR %bb.1
+...
>From a268fedbe1e2054d8236d07f706bc0452515131b Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Thu, 20 Mar 2025 13:03:12 -0700
Subject: [PATCH 6/7] fixup! remove accidental file
---
patch.diff | 21 ---------------------
1 file changed, 21 deletions(-)
delete mode 100644 patch.diff
diff --git a/patch.diff b/patch.diff
deleted file mode 100644
index 0f7b3299c155c..0000000000000
--- a/patch.diff
+++ /dev/null
@@ -1,21 +0,0 @@
-commit d6462da5dde7d38604bd5783e609ec8392eaf74c
-Author: Michael Maitland <michaeltmaitland at gmail.com>
-Date: Thu Mar 20 08:21:12 2025 -0700
-
- fixup! clang-format
-
-diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
-index 61f43e2e72b1..80ae0fd3d930 100644
---- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
-+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
-@@ -1342,8 +1342,8 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
-
- if (UserMI.isPHI()) {
- LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
-- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
-- Worklist.insert(&PhiUse);
-+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
-+ Worklist.insert(&PhiUse);
- continue;
- }
-
>From c37a482a4f5d33f97ce32da2f33310398f1f16a1 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 24 Mar 2025 06:10:08 -0700
Subject: [PATCH 7/7] fixup! fix phi cycle logic
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 7952d68665688..9ed2ba274bc53 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1341,14 +1341,13 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
continue;
}
- if (UserMI.isPHI() && PHISeen.insert(&UserMI).second) {
+ if (UserMI.isPHI()) {
+ // Don't follow PHI cycles
+ if (!PHISeen.insert(&UserMI).second)
+ continue;
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg())) {
- // If UserMI has a PHI cycle, don't analyze it.
- if (PhiUse.getParent() == &UserMI)
- continue;
+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
Worklist.insert(&PhiUse);
- }
continue;
}
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