[llvm] [RISCV] Support VP_SPLAT mask operations (PR #132345)
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Mon Mar 24 00:10:52 PDT 2025
https://github.com/NexMing updated https://github.com/llvm/llvm-project/pull/132345
>From 259bc3e745ef78db571ac3e213cf3a4da521cf35 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Fri, 21 Mar 2025 14:00:58 +0800
Subject: [PATCH 1/2] [RISCV] Support VP_SPLAT mask operations
Support VP_SPLAT mask operations, convert it to select operation.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 23 +++-
llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll | 107 +++++++++++++++++++
2 files changed, 128 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 48d8fc23dc1bb..10f8824367ac3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -810,6 +810,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
+ setOperationAction(ISD::EXPERIMENTAL_VP_SPLAT, VT, Custom);
setOperationPromotedToType(
ISD::VECTOR_SPLICE, VT,
@@ -12773,8 +12774,26 @@ SDValue RISCVTargetLowering::lowerVPSplatExperimental(SDValue Op,
Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
}
- SDValue Result =
- lowerScalarSplat(SDValue(), Val, VL, ContainerVT, DL, DAG, Subtarget);
+ SDValue Result;
+ if (VT.getScalarType() == MVT::i1) {
+ if (auto *C = dyn_cast<ConstantSDNode>(Val)) {
+ Result = C->isZero()
+ ? DAG.getNode(RISCVISD::VMCLR_VL, DL, ContainerVT, VL)
+ : DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL);
+ } else {
+ MVT WidenVT = ContainerVT.changeVectorElementType(MVT::i8);
+ SDValue LHS =
+ DAG.getNode(RISCVISD::VMV_V_X_VL, DL, WidenVT, DAG.getUNDEF(WidenVT),
+ DAG.getZExtOrTrunc(Val, DL, Subtarget.getXLenVT()), VL);
+ SDValue RHS = DAG.getConstant(0, DL, WidenVT);
+ Result = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+ {LHS, RHS, DAG.getCondCode(ISD::SETNE),
+ DAG.getUNDEF(ContainerVT), Mask, VL});
+ }
+ } else {
+ Result =
+ lowerScalarSplat(SDValue(), Val, VL, ContainerVT, DL, DAG, Subtarget);
+ }
if (!VT.isFixedLengthVector())
return Result;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll
new file mode 100644
index 0000000000000..e970758a2610b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+
+define <vscale x 1 x i1> @vp_splat_nxv1i1_true_unmasked(i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv1i1_true_unmasked:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vmset.m v0
+; CHECK-NEXT: ret
+ %splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
+ ret <vscale x 1 x i1> %splat
+}
+
+define <vscale x 1 x i1> @vp_splat_nxv1i1_false_unmasked(i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv1i1_false_unmasked:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: ret
+ %splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
+ ret <vscale x 1 x i1> %splat
+}
+
+define <vscale x 1 x i1> @vp_splat_nxv1i1(i1 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv1i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: ret
+ %splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 %val, <vscale x 1 x i1> %m, i32 %evl)
+ ret <vscale x 1 x i1> %splat
+}
+
+define <vscale x 2 x i1> @vp_splat_nxv2i1(i1 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv2i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: ret
+ %splat = call <vscale x 2 x i1> @llvm.experimental.vp.splat.nxv2i1(i1 %val, <vscale x 2 x i1> %m, i32 %evl)
+ ret <vscale x 2 x i1> %splat
+}
+
+define <vscale x 4 x i1> @vp_splat_nxv4i1(i1 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv4i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: ret
+ %splat = call <vscale x 4 x i1> @llvm.experimental.vp.splat.nxv4i1(i1 %val, <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i1> %splat
+}
+
+define <vscale x 8 x i1> @vp_splat_nxv8i1(i1 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv8i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.x v8, a0
+; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: ret
+ %splat = call <vscale x 8 x i1> @llvm.experimental.vp.splat.nxv8i1(i1 %val, <vscale x 8 x i1> %m, i32 %evl)
+ ret <vscale x 8 x i1> %splat
+}
+
+define <vscale x 16 x i1> @vp_splat_nxv16i1(i1 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv16i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.x v10, a0
+; CHECK-NEXT: vmsne.vi v8, v10, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: ret
+ %splat = call <vscale x 16 x i1> @llvm.experimental.vp.splat.nxv16i1(i1 %val, <vscale x 16 x i1> %m, i32 %evl)
+ ret <vscale x 16 x i1> %splat
+}
+
+define <vscale x 32 x i1> @vp_splat_nxv32i1(i1 %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv32i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: vmsne.vi v8, v12, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: ret
+ %splat = call <vscale x 32 x i1> @llvm.experimental.vp.splat.nxv32i1(i1 %val, <vscale x 32 x i1> %m, i32 %evl)
+ ret <vscale x 32 x i1> %splat
+}
+
+define <vscale x 64 x i1> @vp_splat_nxv64i1(i1 %val, <vscale x 64 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vp_splat_nxv64i1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: vmv.v.x v16, a0
+; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: ret
+ %splat = call <vscale x 64 x i1> @llvm.experimental.vp.splat.nxv64i1(i1 %val, <vscale x 64 x i1> %m, i32 %evl)
+ ret <vscale x 64 x i1> %splat
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}
>From aa49f31731308aae67c8b0fe9c798fdc5f65b5f6 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Mon, 24 Mar 2025 15:09:57 +0800
Subject: [PATCH 2/2] [NFC] Simplify code
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 10f8824367ac3..c8e630c646259 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12777,9 +12777,9 @@ SDValue RISCVTargetLowering::lowerVPSplatExperimental(SDValue Op,
SDValue Result;
if (VT.getScalarType() == MVT::i1) {
if (auto *C = dyn_cast<ConstantSDNode>(Val)) {
- Result = C->isZero()
- ? DAG.getNode(RISCVISD::VMCLR_VL, DL, ContainerVT, VL)
- : DAG.getNode(RISCVISD::VMSET_VL, DL, ContainerVT, VL);
+ Result =
+ DAG.getNode(C->isZero() ? RISCVISD::VMCLR_VL : RISCVISD::VMSET_VL, DL,
+ ContainerVT, VL);
} else {
MVT WidenVT = ContainerVT.changeVectorElementType(MVT::i8);
SDValue LHS =
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