[llvm] AMDGPU: Move insertion into V2SCopies map (PR #130776)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 16 23:31:49 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/130776
>From f3ebefab50d3c6bfea89393ac52ea770a8be700c Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 11 Mar 2025 15:02:16 +0700
Subject: [PATCH] AMDGPU: Move insertion into V2SCopies map
Insert the start instruction directly into the map before the uses. This
prevents improperly re-visting sgpr->vgpr phi inputs multiple times which
would trigger a use after free.
I don't particularly trust the iteration scheme here. This is also
unnecessarily revisting transitive users of a phi or reg_sequence for every
input operand, but I will address that separately.
Fixes #130646. I also believe it fixes #130119, although that test fails
less consistently for me.
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 6 +-
.../AMDGPU/agpr-copy-no-free-registers.ll | 460 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 3794 ++++++++---------
llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll | 12 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 20 +-
.../test/CodeGen/AMDGPU/carryout-selection.ll | 1356 +++---
.../CodeGen/AMDGPU/cf-loop-on-constant.ll | 18 +-
llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll | 17 +-
llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll | 18 +-
.../CodeGen/AMDGPU/extract_vector_dynelt.ll | 384 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 356 +-
...-phi-regression-issue130646-issue130119.ll | 168 +
...sgpr-copies-phi-regression-issue130646.mir | 88 +
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 301 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 195 +-
llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll | 2 +-
llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll | 352 +-
llvm/test/CodeGen/AMDGPU/idiv-licm.ll | 627 ++-
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 71 +-
.../CodeGen/AMDGPU/insert-delay-alu-bug.ll | 108 +-
.../insert_waitcnt_for_precise_memory.ll | 235 +-
llvm/test/CodeGen/AMDGPU/llvm.mulo.ll | 48 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 858 ++--
llvm/test/CodeGen/AMDGPU/mad_64_32.ll | 11 +-
llvm/test/CodeGen/AMDGPU/multilevel-break.ll | 17 +-
.../CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 38 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 104 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 502 ++-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 174 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 133 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 54 +-
llvm/test/CodeGen/AMDGPU/sra.ll | 122 +-
llvm/test/CodeGen/AMDGPU/srem.ll | 2578 ++++++-----
llvm/test/CodeGen/AMDGPU/srem64.ll | 565 ++-
llvm/test/CodeGen/AMDGPU/udiv.ll | 413 +-
llvm/test/CodeGen/AMDGPU/udiv64.ll | 92 +-
llvm/test/CodeGen/AMDGPU/udivrem.ll | 454 +-
llvm/test/CodeGen/AMDGPU/urem64.ll | 332 +-
llvm/test/CodeGen/AMDGPU/wave32.ll | 472 +-
39 files changed, 7429 insertions(+), 8126 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 4342e7a369c13..ba75afc593577 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -691,6 +691,9 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
TII->get(AMDGPU::COPY), NewDst)
.addReg(MO.getReg());
MO.setReg(NewDst);
+
+ // FIXME: We are transitively revisiting users of this
+ // instruction for every input.
analyzeVGPRToSGPRCopy(NewCopy);
}
}
@@ -928,6 +931,8 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
V2SCopyInfo Info(getNextVGPRToSGPRCopyId(), MI,
TRI->getRegSizeInBits(*DstRC));
+ V2SCopies[Info.ID] = Info;
+
SmallVector<MachineInstr *, 8> AnalysisWorklist;
// Needed because the SSA is not a tree but a graph and may have
// forks and joins. We should not then go same way twice.
@@ -976,7 +981,6 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
AnalysisWorklist.push_back(U);
}
}
- V2SCopies[Info.ID] = Info;
}
// The main function that computes the VGPR to SGPR copy score
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
index a4eab62f501ce..0e3bd9d153ebf 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
@@ -512,317 +512,315 @@ define void @v32_asm_def_use(float %v0, float %v1) #4 {
define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg2, i64 %arg3, <2 x half> %arg4, <2 x half> %arg5) #3 {
; GFX908-LABEL: introduced_copy_to_sgpr:
; GFX908: ; %bb.0: ; %bb
-; GFX908-NEXT: global_load_ushort v16, v[0:1], off glc
+; GFX908-NEXT: global_load_ushort v0, v[0:1], off glc
; GFX908-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
-; GFX908-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
-; GFX908-NEXT: s_load_dword s7, s[8:9], 0x18
-; GFX908-NEXT: s_mov_b32 s6, 0
-; GFX908-NEXT: s_mov_b32 s9, s6
+; GFX908-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10
+; GFX908-NEXT: s_load_dword s5, s[8:9], 0x18
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX908-NEXT: s_sub_i32 s8, 0, s3
-; GFX908-NEXT: v_cvt_f32_f16_e32 v17, s7
-; GFX908-NEXT: v_mov_b32_e32 v19, 0
-; GFX908-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GFX908-NEXT: v_mov_b32_e32 v0, 0
+; GFX908-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX908-NEXT: s_sub_i32 s4, 0, s3
+; GFX908-NEXT: s_lshr_b32 s12, s5, 16
+; GFX908-NEXT: v_cvt_f32_f16_e32 v26, s5
+; GFX908-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX908-NEXT: v_cvt_f32_f16_e32 v27, s12
+; GFX908-NEXT: s_lshl_b64 s[8:9], s[10:11], 5
+; GFX908-NEXT: s_or_b32 s8, s8, 28
+; GFX908-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX908-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX908-NEXT: v_mov_b32_e32 v15, s9
+; GFX908-NEXT: s_lshl_b64 s[6:7], s[0:1], 5
+; GFX908-NEXT: v_mov_b32_e32 v14, s8
+; GFX908-NEXT: v_mul_lo_u32 v1, s4, v2
+; GFX908-NEXT: s_mov_b32 s4, 0
+; GFX908-NEXT: v_mul_hi_u32 v3, v2, v1
; GFX908-NEXT: v_mov_b32_e32 v1, 0
-; GFX908-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX908-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX908-NEXT: v_readfirstlane_b32 s10, v2
-; GFX908-NEXT: s_mul_i32 s8, s8, s10
-; GFX908-NEXT: s_mul_hi_u32 s8, s10, s8
-; GFX908-NEXT: s_add_i32 s10, s10, s8
-; GFX908-NEXT: s_mul_hi_u32 s8, s2, s10
-; GFX908-NEXT: s_mul_i32 s10, s8, s3
-; GFX908-NEXT: s_sub_i32 s2, s2, s10
-; GFX908-NEXT: s_add_i32 s11, s8, 1
-; GFX908-NEXT: s_sub_i32 s10, s2, s3
-; GFX908-NEXT: s_cmp_ge_u32 s2, s3
-; GFX908-NEXT: s_cselect_b32 s8, s11, s8
-; GFX908-NEXT: s_cselect_b32 s2, s10, s2
-; GFX908-NEXT: s_add_i32 s10, s8, 1
-; GFX908-NEXT: s_cmp_ge_u32 s2, s3
-; GFX908-NEXT: s_cselect_b32 s8, s10, s8
-; GFX908-NEXT: s_lshr_b32 s7, s7, 16
-; GFX908-NEXT: v_cvt_f32_f16_e32 v18, s7
-; GFX908-NEXT: s_lshl_b64 s[2:3], s[0:1], 5
-; GFX908-NEXT: s_lshl_b64 s[12:13], s[8:9], 5
-; GFX908-NEXT: s_lshl_b64 s[10:11], s[4:5], 5
-; GFX908-NEXT: s_or_b32 s10, s10, 28
+; GFX908-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX908-NEXT: v_mul_hi_u32 v4, s2, v2
+; GFX908-NEXT: v_mov_b32_e32 v2, s10
+; GFX908-NEXT: v_mov_b32_e32 v3, s11
+; GFX908-NEXT: v_mul_lo_u32 v5, v4, s3
+; GFX908-NEXT: v_add_u32_e32 v6, 1, v4
+; GFX908-NEXT: v_sub_u32_e32 v5, s2, v5
+; GFX908-NEXT: v_subrev_u32_e32 v7, s3, v5
+; GFX908-NEXT: v_cmp_le_u32_e32 vcc, s3, v5
+; GFX908-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX908-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX908-NEXT: v_add_u32_e32 v7, 1, v4
+; GFX908-NEXT: v_cmp_le_u32_e32 vcc, s3, v5
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_readfirstlane_b32 s7, v16
-; GFX908-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX908-NEXT: s_mul_i32 s1, s1, s7
-; GFX908-NEXT: s_mul_hi_u32 s9, s0, s7
-; GFX908-NEXT: s_mul_i32 s0, s0, s7
-; GFX908-NEXT: s_add_i32 s1, s9, s1
-; GFX908-NEXT: s_lshl_b64 s[14:15], s[0:1], 5
+; GFX908-NEXT: v_and_b32_e32 v28, 0xffff, v0
+; GFX908-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
+; GFX908-NEXT: v_mul_lo_u32 v8, s1, v28
+; GFX908-NEXT: v_mul_hi_u32 v9, s0, v28
+; GFX908-NEXT: v_lshlrev_b64 v[4:5], 5, v[0:1]
+; GFX908-NEXT: v_mul_lo_u32 v6, s0, v28
+; GFX908-NEXT: v_add_u32_e32 v7, v9, v8
+; GFX908-NEXT: v_accvgpr_write_b32 a0, v4
+; GFX908-NEXT: v_accvgpr_write_b32 a1, v5
+; GFX908-NEXT: v_lshlrev_b64 v[6:7], 5, v[6:7]
; GFX908-NEXT: s_branch .LBB3_2
-; GFX908-NEXT: .LBB3_1: ; %Flow20
+; GFX908-NEXT: .LBB3_1: ; %bb12
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: s_andn2_b64 vcc, exec, s[0:1]
-; GFX908-NEXT: s_cbranch_vccz .LBB3_12
+; GFX908-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0
+; GFX908-NEXT: v_accvgpr_read_b32 v5, a1
+; GFX908-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX908-NEXT: v_accvgpr_read_b32 v4, a0
+; GFX908-NEXT: v_add_co_u32_e32 v14, vcc, v14, v4
+; GFX908-NEXT: v_addc_co_u32_e32 v15, vcc, v15, v5, vcc
+; GFX908-NEXT: s_cbranch_execz .LBB3_12
; GFX908-NEXT: .LBB3_2: ; %bb9
; GFX908-NEXT: ; =>This Loop Header: Depth=1
; GFX908-NEXT: ; Child Loop BB3_5 Depth 2
-; GFX908-NEXT: s_mov_b64 s[16:17], -1
+; GFX908-NEXT: s_mov_b64 s[0:1], -1
; GFX908-NEXT: s_cbranch_scc0 .LBB3_10
; GFX908-NEXT: ; %bb.3: ; %bb14
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: global_load_dwordx2 v[2:3], v[0:1], off
-; GFX908-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], -1
-; GFX908-NEXT: s_mov_b32 s7, s6
-; GFX908-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
-; GFX908-NEXT: v_mov_b32_e32 v4, s6
-; GFX908-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v6
-; GFX908-NEXT: v_mov_b32_e32 v6, s6
-; GFX908-NEXT: v_mov_b32_e32 v9, s7
-; GFX908-NEXT: v_mov_b32_e32 v5, s7
-; GFX908-NEXT: v_mov_b32_e32 v7, s7
-; GFX908-NEXT: v_mov_b32_e32 v8, s6
-; GFX908-NEXT: v_cmp_lt_i64_e64 s[16:17], s[4:5], 0
-; GFX908-NEXT: v_mov_b32_e32 v11, v5
-; GFX908-NEXT: s_mov_b64 s[18:19], s[10:11]
-; GFX908-NEXT: v_mov_b32_e32 v10, v4
+; GFX908-NEXT: v_mov_b32_e32 v10, 0
+; GFX908-NEXT: v_mov_b32_e32 v11, 0
+; GFX908-NEXT: global_load_dwordx2 v[10:11], v[10:11], off
+; GFX908-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[2:3]
+; GFX908-NEXT: s_mov_b32 s5, s4
+; GFX908-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX908-NEXT: v_accvgpr_write_b32 a2, v14
+; GFX908-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[2:3]
+; GFX908-NEXT: v_accvgpr_write_b32 a3, v15
+; GFX908-NEXT: v_mov_b32_e32 v13, s5
+; GFX908-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v16
+; GFX908-NEXT: v_mov_b32_e32 v17, s5
+; GFX908-NEXT: v_mov_b32_e32 v12, s4
+; GFX908-NEXT: v_mov_b32_e32 v16, s4
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: v_readfirstlane_b32 s7, v2
-; GFX908-NEXT: v_readfirstlane_b32 s9, v3
-; GFX908-NEXT: s_add_u32 s7, s7, 1
-; GFX908-NEXT: s_addc_u32 s9, s9, 0
-; GFX908-NEXT: s_mul_hi_u32 s20, s2, s7
-; GFX908-NEXT: s_mul_i32 s9, s2, s9
-; GFX908-NEXT: s_mul_i32 s21, s3, s7
-; GFX908-NEXT: s_add_i32 s9, s20, s9
-; GFX908-NEXT: s_mul_i32 s7, s2, s7
-; GFX908-NEXT: s_add_i32 s9, s9, s21
+; GFX908-NEXT: v_add_co_u32_e32 v20, vcc, 1, v10
+; GFX908-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v11, vcc
+; GFX908-NEXT: v_mul_lo_u32 v21, s6, v18
+; GFX908-NEXT: v_mul_hi_u32 v22, s6, v20
+; GFX908-NEXT: v_mul_lo_u32 v23, s7, v20
+; GFX908-NEXT: v_mul_lo_u32 v29, s6, v20
+; GFX908-NEXT: v_mov_b32_e32 v19, s5
+; GFX908-NEXT: v_add_u32_e32 v20, v22, v21
+; GFX908-NEXT: v_add_u32_e32 v30, v20, v23
+; GFX908-NEXT: v_mov_b32_e32 v21, s5
+; GFX908-NEXT: v_mov_b32_e32 v18, s4
+; GFX908-NEXT: v_mov_b32_e32 v20, s4
; GFX908-NEXT: s_branch .LBB3_5
; GFX908-NEXT: .LBB3_4: ; %bb58
; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2
-; GFX908-NEXT: v_add_co_u32_sdwa v2, vcc, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX908-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX908-NEXT: s_add_u32 s18, s18, s14
-; GFX908-NEXT: v_cmp_lt_i64_e64 s[22:23], -1, v[2:3]
-; GFX908-NEXT: s_addc_u32 s19, s19, s15
-; GFX908-NEXT: s_mov_b64 s[20:21], 0
-; GFX908-NEXT: s_andn2_b64 vcc, exec, s[22:23]
+; GFX908-NEXT: v_add_co_u32_e32 v10, vcc, v10, v28
+; GFX908-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
+; GFX908-NEXT: v_add_co_u32_e32 v14, vcc, v14, v6
+; GFX908-NEXT: v_cmp_lt_i64_e64 s[10:11], -1, v[10:11]
+; GFX908-NEXT: v_addc_co_u32_e32 v15, vcc, v15, v7, vcc
+; GFX908-NEXT: s_mov_b64 s[8:9], 0
+; GFX908-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GFX908-NEXT: s_cbranch_vccz .LBB3_9
; GFX908-NEXT: .LBB3_5: ; %bb16
; GFX908-NEXT: ; Parent Loop BB3_2 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
-; GFX908-NEXT: s_add_u32 s20, s18, s7
-; GFX908-NEXT: s_addc_u32 s21, s19, s9
-; GFX908-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
+; GFX908-NEXT: v_add_co_u32_e32 v22, vcc, v14, v29
+; GFX908-NEXT: v_addc_co_u32_e32 v23, vcc, v15, v30, vcc
+; GFX908-NEXT: global_load_dword v32, v[22:23], off offset:-12 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
+; GFX908-NEXT: global_load_dword v31, v[22:23], off offset:-8 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_load_dword v12, v19, s[20:21] offset:-4 glc
+; GFX908-NEXT: global_load_dword v24, v[22:23], off offset:-4 glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: global_load_dword v12, v19, s[20:21] glc
+; GFX908-NEXT: global_load_dword v22, v[22:23], off glc
; GFX908-NEXT: s_waitcnt vmcnt(0)
-; GFX908-NEXT: ds_read_b64 v[12:13], v19
-; GFX908-NEXT: ds_read_b64 v[14:15], v0
+; GFX908-NEXT: ds_read_b64 v[22:23], v1
+; GFX908-NEXT: ds_read_b64 v[24:25], v0
; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1]
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_cbranch_vccnz .LBB3_7
; GFX908-NEXT: ; %bb.6: ; %bb51
; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2
-; GFX908-NEXT: v_cvt_f32_f16_sdwa v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX908-NEXT: v_cvt_f32_f16_e32 v21, v21
-; GFX908-NEXT: v_cvt_f32_f16_sdwa v23, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX908-NEXT: v_cvt_f32_f16_e32 v20, v20
-; GFX908-NEXT: v_add_f32_e32 v24, v17, v12
-; GFX908-NEXT: v_add_f32_e32 v25, v18, v13
-; GFX908-NEXT: v_add_f32_e32 v26, 0, v12
-; GFX908-NEXT: v_add_f32_e32 v27, 0, v13
-; GFX908-NEXT: v_add_f32_e32 v15, v22, v15
-; GFX908-NEXT: v_add_f32_e32 v14, v21, v14
-; GFX908-NEXT: v_add_f32_e32 v13, v23, v13
-; GFX908-NEXT: v_add_f32_e32 v12, v20, v12
-; GFX908-NEXT: v_add_f32_e32 v5, v5, v25
-; GFX908-NEXT: v_add_f32_e32 v4, v4, v24
-; GFX908-NEXT: v_add_f32_e32 v7, v7, v27
-; GFX908-NEXT: v_add_f32_e32 v6, v6, v26
-; GFX908-NEXT: v_add_f32_e32 v8, v8, v14
-; GFX908-NEXT: v_add_f32_e32 v9, v9, v15
-; GFX908-NEXT: v_add_f32_e32 v10, v10, v12
-; GFX908-NEXT: v_add_f32_e32 v11, v11, v13
+; GFX908-NEXT: v_cvt_f32_f16_sdwa v33, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX908-NEXT: v_cvt_f32_f16_e32 v32, v32
+; GFX908-NEXT: v_cvt_f32_f16_sdwa v34, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX908-NEXT: v_cvt_f32_f16_e32 v31, v31
+; GFX908-NEXT: v_add_f32_e32 v4, v26, v22
+; GFX908-NEXT: v_add_f32_e32 v5, v27, v23
+; GFX908-NEXT: v_add_f32_e32 v8, 0, v22
+; GFX908-NEXT: v_add_f32_e32 v9, 0, v23
+; GFX908-NEXT: v_add_f32_e32 v25, v33, v25
+; GFX908-NEXT: v_add_f32_e32 v24, v32, v24
+; GFX908-NEXT: v_add_f32_e32 v23, v34, v23
+; GFX908-NEXT: v_add_f32_e32 v22, v31, v22
+; GFX908-NEXT: v_add_f32_e32 v13, v13, v5
+; GFX908-NEXT: v_add_f32_e32 v12, v12, v4
+; GFX908-NEXT: v_add_f32_e32 v17, v17, v9
+; GFX908-NEXT: v_add_f32_e32 v16, v16, v8
+; GFX908-NEXT: v_add_f32_e32 v18, v18, v24
+; GFX908-NEXT: v_add_f32_e32 v19, v19, v25
+; GFX908-NEXT: v_add_f32_e32 v20, v20, v22
+; GFX908-NEXT: v_add_f32_e32 v21, v21, v23
; GFX908-NEXT: s_branch .LBB3_4
; GFX908-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2
-; GFX908-NEXT: s_mov_b64 s[20:21], s[16:17]
-; GFX908-NEXT: s_andn2_b64 vcc, exec, s[20:21]
+; GFX908-NEXT: s_mov_b64 s[8:9], s[2:3]
+; GFX908-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GFX908-NEXT: s_cbranch_vccz .LBB3_4
; GFX908-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: s_mov_b64 s[20:21], -1
-; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
-; GFX908-NEXT: ; implicit-def: $sgpr18_sgpr19
+; GFX908-NEXT: s_mov_b64 s[8:9], -1
+; GFX908-NEXT: ; implicit-def: $vgpr10_vgpr11
+; GFX908-NEXT: ; implicit-def: $vgpr14_vgpr15
; GFX908-NEXT: .LBB3_9: ; %loop.exit.guard
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: s_xor_b64 s[16:17], s[20:21], -1
+; GFX908-NEXT: v_accvgpr_read_b32 v15, a3
+; GFX908-NEXT: s_xor_b64 s[0:1], s[8:9], -1
+; GFX908-NEXT: v_accvgpr_read_b32 v14, a2
; GFX908-NEXT: .LBB3_10: ; %Flow19
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: s_mov_b64 s[0:1], -1
-; GFX908-NEXT: s_and_b64 vcc, exec, s[16:17]
-; GFX908-NEXT: s_cbranch_vccz .LBB3_1
-; GFX908-NEXT: ; %bb.11: ; %bb12
-; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX908-NEXT: s_add_u32 s4, s4, s8
-; GFX908-NEXT: s_addc_u32 s5, s5, 0
-; GFX908-NEXT: s_add_u32 s10, s10, s12
-; GFX908-NEXT: s_addc_u32 s11, s11, s13
-; GFX908-NEXT: s_mov_b64 s[0:1], 0
-; GFX908-NEXT: s_branch .LBB3_1
+; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1]
+; GFX908-NEXT: s_cbranch_vccnz .LBB3_1
+; GFX908-NEXT: ; %bb.11:
+; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX908-NEXT: ; implicit-def: $vgpr14_vgpr15
; GFX908-NEXT: .LBB3_12: ; %DummyReturnBlock
; GFX908-NEXT: s_endpgm
;
; GFX90A-LABEL: introduced_copy_to_sgpr:
; GFX90A: ; %bb.0: ; %bb
-; GFX90A-NEXT: global_load_ushort v18, v[0:1], off glc
+; GFX90A-NEXT: global_load_ushort v10, v[0:1], off glc
; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
-; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
-; GFX90A-NEXT: s_load_dword s7, s[8:9], 0x18
-; GFX90A-NEXT: s_mov_b32 s6, 0
-; GFX90A-NEXT: s_mov_b32 s9, s6
+; GFX90A-NEXT: s_load_dword s5, s[8:9], 0x18
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x10
+; GFX90A-NEXT: s_mov_b32 s4, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX90A-NEXT: s_sub_i32 s8, 0, s3
-; GFX90A-NEXT: v_mov_b32_e32 v19, 0
-; GFX90A-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GFX90A-NEXT: v_pk_mov_b32 v[0:1], 0, 0
-; GFX90A-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX90A-NEXT: v_cvt_u32_f32_e32 v3, v2
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v2, s7
-; GFX90A-NEXT: v_readfirstlane_b32 s10, v3
-; GFX90A-NEXT: s_mul_i32 s8, s8, s10
-; GFX90A-NEXT: s_mul_hi_u32 s8, s10, s8
-; GFX90A-NEXT: s_add_i32 s10, s10, s8
-; GFX90A-NEXT: s_mul_hi_u32 s8, s2, s10
-; GFX90A-NEXT: s_mul_i32 s10, s8, s3
-; GFX90A-NEXT: s_sub_i32 s2, s2, s10
-; GFX90A-NEXT: s_add_i32 s11, s8, 1
-; GFX90A-NEXT: s_sub_i32 s10, s2, s3
-; GFX90A-NEXT: s_cmp_ge_u32 s2, s3
-; GFX90A-NEXT: s_cselect_b32 s8, s11, s8
-; GFX90A-NEXT: s_cselect_b32 s2, s10, s2
-; GFX90A-NEXT: s_add_i32 s10, s8, 1
-; GFX90A-NEXT: s_cmp_ge_u32 s2, s3
-; GFX90A-NEXT: s_cselect_b32 s8, s10, s8
-; GFX90A-NEXT: s_lshr_b32 s7, s7, 16
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v3, s7
-; GFX90A-NEXT: s_lshl_b64 s[2:3], s[0:1], 5
-; GFX90A-NEXT: s_lshl_b64 s[12:13], s[8:9], 5
-; GFX90A-NEXT: s_lshl_b64 s[10:11], s[4:5], 5
+; GFX90A-NEXT: s_sub_i32 s12, 0, s3
+; GFX90A-NEXT: s_lshr_b32 s13, s5, 16
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v2, s5
+; GFX90A-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v3, s13
+; GFX90A-NEXT: s_lshl_b64 s[10:11], s[8:9], 5
; GFX90A-NEXT: s_or_b32 s10, s10, 28
+; GFX90A-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX90A-NEXT: s_lshl_b64 s[6:7], s[0:1], 5
+; GFX90A-NEXT: v_pk_mov_b32 v[4:5], s[8:9], s[8:9] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[10:11], s[10:11] op_sel:[0,1]
+; GFX90A-NEXT: v_mul_lo_u32 v8, s12, v0
+; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v8
+; GFX90A-NEXT: v_add_u32_e32 v0, v0, v8
+; GFX90A-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX90A-NEXT: v_mul_lo_u32 v8, v0, s3
+; GFX90A-NEXT: v_sub_u32_e32 v8, s2, v8
+; GFX90A-NEXT: v_add_u32_e32 v9, 1, v0
+; GFX90A-NEXT: v_subrev_u32_e32 v11, s3, v8
+; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s3, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX90A-NEXT: v_add_u32_e32 v9, 1, v0
+; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s3, v8
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
+; GFX90A-NEXT: v_lshlrev_b64 v[8:9], 5, v[0:1]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_readfirstlane_b32 s7, v18
-; GFX90A-NEXT: s_and_b32 s7, 0xffff, s7
-; GFX90A-NEXT: s_mul_i32 s1, s1, s7
-; GFX90A-NEXT: s_mul_hi_u32 s9, s0, s7
-; GFX90A-NEXT: s_mul_i32 s0, s0, s7
-; GFX90A-NEXT: s_add_i32 s1, s9, s1
-; GFX90A-NEXT: s_lshl_b64 s[14:15], s[0:1], 5
+; GFX90A-NEXT: v_and_b32_e32 v30, 0xffff, v10
+; GFX90A-NEXT: v_mul_lo_u32 v11, s1, v30
+; GFX90A-NEXT: v_mul_hi_u32 v12, s0, v30
+; GFX90A-NEXT: v_mul_lo_u32 v10, s0, v30
+; GFX90A-NEXT: v_add_u32_e32 v11, v12, v11
+; GFX90A-NEXT: v_lshlrev_b64 v[10:11], 5, v[10:11]
+; GFX90A-NEXT: v_pk_mov_b32 v[12:13], 0, 0
; GFX90A-NEXT: s_branch .LBB3_2
-; GFX90A-NEXT: .LBB3_1: ; %Flow20
+; GFX90A-NEXT: .LBB3_1: ; %bb12
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[0:1]
-; GFX90A-NEXT: s_cbranch_vccz .LBB3_12
+; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v4, v0
+; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8
+; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v9, vcc
+; GFX90A-NEXT: s_cbranch_execz .LBB3_12
; GFX90A-NEXT: .LBB3_2: ; %bb9
; GFX90A-NEXT: ; =>This Loop Header: Depth=1
; GFX90A-NEXT: ; Child Loop BB3_5 Depth 2
-; GFX90A-NEXT: s_mov_b64 s[16:17], -1
+; GFX90A-NEXT: s_mov_b64 s[0:1], -1
; GFX90A-NEXT: s_cbranch_scc0 .LBB3_10
; GFX90A-NEXT: ; %bb.3: ; %bb14
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
-; GFX90A-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], -1
-; GFX90A-NEXT: s_mov_b32 s7, s6
-; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
-; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
-; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v8
-; GFX90A-NEXT: v_pk_mov_b32 v[8:9], s[6:7], s[6:7] op_sel:[0,1]
-; GFX90A-NEXT: v_pk_mov_b32 v[10:11], s[6:7], s[6:7] op_sel:[0,1]
-; GFX90A-NEXT: v_cmp_lt_i64_e64 s[16:17], s[4:5], 0
-; GFX90A-NEXT: s_mov_b64 s[18:19], s[10:11]
-; GFX90A-NEXT: v_pk_mov_b32 v[12:13], v[6:7], v[6:7] op_sel:[0,1]
+; GFX90A-NEXT: global_load_dwordx2 v[14:15], v[12:13], off
+; GFX90A-NEXT: v_cmp_lt_i64_e32 vcc, -1, v[4:5]
+; GFX90A-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX90A-NEXT: s_mov_b32 s5, s4
+; GFX90A-NEXT: v_cmp_gt_i64_e64 s[2:3], 0, v[4:5]
+; GFX90A-NEXT: v_pk_mov_b32 v[18:19], v[6:7], v[6:7] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[16:17], s[4:5], s[4:5] op_sel:[0,1]
+; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v20
+; GFX90A-NEXT: v_pk_mov_b32 v[20:21], s[4:5], s[4:5] op_sel:[0,1]
+; GFX90A-NEXT: v_pk_mov_b32 v[22:23], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_readfirstlane_b32 s7, v4
-; GFX90A-NEXT: v_readfirstlane_b32 s9, v5
-; GFX90A-NEXT: s_add_u32 s7, s7, 1
-; GFX90A-NEXT: s_addc_u32 s9, s9, 0
-; GFX90A-NEXT: s_mul_hi_u32 s20, s2, s7
-; GFX90A-NEXT: s_mul_i32 s9, s2, s9
-; GFX90A-NEXT: s_mul_i32 s21, s3, s7
-; GFX90A-NEXT: s_add_i32 s9, s20, s9
-; GFX90A-NEXT: s_mul_i32 s7, s2, s7
-; GFX90A-NEXT: s_add_i32 s9, s9, s21
+; GFX90A-NEXT: v_add_co_u32_e32 v24, vcc, 1, v14
+; GFX90A-NEXT: v_addc_co_u32_e32 v25, vcc, 0, v15, vcc
+; GFX90A-NEXT: v_mul_lo_u32 v25, s6, v25
+; GFX90A-NEXT: v_mul_hi_u32 v26, s6, v24
+; GFX90A-NEXT: v_mul_lo_u32 v27, s7, v24
+; GFX90A-NEXT: v_mul_lo_u32 v31, s6, v24
+; GFX90A-NEXT: v_add_u32_e32 v24, v26, v25
+; GFX90A-NEXT: v_add_u32_e32 v32, v24, v27
+; GFX90A-NEXT: v_pk_mov_b32 v[24:25], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT: s_branch .LBB3_5
; GFX90A-NEXT: .LBB3_4: ; %bb58
; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2
-; GFX90A-NEXT: v_add_co_u32_sdwa v4, vcc, v4, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; GFX90A-NEXT: s_add_u32 s18, s18, s14
-; GFX90A-NEXT: s_addc_u32 s19, s19, s15
-; GFX90A-NEXT: v_cmp_lt_i64_e64 s[22:23], -1, v[4:5]
-; GFX90A-NEXT: s_mov_b64 s[20:21], 0
-; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[22:23]
+; GFX90A-NEXT: v_add_co_u32_e32 v14, vcc, v14, v30
+; GFX90A-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
+; GFX90A-NEXT: v_add_co_u32_e32 v18, vcc, v18, v10
+; GFX90A-NEXT: v_addc_co_u32_e32 v19, vcc, v19, v11, vcc
+; GFX90A-NEXT: v_cmp_lt_i64_e64 s[10:11], -1, v[14:15]
+; GFX90A-NEXT: s_mov_b64 s[8:9], 0
+; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GFX90A-NEXT: s_cbranch_vccz .LBB3_9
; GFX90A-NEXT: .LBB3_5: ; %bb16
; GFX90A-NEXT: ; Parent Loop BB3_2 Depth=1
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
-; GFX90A-NEXT: s_add_u32 s20, s18, s7
-; GFX90A-NEXT: s_addc_u32 s21, s19, s9
-; GFX90A-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
+; GFX90A-NEXT: v_add_co_u32_e32 v26, vcc, v18, v31
+; GFX90A-NEXT: v_addc_co_u32_e32 v27, vcc, v19, v32, vcc
+; GFX90A-NEXT: global_load_dword v34, v[26:27], off offset:-12 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
+; GFX90A-NEXT: global_load_dword v33, v[26:27], off offset:-8 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] offset:-4 glc
+; GFX90A-NEXT: global_load_dword v28, v[26:27], off offset:-4 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] glc
+; GFX90A-NEXT: global_load_dword v28, v[26:27], off glc
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: ds_read_b64 v[14:15], v19
-; GFX90A-NEXT: ds_read_b64 v[16:17], v0
+; GFX90A-NEXT: ; kill: killed $vgpr26 killed $vgpr27
+; GFX90A-NEXT: ds_read_b64 v[26:27], v1
+; GFX90A-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-NEXT: ds_read_b64 v[28:29], v0
; GFX90A-NEXT: s_and_b64 vcc, exec, s[0:1]
-; GFX90A-NEXT: ; kill: killed $sgpr20 killed $sgpr21
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_cbranch_vccnz .LBB3_7
; GFX90A-NEXT: ; %bb.6: ; %bb51
; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v23, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v22, v21
-; GFX90A-NEXT: v_cvt_f32_f16_sdwa v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX90A-NEXT: v_cvt_f32_f16_e32 v20, v20
-; GFX90A-NEXT: v_pk_add_f32 v[24:25], v[2:3], v[14:15]
-; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[14:15], 0 op_sel_hi:[1,0]
-; GFX90A-NEXT: v_pk_add_f32 v[16:17], v[22:23], v[16:17]
-; GFX90A-NEXT: v_pk_add_f32 v[14:15], v[20:21], v[14:15]
-; GFX90A-NEXT: v_pk_add_f32 v[6:7], v[6:7], v[24:25]
-; GFX90A-NEXT: v_pk_add_f32 v[8:9], v[8:9], v[26:27]
-; GFX90A-NEXT: v_pk_add_f32 v[10:11], v[10:11], v[16:17]
-; GFX90A-NEXT: v_pk_add_f32 v[12:13], v[12:13], v[14:15]
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v35, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v34, v34
+; GFX90A-NEXT: v_cvt_f32_f16_sdwa v37, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX90A-NEXT: v_cvt_f32_f16_e32 v36, v33
+; GFX90A-NEXT: v_pk_add_f32 v[38:39], v[2:3], v[26:27]
+; GFX90A-NEXT: v_pk_add_f32 v[40:41], v[26:27], 0 op_sel_hi:[1,0]
+; GFX90A-NEXT: v_pk_add_f32 v[28:29], v[34:35], v[28:29]
+; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[36:37], v[26:27]
+; GFX90A-NEXT: v_pk_add_f32 v[16:17], v[16:17], v[38:39]
+; GFX90A-NEXT: v_pk_add_f32 v[20:21], v[20:21], v[40:41]
+; GFX90A-NEXT: v_pk_add_f32 v[22:23], v[22:23], v[28:29]
+; GFX90A-NEXT: v_pk_add_f32 v[24:25], v[24:25], v[26:27]
; GFX90A-NEXT: s_branch .LBB3_4
; GFX90A-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2
-; GFX90A-NEXT: s_mov_b64 s[20:21], s[16:17]
-; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[20:21]
+; GFX90A-NEXT: s_mov_b64 s[8:9], s[2:3]
+; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GFX90A-NEXT: s_cbranch_vccz .LBB3_4
; GFX90A-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: s_mov_b64 s[20:21], -1
-; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
-; GFX90A-NEXT: ; implicit-def: $sgpr18_sgpr19
+; GFX90A-NEXT: s_mov_b64 s[8:9], -1
+; GFX90A-NEXT: ; implicit-def: $vgpr14_vgpr15
+; GFX90A-NEXT: ; implicit-def: $vgpr18_vgpr19
; GFX90A-NEXT: .LBB3_9: ; %loop.exit.guard
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: s_xor_b64 s[16:17], s[20:21], -1
+; GFX90A-NEXT: s_xor_b64 s[0:1], s[8:9], -1
; GFX90A-NEXT: .LBB3_10: ; %Flow19
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: s_mov_b64 s[0:1], -1
-; GFX90A-NEXT: s_and_b64 vcc, exec, s[16:17]
-; GFX90A-NEXT: s_cbranch_vccz .LBB3_1
-; GFX90A-NEXT: ; %bb.11: ; %bb12
-; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
-; GFX90A-NEXT: s_add_u32 s4, s4, s8
-; GFX90A-NEXT: s_addc_u32 s5, s5, 0
-; GFX90A-NEXT: s_add_u32 s10, s10, s12
-; GFX90A-NEXT: s_addc_u32 s11, s11, s13
-; GFX90A-NEXT: s_mov_b64 s[0:1], 0
-; GFX90A-NEXT: s_branch .LBB3_1
+; GFX90A-NEXT: s_and_b64 vcc, exec, s[0:1]
+; GFX90A-NEXT: s_cbranch_vccnz .LBB3_1
+; GFX90A-NEXT: ; %bb.11:
+; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX90A-NEXT: .LBB3_12: ; %DummyReturnBlock
; GFX90A-NEXT: s_endpgm
bb:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index 8e16889c72e65..1f87e89a796b6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -54,49 +54,44 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s3
-; GFX6-NEXT: s_sub_i32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: udiv_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s2, s5
-; GFX9-NEXT: s_mul_i32 s5, s4, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_add_i32 s6, s4, 1
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_add_i32 s5, s4, 1
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%r = udiv i32 %x, %y
store i32 %r, ptr addrspace(1) %out
@@ -152,43 +147,39 @@ define amdgpu_kernel void @urem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s3
-; GFX6-NEXT: s_sub_i32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s3
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s3
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: urem_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s2, s5
-; GFX9-NEXT: s_mul_i32 s4, s4, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s4, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_sub_i32 s4, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%r = urem i32 %x, %y
@@ -260,19 +251,16 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s8
-; GFX6-NEXT: s_sub_i32 s0, s0, s2
-; GFX6-NEXT: s_sub_i32 s2, s0, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s8
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s2, s0
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s8
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s8
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s1, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -281,35 +269,33 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-LABEL: sdiv_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_abs_i32 s4, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX9-NEXT: s_sub_i32 s5, 0, s4
-; GFX9-NEXT: s_xor_b32 s3, s2, s3
-; GFX9-NEXT: s_abs_i32 s2, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s3, s3, 31
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6
-; GFX9-NEXT: s_mul_i32 s6, s5, s4
-; GFX9-NEXT: s_sub_i32 s2, s2, s6
-; GFX9-NEXT: s_add_i32 s7, s5, 1
-; GFX9-NEXT: s_sub_i32 s6, s2, s4
-; GFX9-NEXT: s_cmp_ge_u32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_cselect_b32 s2, s6, s2
-; GFX9-NEXT: s_add_i32 s6, s5, 1
-; GFX9-NEXT: s_cmp_ge_u32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s2, s6, s5
+; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
+; GFX9-NEXT: s_abs_i32 s5, s2
; GFX9-NEXT: s_xor_b32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: s_ashr_i32 s2, s2, 31
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v2, s5, v2
+; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%r = sdiv i32 %x, %y
@@ -377,50 +363,46 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
-; GFX6-NEXT: s_mul_i32 s1, s1, s3
-; GFX6-NEXT: s_sub_i32 s1, s8, s1
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: s_xor_b32 s1, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, s1, s0
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: srem_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_abs_i32 s3, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX9-NEXT: s_sub_i32 s5, 0, s3
-; GFX9-NEXT: s_ashr_i32 s4, s2, 31
-; GFX9-NEXT: s_abs_i32 s2, s2
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6
-; GFX9-NEXT: s_mul_i32 s5, s5, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_xor_b32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: s_abs_i32 s4, s2
+; GFX9-NEXT: s_ashr_i32 s2, s2, 31
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%r = srem i32 %x, %y
@@ -1180,192 +1162,173 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-LABEL: udiv_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
-; GFX6-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x9
-; GFX6-NEXT: s_mov_b32 s19, 0xf000
-; GFX6-NEXT: s_mov_b32 s18, -1
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX6-NEXT: s_sub_i32 s0, 0, s12
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13
; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s14
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s15
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s12
-; GFX6-NEXT: s_sub_i32 s0, s8, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s12
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX6-NEXT: s_sub_i32 s2, 0, s13
-; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT: s_sub_i32 s0, 0, s13
+; GFX6-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT: s_sub_i32 s0, 0, s14
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
-; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT: v_readfirstlane_b32 s2, v1
-; GFX6-NEXT: s_mul_i32 s2, s2, s13
-; GFX6-NEXT: s_sub_i32 s2, s9, s2
-; GFX6-NEXT: s_sub_i32 s3, s2, s13
-; GFX6-NEXT: s_cmp_ge_u32 s2, s13
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s12
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v5, v1, s13
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s8, v2
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s12, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s9, v5
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT: s_cselect_b32 s2, s3, s2
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s2, s13
-; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX6-NEXT: s_sub_i32 s6, 0, s14
-; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s13, v3
+; GFX6-NEXT: v_mul_lo_u32 v6, s0, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT: v_mul_hi_u32 v5, v3, v5
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3]
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT: v_mul_hi_u32 v3, s10, v3
-; GFX6-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v6
-; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
-; GFX6-NEXT: v_readfirstlane_b32 s6, v3
-; GFX6-NEXT: s_mul_i32 s6, s6, s14
-; GFX6-NEXT: s_sub_i32 s6, s10, s6
-; GFX6-NEXT: s_sub_i32 s7, s6, s14
-; GFX6-NEXT: s_cmp_ge_u32 s6, s14
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v3
-; GFX6-NEXT: s_cselect_b32 s6, s7, s6
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s6, s14
-; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 0
-; GFX6-NEXT: s_sub_i32 s8, 0, s15
-; GFX6-NEXT: v_mul_lo_u32 v7, s8, v5
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_mul_hi_u32 v4, v2, v6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s15
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v1
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v6
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v3
+; GFX6-NEXT: s_sub_i32 s0, 0, s15
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, s14
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
+; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
+; GFX6-NEXT: v_mul_hi_u32 v4, s11, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s14, v3
+; GFX6-NEXT: v_mul_lo_u32 v6, v4, s15
+; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s11, v6
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s15, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v3
-; GFX6-NEXT: v_mul_hi_u32 v7, v5, v7
-; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[6:7]
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v7
-; GFX6-NEXT: v_mul_hi_u32 v5, s11, v5
-; GFX6-NEXT: v_readfirstlane_b32 s0, v5
-; GFX6-NEXT: s_mul_i32 s0, s0, s15
-; GFX6-NEXT: s_sub_i32 s0, s11, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s15
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v5
-; GFX6-NEXT: s_cmp_ge_u32 s0, s15
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v3
-; GFX6-NEXT: s_cmp_ge_u32 s0, s15
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: udiv_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX9-NEXT: s_sub_i32 s0, 0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GFX9-NEXT: s_sub_i32 s2, 0, s12
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s14
+; GFX9-NEXT: s_sub_i32 s1, 0, s13
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s14
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s14
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: s_mul_i32 s2, s2, s3
-; GFX9-NEXT: s_mul_hi_u32 s2, s3, s2
-; GFX9-NEXT: s_add_i32 s3, s3, s2
-; GFX9-NEXT: s_mul_hi_u32 s2, s8, s3
-; GFX9-NEXT: s_mul_i32 s3, s2, s12
-; GFX9-NEXT: s_sub_i32 s3, s8, s3
-; GFX9-NEXT: s_add_i32 s5, s2, 1
-; GFX9-NEXT: s_sub_i32 s6, s3, s12
-; GFX9-NEXT: s_cmp_ge_u32 s3, s12
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_cselect_b32 s3, s6, s3
-; GFX9-NEXT: s_add_i32 s5, s2, 1
-; GFX9-NEXT: s_cmp_ge_u32 s3, s12
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sub_i32 s3, 0, s13
-; GFX9-NEXT: s_mul_i32 s3, s3, s4
-; GFX9-NEXT: s_mul_hi_u32 s3, s4, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v2
-; GFX9-NEXT: s_mul_hi_u32 s3, s9, s4
-; GFX9-NEXT: s_mul_i32 s4, s3, s13
-; GFX9-NEXT: s_sub_i32 s4, s9, s4
-; GFX9-NEXT: s_add_i32 s5, s3, 1
-; GFX9-NEXT: s_sub_i32 s6, s4, s13
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: s_cmp_ge_u32 s4, s13
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_cselect_b32 s3, s5, s3
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_add_i32 s5, s3, 1
-; GFX9-NEXT: s_cmp_ge_u32 s4, s13
-; GFX9-NEXT: s_cselect_b32 s3, s5, s3
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s15
-; GFX9-NEXT: s_sub_i32 s4, 0, s14
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_mul_hi_u32 s4, s10, s5
-; GFX9-NEXT: s_mul_i32 s5, s4, s14
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_add_i32 s6, s4, 1
-; GFX9-NEXT: s_sub_i32 s7, s5, s14
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: s_cmp_ge_u32 s5, s14
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_add_i32 s6, s4, 1
-; GFX9-NEXT: s_cmp_ge_u32 s5, s14
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_sub_i32 s5, 0, s15
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s11, s6
-; GFX9-NEXT: s_mul_i32 s6, s5, s15
-; GFX9-NEXT: s_sub_i32 s6, s11, s6
-; GFX9-NEXT: s_add_i32 s7, s5, 1
-; GFX9-NEXT: s_sub_i32 s8, s6, s15
-; GFX9-NEXT: s_cmp_ge_u32 s6, s15
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_add_i32 s7, s5, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s15
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
-; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v1
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s12
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s13
+; GFX9-NEXT: v_mul_hi_u32 v6, v2, v6
+; GFX9-NEXT: v_sub_u32_e32 v3, s8, v3
+; GFX9-NEXT: v_subrev_u32_e32 v8, s12, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s15
+; GFX9-NEXT: v_sub_u32_e32 v4, s9, v4
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
+; GFX9-NEXT: s_sub_i32 s2, 0, s15
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v8, s13, v4
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v6
+; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
+; GFX9-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v7
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v8, v2, s14
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX9-NEXT: v_sub_u32_e32 v6, s10, v8
+; GFX9-NEXT: v_subrev_u32_e32 v8, s14, v6
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, v3, s15
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, s11, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_subrev_u32_e32 v7, s15, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
%r = udiv <4 x i32> %x, %y
store <4 x i32> %r, ptr addrspace(1) %out
@@ -1504,82 +1467,74 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX6-NEXT: s_sub_i32 s0, 0, s12
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13
+; GFX6-NEXT: s_sub_i32 s1, 0, s13
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s14
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s15
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s14
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s12
-; GFX6-NEXT: s_sub_i32 s0, s8, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s12
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s12
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: s_cselect_b32 s6, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s13
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s15
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s13
-; GFX6-NEXT: s_sub_i32 s0, s9, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s13
-; GFX6-NEXT: s_cmp_ge_u32 s0, s13
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s13
-; GFX6-NEXT: s_cmp_ge_u32 s0, s13
-; GFX6-NEXT: s_cselect_b32 s7, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s14
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s14
-; GFX6-NEXT: s_sub_i32 s0, s10, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s14
-; GFX6-NEXT: s_cmp_ge_u32 s0, s14
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s14
-; GFX6-NEXT: s_cmp_ge_u32 s0, s14
-; GFX6-NEXT: s_cselect_b32 s8, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s15
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s1, v1
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v2, s11, v0
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: v_readfirstlane_b32 s4, v2
-; GFX6-NEXT: s_mul_i32 s4, s4, s15
-; GFX6-NEXT: s_sub_i32 s4, s11, s4
-; GFX6-NEXT: s_sub_i32 s5, s4, s15
-; GFX6-NEXT: s_cmp_ge_u32 s4, s15
-; GFX6-NEXT: s_cselect_b32 s4, s5, s4
-; GFX6-NEXT: s_sub_i32 s5, s4, s15
-; GFX6-NEXT: s_cmp_ge_u32 s4, s15
-; GFX6-NEXT: s_cselect_b32 s4, s5, s4
-; GFX6-NEXT: v_mov_b32_e32 v2, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_sub_i32 s4, 0, s14
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX6-NEXT: s_sub_i32 s4, 0, s15
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s14
+; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GFX6-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s14, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s15
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s14, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s11, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s15, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s15, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
@@ -1596,76 +1551,68 @@ define amdgpu_kernel void @urem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s14
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s3, 0, s13
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: s_mul_i32 s2, s2, s3
-; GFX9-NEXT: s_mul_hi_u32 s2, s3, s2
-; GFX9-NEXT: s_add_i32 s3, s3, s2
-; GFX9-NEXT: s_mul_hi_u32 s2, s8, s3
-; GFX9-NEXT: s_mul_i32 s2, s2, s12
-; GFX9-NEXT: s_sub_i32 s2, s8, s2
-; GFX9-NEXT: s_sub_i32 s3, s2, s12
-; GFX9-NEXT: s_cmp_ge_u32 s2, s12
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_sub_i32 s3, s2, s12
-; GFX9-NEXT: s_cmp_ge_u32 s2, s12
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_sub_i32 s3, 0, s13
-; GFX9-NEXT: s_mul_i32 s3, s3, s4
-; GFX9-NEXT: s_mul_hi_u32 s3, s4, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s3
-; GFX9-NEXT: s_mul_hi_u32 s3, s9, s4
-; GFX9-NEXT: s_mul_i32 s3, s3, s13
-; GFX9-NEXT: s_sub_i32 s3, s9, s3
-; GFX9-NEXT: s_sub_i32 s4, s3, s13
+; GFX9-NEXT: v_mul_lo_u32 v3, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: s_cmp_ge_u32 s3, s13
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_sub_i32 s4, s3, s13
-; GFX9-NEXT: s_cmp_ge_u32 s3, s13
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s15
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_sub_i32 s4, 0, s14
-; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_mul_hi_u32 s4, s10, s5
-; GFX9-NEXT: s_mul_i32 s4, s4, s14
-; GFX9-NEXT: s_sub_i32 s4, s10, s4
-; GFX9-NEXT: s_sub_i32 s5, s4, s14
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: s_cmp_ge_u32 s4, s14
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_sub_i32 s5, s4, s14
-; GFX9-NEXT: s_cmp_ge_u32 s4, s14
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_sub_i32 s5, 0, s15
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s11, s6
-; GFX9-NEXT: s_mul_i32 s5, s5, s15
-; GFX9-NEXT: s_sub_i32 s5, s11, s5
-; GFX9-NEXT: s_sub_i32 s6, s5, s15
-; GFX9-NEXT: s_cmp_ge_u32 s5, s15
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_sub_i32 s6, s5, s15
-; GFX9-NEXT: s_cmp_ge_u32 s5, s15
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-NEXT: v_mul_lo_u32 v5, s3, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s14
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s15
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
+; GFX9-NEXT: s_sub_i32 s2, 0, s15
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX9-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX9-NEXT: v_sub_u32_e32 v0, s8, v0
+; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v0
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s14
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, s9, v1
+; GFX9-NEXT: v_subrev_u32_e32 v6, s12, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, s13, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s15
+; GFX9-NEXT: v_subrev_u32_e32 v6, s13, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX9-NEXT: v_sub_u32_e32 v2, s10, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s14, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s14, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, s11, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s15, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s15, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
%r = urem <4 x i32> %x, %y
@@ -1845,241 +1792,220 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-LABEL: sdiv_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
-; GFX6-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x9
-; GFX6-NEXT: s_mov_b32 s19, 0xf000
-; GFX6-NEXT: s_mov_b32 s18, -1
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_abs_i32 s0, s12
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX6-NEXT: s_sub_i32 s1, 0, s0
-; GFX6-NEXT: s_xor_b32 s2, s8, s12
+; GFX6-NEXT: s_abs_i32 s6, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_abs_i32 s7, s13
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT: s_sub_i32 s4, 0, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_sub_i32 s5, 0, s7
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s1, v0
-; GFX6-NEXT: s_abs_i32 s1, s8
-; GFX6-NEXT: s_ashr_i32 s8, s2, 31
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s0
-; GFX6-NEXT: s_sub_i32 s1, s1, s2
-; GFX6-NEXT: s_sub_i32 s2, s1, s0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX6-NEXT: s_abs_i32 s2, s13
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX6-NEXT: s_sub_i32 s3, 0, s2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_xor_b32 s6, s9, s13
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1]
-; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT: v_mul_lo_u32 v3, s3, v2
-; GFX6-NEXT: s_abs_i32 s3, s9
-; GFX6-NEXT: s_ashr_i32 s9, s6, 31
-; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_hi_u32 v2, s3, v2
-; GFX6-NEXT: v_readfirstlane_b32 s6, v2
-; GFX6-NEXT: s_mul_i32 s6, s6, s2
-; GFX6-NEXT: s_sub_i32 s3, s3, s6
-; GFX6-NEXT: s_sub_i32 s6, s3, s2
-; GFX6-NEXT: s_cmp_ge_u32 s3, s2
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v2
-; GFX6-NEXT: s_cselect_b32 s3, s6, s3
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s3, s2
-; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s4, v0
+; GFX6-NEXT: s_abs_i32 s4, s8
+; GFX6-NEXT: v_mul_lo_u32 v3, s5, v1
+; GFX6-NEXT: s_xor_b32 s5, s8, s12
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_ashr_i32 s5, s5, 31
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s6, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; GFX6-NEXT: s_abs_i32 s6, s14
-; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s6
-; GFX6-NEXT: s_sub_i32 s7, 0, s6
-; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s6
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: s_abs_i32 s4, s9
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s7
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s7, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX6-NEXT: s_sub_i32 s4, 0, s6
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, v3, v4
+; GFX6-NEXT: s_abs_i32 s7, s15
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT: s_abs_i32 s4, s10
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT: v_mul_hi_u32 v2, s4, v2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; GFX6-NEXT: s_xor_b32 s5, s9, s13
+; GFX6-NEXT: s_ashr_i32 s5, s5, 31
+; GFX6-NEXT: v_mul_lo_u32 v3, v2, s6
; GFX6-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GFX6-NEXT: v_mul_lo_u32 v5, s7, v4
-; GFX6-NEXT: s_abs_i32 s7, s10
-; GFX6-NEXT: s_xor_b32 s10, s10, s14
-; GFX6-NEXT: s_ashr_i32 s10, s10, 31
+; GFX6-NEXT: v_xor_b32_e32 v1, s5, v1
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s6, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX6-NEXT: s_sub_i32 s4, 0, s7
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v5, s4, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GFX6-NEXT: v_mul_hi_u32 v4, s7, v4
-; GFX6-NEXT: v_readfirstlane_b32 s12, v4
-; GFX6-NEXT: s_mul_i32 s12, s12, s6
-; GFX6-NEXT: s_sub_i32 s7, s7, s12
-; GFX6-NEXT: s_sub_i32 s12, s7, s6
-; GFX6-NEXT: s_cmp_ge_u32 s7, s6
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT: s_cselect_b32 s7, s12, s7
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s7, s6
-; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 0
-; GFX6-NEXT: s_abs_i32 s12, s15
-; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s12
-; GFX6-NEXT: s_sub_i32 s0, 0, s12
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v6
-; GFX6-NEXT: s_abs_i32 s1, s11
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v1
-; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[2:3]
-; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[6:7]
-; GFX6-NEXT: v_xor_b32_e32 v1, s9, v1
-; GFX6-NEXT: v_mul_lo_u32 v2, s0, v6
-; GFX6-NEXT: s_xor_b32 s0, s11, s15
-; GFX6-NEXT: v_xor_b32_e32 v3, s10, v3
-; GFX6-NEXT: s_ashr_i32 s0, s0, 31
-; GFX6-NEXT: v_mul_hi_u32 v2, v6, v2
-; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s9, v1
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, s1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s10, v3
-; GFX6-NEXT: v_readfirstlane_b32 s2, v4
-; GFX6-NEXT: s_mul_i32 s2, s2, s12
-; GFX6-NEXT: s_sub_i32 s1, s1, s2
-; GFX6-NEXT: s_sub_i32 s2, s1, s12
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v4
-; GFX6-NEXT: s_cmp_ge_u32 s1, s12
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s12
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s0, v3
-; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT: s_abs_i32 s4, s11
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v5
+; GFX6-NEXT: v_mul_hi_u32 v3, s4, v3
+; GFX6-NEXT: s_xor_b32 s5, s10, s14
+; GFX6-NEXT: s_ashr_i32 s5, s5, 31
+; GFX6-NEXT: v_xor_b32_e32 v2, s5, v2
+; GFX6-NEXT: v_mul_lo_u32 v4, v3, s7
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s5, v2
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s7, v4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT: s_xor_b32 s5, s11, s15
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
+; GFX6-NEXT: s_ashr_i32 s5, s5, 31
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_xor_b32_e32 v3, s5, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s5, v3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_abs_i32 s0, s12
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX9-NEXT: s_sub_i32 s3, 0, s0
-; GFX9-NEXT: s_abs_i32 s2, s8
-; GFX9-NEXT: s_xor_b32 s1, s8, s12
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s1, s1, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s3, s3, s6
-; GFX9-NEXT: s_mul_hi_u32 s3, s6, s3
-; GFX9-NEXT: s_add_i32 s6, s6, s3
-; GFX9-NEXT: s_mul_hi_u32 s3, s2, s6
-; GFX9-NEXT: s_mul_i32 s6, s3, s0
-; GFX9-NEXT: s_sub_i32 s2, s2, s6
-; GFX9-NEXT: s_add_i32 s7, s3, 1
-; GFX9-NEXT: s_sub_i32 s6, s2, s0
-; GFX9-NEXT: s_cmp_ge_u32 s2, s0
-; GFX9-NEXT: s_cselect_b32 s3, s7, s3
-; GFX9-NEXT: s_cselect_b32 s2, s6, s2
-; GFX9-NEXT: s_add_i32 s6, s3, 1
-; GFX9-NEXT: s_cmp_ge_u32 s2, s0
-; GFX9-NEXT: s_cselect_b32 s0, s6, s3
-; GFX9-NEXT: s_abs_i32 s2, s13
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX9-NEXT: s_xor_b32 s0, s0, s1
-; GFX9-NEXT: s_sub_i32 s7, 0, s2
-; GFX9-NEXT: s_sub_i32 s8, s0, s1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_abs_i32 s6, s9
-; GFX9-NEXT: s_xor_b32 s3, s9, s13
-; GFX9-NEXT: s_ashr_i32 s3, s3, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s1, s0, s7
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX9-NEXT: s_mul_i32 s1, s0, s2
-; GFX9-NEXT: s_sub_i32 s1, s6, s1
-; GFX9-NEXT: s_add_i32 s7, s0, 1
-; GFX9-NEXT: s_sub_i32 s6, s1, s2
-; GFX9-NEXT: s_cmp_ge_u32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s0, s7, s0
-; GFX9-NEXT: s_cselect_b32 s1, s6, s1
-; GFX9-NEXT: s_add_i32 s6, s0, 1
-; GFX9-NEXT: s_cmp_ge_u32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s0, s6, s0
-; GFX9-NEXT: s_abs_i32 s1, s14
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
-; GFX9-NEXT: s_xor_b32 s0, s0, s3
-; GFX9-NEXT: s_sub_i32 s7, 0, s1
-; GFX9-NEXT: s_sub_i32 s3, s0, s3
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_abs_i32 s6, s10
-; GFX9-NEXT: s_xor_b32 s2, s10, s14
-; GFX9-NEXT: s_ashr_i32 s2, s2, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s7, s0, s7
-; GFX9-NEXT: s_add_i32 s0, s0, s7
-; GFX9-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX9-NEXT: s_mul_i32 s7, s0, s1
-; GFX9-NEXT: s_sub_i32 s6, s6, s7
-; GFX9-NEXT: s_add_i32 s9, s0, 1
-; GFX9-NEXT: s_sub_i32 s7, s6, s1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s1
-; GFX9-NEXT: s_cselect_b32 s0, s9, s0
-; GFX9-NEXT: s_cselect_b32 s6, s7, s6
-; GFX9-NEXT: s_add_i32 s7, s0, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s1
-; GFX9-NEXT: s_cselect_b32 s6, s7, s0
-; GFX9-NEXT: s_abs_i32 s7, s15
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s7
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: s_xor_b32 s5, s6, s2
-; GFX9-NEXT: s_sub_i32 s6, 0, s7
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_abs_i32 s2, s12
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s2
+; GFX9-NEXT: s_abs_i32 s3, s13
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX9-NEXT: s_sub_i32 s5, 0, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_sub_i32 s6, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX9-NEXT: s_sub_i32 s2, s5, s2
-; GFX9-NEXT: s_abs_i32 s4, s11
-; GFX9-NEXT: s_xor_b32 s3, s11, s15
+; GFX9-NEXT: s_xor_b32 s4, s8, s12
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
-; GFX9-NEXT: s_ashr_i32 s3, s3, 31
-; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: s_mul_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s6, s5, s6
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX9-NEXT: s_mul_i32 s6, s5, s7
-; GFX9-NEXT: s_sub_i32 s4, s4, s6
-; GFX9-NEXT: s_add_i32 s8, s5, 1
-; GFX9-NEXT: s_sub_i32 s6, s4, s7
-; GFX9-NEXT: s_cmp_ge_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s5, s8, s5
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_add_i32 s6, s5, 1
-; GFX9-NEXT: s_cmp_ge_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s6, s5
-; GFX9-NEXT: s_xor_b32 s4, s4, s3
-; GFX9-NEXT: s_sub_i32 s3, s4, s3
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s3
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-NEXT: s_abs_i32 s7, s9
+; GFX9-NEXT: v_mul_lo_u32 v3, s5, v1
+; GFX9-NEXT: s_abs_i32 s5, s8
+; GFX9-NEXT: v_mul_lo_u32 v4, s6, v2
+; GFX9-NEXT: s_abs_i32 s8, s14
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: s_ashr_i32 s4, s4, 31
+; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4
+; GFX9-NEXT: s_xor_b32 s6, s9, s13
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_hi_u32 v2, s7, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, v1, s2
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, v2, s3
+; GFX9-NEXT: v_sub_u32_e32 v3, s5, v3
+; GFX9-NEXT: v_subrev_u32_e32 v6, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s8
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_sub_u32_e32 v4, s7, v5
+; GFX9-NEXT: v_subrev_u32_e32 v1, s4, v1
+; GFX9-NEXT: v_subrev_u32_e32 v6, s3, v4
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v4
+; GFX9-NEXT: s_sub_i32 s4, 0, s8
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v6, s4, v3
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v6
+; GFX9-NEXT: s_abs_i32 s4, s15
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s4
+; GFX9-NEXT: s_abs_i32 s3, s10
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v3, s3, v3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX9-NEXT: s_ashr_i32 s2, s6, 31
+; GFX9-NEXT: v_xor_b32_e32 v2, s2, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, v3, s8
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v3
+; GFX9-NEXT: v_sub_u32_e32 v5, s3, v5
+; GFX9-NEXT: s_sub_i32 s3, 0, s4
+; GFX9-NEXT: v_mul_lo_u32 v7, s3, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: s_abs_i32 s3, s11
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v7
+; GFX9-NEXT: v_subrev_u32_e32 v8, s8, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_mul_hi_u32 v4, s3, v4
+; GFX9-NEXT: v_subrev_u32_e32 v2, s2, v2
+; GFX9-NEXT: s_xor_b32 s2, s10, s14
+; GFX9-NEXT: v_add_u32_e32 v7, 1, v3
+; GFX9-NEXT: v_mul_lo_u32 v5, v4, s4
+; GFX9-NEXT: s_ashr_i32 s2, s2, 31
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, s3, v5
+; GFX9-NEXT: v_subrev_u32_e32 v7, s4, v5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5
+; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v3
+; GFX9-NEXT: s_xor_b32 s2, s11, s15
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v4
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v5
+; GFX9-NEXT: s_ashr_i32 s2, s2, 31
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v4, s2, v4
+; GFX9-NEXT: v_subrev_u32_e32 v4, s2, v4
+; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1]
; GFX9-NEXT: s_endpgm
%r = sdiv <4 x i32> %x, %y
store <4 x i32> %r, ptr addrspace(1) %out
@@ -2246,107 +2172,98 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX6-LABEL: srem_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_abs_i32 s0, s12
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX6-NEXT: s_sub_i32 s1, 0, s0
-; GFX6-NEXT: s_ashr_i32 s2, s8, 31
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s1, v0
-; GFX6-NEXT: s_abs_i32 s1, s8
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT: v_readfirstlane_b32 s3, v0
-; GFX6-NEXT: s_mul_i32 s3, s3, s0
-; GFX6-NEXT: s_sub_i32 s1, s1, s3
-; GFX6-NEXT: s_sub_i32 s3, s1, s0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: s_cselect_b32 s1, s3, s1
-; GFX6-NEXT: s_sub_i32 s3, s1, s0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: s_cselect_b32 s0, s3, s1
-; GFX6-NEXT: s_abs_i32 s1, s13
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s1
-; GFX6-NEXT: s_sub_i32 s3, 0, s1
-; GFX6-NEXT: s_xor_b32 s0, s0, s2
-; GFX6-NEXT: s_sub_i32 s7, s0, s2
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_ashr_i32 s6, s9, 31
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s3, v0
-; GFX6-NEXT: s_abs_i32 s3, s9
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s1
-; GFX6-NEXT: s_sub_i32 s0, s3, s0
-; GFX6-NEXT: s_sub_i32 s2, s0, s1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s1
-; GFX6-NEXT: s_cselect_b32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s2, s0, s1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s1
-; GFX6-NEXT: s_cselect_b32 s0, s2, s0
-; GFX6-NEXT: s_abs_i32 s1, s14
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s1
-; GFX6-NEXT: s_sub_i32 s2, 0, s1
-; GFX6-NEXT: s_xor_b32 s0, s0, s6
-; GFX6-NEXT: s_sub_i32 s6, s0, s6
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_ashr_i32 s8, s10, 31
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
-; GFX6-NEXT: s_abs_i32 s2, s10
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s1
-; GFX6-NEXT: s_sub_i32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s2, s0, s1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s1
-; GFX6-NEXT: s_cselect_b32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s2, s0, s1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s1
-; GFX6-NEXT: s_cselect_b32 s9, s2, s0
-; GFX6-NEXT: s_abs_i32 s10, s15
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s10
-; GFX6-NEXT: s_sub_i32 s0, 0, s10
; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_abs_i32 s6, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX6-NEXT: s_abs_i32 s7, s13
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT: s_sub_i32 s4, 0, s6
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_sub_i32 s5, 0, s7
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0
-; GFX6-NEXT: v_mov_b32_e32 v0, s7
-; GFX6-NEXT: v_mul_lo_u32 v1, s0, v2
-; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: s_abs_i32 s4, s11
-; GFX6-NEXT: s_ashr_i32 s5, s11, 31
-; GFX6-NEXT: v_mul_hi_u32 v3, v2, v1
-; GFX6-NEXT: v_mov_b32_e32 v1, s6
-; GFX6-NEXT: s_xor_b32 s6, s9, s8
-; GFX6-NEXT: s_sub_i32 s6, s6, s8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s4, v0
+; GFX6-NEXT: s_abs_i32 s4, s8
+; GFX6-NEXT: v_mul_lo_u32 v3, s5, v1
+; GFX6-NEXT: s_ashr_i32 s5, s8, 31
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_abs_i32 s8, s9
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_mul_hi_u32 v1, s8, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX6-NEXT: s_abs_i32 s4, s14
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s4
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
+; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: s_sub_i32 s6, 0, s4
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v4, s6, v2
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s7, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_mul_hi_u32 v3, v2, v4
+; GFX6-NEXT: s_abs_i32 s7, s15
+; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GFX6-NEXT: s_abs_i32 s6, s10
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT: v_mul_hi_u32 v2, s4, v2
-; GFX6-NEXT: v_readfirstlane_b32 s7, v2
-; GFX6-NEXT: s_mul_i32 s7, s7, s10
-; GFX6-NEXT: s_sub_i32 s4, s4, s7
-; GFX6-NEXT: s_sub_i32 s7, s4, s10
-; GFX6-NEXT: s_cmp_ge_u32 s4, s10
-; GFX6-NEXT: s_cselect_b32 s4, s7, s4
-; GFX6-NEXT: s_sub_i32 s7, s4, s10
-; GFX6-NEXT: s_cmp_ge_u32 s4, s10
-; GFX6-NEXT: s_cselect_b32 s4, s7, s4
-; GFX6-NEXT: s_xor_b32 s4, s4, s5
-; GFX6-NEXT: s_sub_i32 s4, s4, s5
-; GFX6-NEXT: v_mov_b32_e32 v2, s6
-; GFX6-NEXT: v_mov_b32_e32 v3, s4
-; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v4
+; GFX6-NEXT: s_ashr_i32 s5, s9, 31
+; GFX6-NEXT: v_xor_b32_e32 v1, s5, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s4
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
+; GFX6-NEXT: s_sub_i32 s6, 0, s7
+; GFX6-NEXT: v_mul_lo_u32 v4, s6, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: s_abs_i32 s6, s11
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
+; GFX6-NEXT: s_ashr_i32 s5, s10, 31
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s7
+; GFX6-NEXT: v_xor_b32_e32 v2, s5, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s5, v2
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s7, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s7, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX6-NEXT: s_ashr_i32 s4, s11, 31
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_xor_b32_e32 v3, s4, v3
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
@@ -2355,103 +2272,95 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, <4 x i32> %x, <4 x
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_abs_i32 s0, s12
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX9-NEXT: s_sub_i32 s3, 0, s0
-; GFX9-NEXT: s_abs_i32 s2, s8
-; GFX9-NEXT: s_ashr_i32 s1, s8, 31
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s3, s3, s6
-; GFX9-NEXT: s_mul_hi_u32 s3, s6, s3
-; GFX9-NEXT: s_add_i32 s6, s6, s3
-; GFX9-NEXT: s_mul_hi_u32 s3, s2, s6
-; GFX9-NEXT: s_mul_i32 s3, s3, s0
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s3, s2, s0
-; GFX9-NEXT: s_cmp_ge_u32 s2, s0
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_sub_i32 s3, s2, s0
-; GFX9-NEXT: s_cmp_ge_u32 s2, s0
-; GFX9-NEXT: s_cselect_b32 s0, s3, s2
-; GFX9-NEXT: s_abs_i32 s2, s13
+; GFX9-NEXT: s_abs_i32 s2, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX9-NEXT: s_xor_b32 s0, s0, s1
-; GFX9-NEXT: s_sub_i32 s7, 0, s2
-; GFX9-NEXT: s_sub_i32 s8, s0, s1
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_abs_i32 s6, s9
-; GFX9-NEXT: s_ashr_i32 s3, s9, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s1, s0, s7
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX9-NEXT: s_mul_i32 s0, s0, s2
-; GFX9-NEXT: s_sub_i32 s0, s6, s0
-; GFX9-NEXT: s_sub_i32 s1, s0, s2
-; GFX9-NEXT: s_cmp_ge_u32 s0, s2
-; GFX9-NEXT: s_cselect_b32 s0, s1, s0
-; GFX9-NEXT: s_sub_i32 s1, s0, s2
-; GFX9-NEXT: s_cmp_ge_u32 s0, s2
-; GFX9-NEXT: s_cselect_b32 s0, s1, s0
-; GFX9-NEXT: s_abs_i32 s1, s14
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
-; GFX9-NEXT: s_xor_b32 s0, s0, s3
-; GFX9-NEXT: s_sub_i32 s7, 0, s1
-; GFX9-NEXT: s_sub_i32 s3, s0, s3
+; GFX9-NEXT: s_abs_i32 s3, s13
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX9-NEXT: s_sub_i32 s0, 0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_abs_i32 s6, s10
-; GFX9-NEXT: s_ashr_i32 s2, s10, 31
+; GFX9-NEXT: s_sub_i32 s1, 0, s3
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_abs_i32 s7, s14
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s7, s0, s7
-; GFX9-NEXT: s_add_i32 s0, s0, s7
-; GFX9-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX9-NEXT: s_mul_i32 s0, s0, s1
-; GFX9-NEXT: s_sub_i32 s0, s6, s0
-; GFX9-NEXT: s_sub_i32 s6, s0, s1
-; GFX9-NEXT: s_cmp_ge_u32 s0, s1
-; GFX9-NEXT: s_cselect_b32 s0, s6, s0
-; GFX9-NEXT: s_sub_i32 s6, s0, s1
-; GFX9-NEXT: s_cmp_ge_u32 s0, s1
-; GFX9-NEXT: s_cselect_b32 s6, s6, s0
-; GFX9-NEXT: s_abs_i32 s7, s15
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_abs_i32 s6, s9
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s1, v1
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: s_xor_b32 s5, s6, s2
-; GFX9-NEXT: s_sub_i32 s6, 0, s7
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v1
-; GFX9-NEXT: s_sub_i32 s2, s5, s2
-; GFX9-NEXT: s_abs_i32 s4, s11
-; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: s_abs_i32 s5, s8
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: s_ashr_i32 s4, s8, 31
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s7
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v1, s6, v1
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX9-NEXT: s_ashr_i32 s8, s9, 31
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: s_ashr_i32 s3, s11, 31
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
-; GFX9-NEXT: v_readfirstlane_b32 s5, v2
-; GFX9-NEXT: s_mul_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s6, s5, s6
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX9-NEXT: s_mul_i32 s5, s5, s7
-; GFX9-NEXT: s_sub_i32 s4, s4, s5
-; GFX9-NEXT: s_sub_i32 s5, s4, s7
-; GFX9-NEXT: s_cmp_ge_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_sub_i32 s5, s4, s7
-; GFX9-NEXT: s_cmp_ge_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_xor_b32 s4, s4, s3
-; GFX9-NEXT: s_sub_i32 s3, s4, s3
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_sub_u32_e32 v1, s6, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v5, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: s_sub_i32 s2, 0, s7
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s2, v2
+; GFX9-NEXT: s_abs_i32 s2, s15
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s2
+; GFX9-NEXT: v_subrev_u32_e32 v3, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_mul_hi_u32 v3, v2, v5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v6
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v5
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: s_abs_i32 s3, s10
+; GFX9-NEXT: s_sub_i32 s4, 0, s2
+; GFX9-NEXT: v_mul_hi_u32 v2, s3, v2
+; GFX9-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX9-NEXT: s_ashr_i32 s4, s10, 31
+; GFX9-NEXT: v_xor_b32_e32 v1, s8, v1
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s7
+; GFX9-NEXT: v_mul_hi_u32 v5, v3, v5
+; GFX9-NEXT: v_subrev_u32_e32 v1, s8, v1
+; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2
+; GFX9-NEXT: s_abs_i32 s3, s11
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, s3, v3
+; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, v3, s2
+; GFX9-NEXT: v_subrev_u32_e32 v5, s7, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX9-NEXT: v_sub_u32_e32 v3, s3, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s4, v2
+; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
+; GFX9-NEXT: s_ashr_i32 s4, s11, 31
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, s4, v3
+; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
@@ -5665,110 +5574,100 @@ define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
;
; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b32 s0, 0x1000, s10
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GFX6-NEXT: s_sub_i32 s1, 0, s0
-; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s11
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s2
+; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_sub_i32 s6, 0, s2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s1, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
-; GFX6-NEXT: s_mul_i32 s1, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s8, s1
-; GFX6-NEXT: s_sub_i32 s3, s1, s0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT: s_cselect_b32 s1, s3, s1
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cmp_ge_u32 s1, s0
-; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX6-NEXT: s_sub_i32 s3, 0, s2
-; GFX6-NEXT: v_mul_lo_u32 v3, s3, v1
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v0
+; GFX6-NEXT: s_sub_i32 s6, 0, s3
+; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s9, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: s_mul_i32 s0, s0, s2
-; GFX6-NEXT: s_sub_i32 s0, s9, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s2, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s1, v4
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s3, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s2
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: s_sub_i32 s2, 0, s7
+; GFX9-NEXT: s_sub_i32 s3, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s4, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s0, s5
-; GFX9-NEXT: s_mul_i32 s5, s4, s7
-; GFX9-NEXT: s_sub_i32 s0, s0, s5
-; GFX9-NEXT: s_add_i32 s9, s4, 1
-; GFX9-NEXT: s_sub_i32 s5, s0, s7
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: s_cselect_b32 s4, s9, s4
-; GFX9-NEXT: s_cselect_b32 s0, s5, s0
-; GFX9-NEXT: s_add_i32 s5, s4, 1
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
-; GFX9-NEXT: s_cselect_b32 s0, s5, s4
-; GFX9-NEXT: s_sub_i32 s4, 0, s6
-; GFX9-NEXT: s_mul_i32 s4, s4, s8
-; GFX9-NEXT: s_mul_hi_u32 s4, s8, s4
-; GFX9-NEXT: s_add_i32 s8, s8, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s1, s8
-; GFX9-NEXT: s_mul_i32 s5, s4, s6
-; GFX9-NEXT: s_sub_i32 s1, s1, s5
-; GFX9-NEXT: s_add_i32 s7, s4, 1
-; GFX9-NEXT: s_sub_i32 s5, s1, s6
-; GFX9-NEXT: s_cmp_ge_u32 s1, s6
-; GFX9-NEXT: s_cselect_b32 s4, s7, s4
-; GFX9-NEXT: s_cselect_b32 s1, s5, s1
-; GFX9-NEXT: s_add_i32 s5, s4, 1
-; GFX9-NEXT: s_cmp_ge_u32 s1, s6
-; GFX9-NEXT: s_cselect_b32 s1, s5, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, s6
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v0
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, s0, v3
+; GFX9-NEXT: v_sub_u32_e32 v4, s1, v4
+; GFX9-NEXT: v_subrev_u32_e32 v7, s7, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v5, s6, v4
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1]
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
@@ -6012,94 +5911,86 @@ define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_sub_i32 s6, 0, s2
; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s3
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
+; GFX6-NEXT: s_sub_i32 s6, 0, s2
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s6, v0
-; GFX6-NEXT: s_mul_i32 s6, s6, s2
-; GFX6-NEXT: s_sub_i32 s0, s0, s6
-; GFX6-NEXT: s_sub_i32 s6, s0, s2
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b32 s0, s6, s0
-; GFX6-NEXT: s_sub_i32 s6, s0, s2
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b32 s0, s6, s0
-; GFX6-NEXT: s_sub_i32 s2, 0, s3
-; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v0
+; GFX6-NEXT: s_sub_i32 s6, 0, s3
+; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s3
-; GFX6-NEXT: s_sub_i32 s1, s1, s2
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s2
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s3
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s6
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: s_sub_i32 s2, 0, s7
+; GFX9-NEXT: s_sub_i32 s3, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s4, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s0, s5
-; GFX9-NEXT: s_mul_i32 s4, s4, s7
-; GFX9-NEXT: s_sub_i32 s0, s0, s4
-; GFX9-NEXT: s_sub_i32 s4, s0, s7
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: s_cselect_b32 s0, s4, s0
-; GFX9-NEXT: s_sub_i32 s4, s0, s7
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
-; GFX9-NEXT: s_cselect_b32 s0, s4, s0
-; GFX9-NEXT: s_sub_i32 s4, 0, s6
-; GFX9-NEXT: s_mul_i32 s4, s4, s8
-; GFX9-NEXT: s_mul_hi_u32 s4, s8, s4
-; GFX9-NEXT: s_add_i32 s8, s8, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s1, s8
-; GFX9-NEXT: s_mul_i32 s4, s4, s6
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: s_sub_i32 s4, s1, s6
-; GFX9-NEXT: s_cmp_ge_u32 s1, s6
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_sub_i32 s4, s1, s6
-; GFX9-NEXT: s_cmp_ge_u32 s1, s6
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s7
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s6
+; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s1, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
+; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
+; GFX9-NEXT: v_subrev_u32_e32 v4, s6, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
@@ -6217,23 +6108,20 @@ define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s4, v0
; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_xor_b32 s0, s9, s8
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s3
-; GFX6-NEXT: s_sub_i32 s0, s2, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s0, s3
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_xor_b32 s0, s9, s8
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
@@ -6242,40 +6130,38 @@ define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x
; GFX9-LABEL: sdiv_i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_i32 s3, s3, s4
; GFX9-NEXT: s_xor_b32 s3, s3, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX9-NEXT: s_sub_i32 s6, 0, s3
-; GFX9-NEXT: s_ashr_i32 s5, s2, 31
-; GFX9-NEXT: s_add_i32 s2, s2, s5
+; GFX9-NEXT: s_sub_i32 s5, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_xor_b32 s2, s2, s5
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s7, v0
-; GFX9-NEXT: s_mul_i32 s6, s6, s7
-; GFX9-NEXT: s_mul_hi_u32 s6, s7, s6
-; GFX9-NEXT: s_add_i32 s7, s7, s6
-; GFX9-NEXT: s_mul_hi_u32 s6, s2, s7
-; GFX9-NEXT: s_mul_i32 s8, s6, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s8
-; GFX9-NEXT: s_add_i32 s7, s6, 1
-; GFX9-NEXT: s_sub_i32 s8, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s6, s7, s6
-; GFX9-NEXT: s_cselect_b32 s2, s8, s2
-; GFX9-NEXT: s_add_i32 s7, s6, 1
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s7, s6
-; GFX9-NEXT: s_xor_b32 s3, s5, s4
-; GFX9-NEXT: s_xor_b32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v1, s5, v0
+; GFX9-NEXT: s_ashr_i32 s5, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s5
+; GFX9-NEXT: s_xor_b32 s2, s2, s5
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: s_xor_b32 s2, s5, s4
+; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s2, v0
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
%r = sdiv i32 %x, %shl.y
@@ -6483,70 +6369,64 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
;
; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s2
-; GFX6-NEXT: s_abs_i32 s6, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX6-NEXT: s_sub_i32 s7, 0, s6
-; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
+; GFX6-NEXT: s_lshl_b32 s6, 0x1000, s10
+; GFX6-NEXT: s_abs_i32 s7, s6
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s7
+; GFX6-NEXT: s_lshl_b32 s4, 0x1000, s11
+; GFX6-NEXT: s_abs_i32 s5, s4
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s5
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT: s_sub_i32 s10, 0, s7
+; GFX6-NEXT: s_sub_i32 s11, 0, s5
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s7, v0
-; GFX6-NEXT: s_abs_i32 s7, s0
-; GFX6-NEXT: s_xor_b32 s0, s0, s2
-; GFX6-NEXT: s_ashr_i32 s0, s0, 31
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s6
-; GFX6-NEXT: s_sub_i32 s2, s7, s2
-; GFX6-NEXT: s_sub_i32 s7, s2, s6
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s2, s6
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_cselect_b32 s2, s7, s2
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s2, s6
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_abs_i32 s2, s3
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX6-NEXT: s_sub_i32 s6, 0, s2
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_xor_b32 s3, s1, s3
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: s_abs_i32 s1, s1
-; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
-; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT: s_ashr_i32 s3, s3, 31
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: v_mul_lo_u32 v3, s6, v2
-; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_mul_hi_u32 v1, v2, v3
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: s_mul_i32 s0, s0, s2
-; GFX6-NEXT: s_sub_i32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s2
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v1
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT: v_xor_b32_e32 v1, s3, v1
-; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s3, v1
-; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_xor_b32 s6, s8, s6
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s10, v0
+; GFX6-NEXT: s_abs_i32 s10, s8
+; GFX6-NEXT: s_ashr_i32 s6, s6, 31
+; GFX6-NEXT: v_mul_lo_u32 v3, s11, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_xor_b32 s4, s9, s4
+; GFX6-NEXT: s_ashr_i32 s4, s4, 31
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v3, v0, s7
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s7, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT: s_abs_i32 s7, s9
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_mul_hi_u32 v1, s7, v1
+; GFX6-NEXT: v_xor_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_xor_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
@@ -6554,63 +6434,59 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_lshl_b32 s2, 0x1000, s2
-; GFX9-NEXT: s_abs_i32 s6, s2
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX9-NEXT: s_lshl_b32 s7, 0x1000, s3
-; GFX9-NEXT: s_abs_i32 s3, s0
-; GFX9-NEXT: s_xor_b32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s6, 0x1000, s2
+; GFX9-NEXT: s_abs_i32 s7, s6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
+; GFX9-NEXT: s_lshl_b32 s8, 0x1000, s3
+; GFX9-NEXT: s_abs_i32 s9, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s2, 0, s6
-; GFX9-NEXT: s_ashr_i32 s0, s0, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s2, s2, s8
-; GFX9-NEXT: s_mul_hi_u32 s2, s8, s2
-; GFX9-NEXT: s_add_i32 s8, s8, s2
-; GFX9-NEXT: s_mul_hi_u32 s2, s3, s8
-; GFX9-NEXT: s_mul_i32 s8, s2, s6
-; GFX9-NEXT: s_sub_i32 s3, s3, s8
-; GFX9-NEXT: s_add_i32 s9, s2, 1
-; GFX9-NEXT: s_sub_i32 s8, s3, s6
-; GFX9-NEXT: s_cmp_ge_u32 s3, s6
-; GFX9-NEXT: s_cselect_b32 s2, s9, s2
-; GFX9-NEXT: s_cselect_b32 s3, s8, s3
-; GFX9-NEXT: s_add_i32 s8, s2, 1
-; GFX9-NEXT: s_cmp_ge_u32 s3, s6
-; GFX9-NEXT: s_cselect_b32 s6, s8, s2
-; GFX9-NEXT: s_abs_i32 s8, s7
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX9-NEXT: s_xor_b32 s5, s6, s0
-; GFX9-NEXT: s_sub_i32 s6, 0, s8
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s0, s5, s0
-; GFX9-NEXT: s_xor_b32 s4, s1, s7
-; GFX9-NEXT: s_abs_i32 s1, s1
+; GFX9-NEXT: s_sub_i32 s4, 0, s7
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s6, s5, s6
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s1, s5
-; GFX9-NEXT: s_mul_i32 s6, s5, s8
-; GFX9-NEXT: s_sub_i32 s1, s1, s6
-; GFX9-NEXT: s_add_i32 s7, s5, 1
-; GFX9-NEXT: s_sub_i32 s6, s1, s8
-; GFX9-NEXT: s_cmp_ge_u32 s1, s8
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_cselect_b32 s1, s6, s1
-; GFX9-NEXT: s_add_i32 s6, s5, 1
-; GFX9-NEXT: s_cmp_ge_u32 s1, s8
-; GFX9-NEXT: s_cselect_b32 s1, s6, s5
-; GFX9-NEXT: s_xor_b32 s1, s1, s4
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_sub_i32 s5, 0, s9
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, s4, v0
+; GFX9-NEXT: s_abs_i32 s4, s0
+; GFX9-NEXT: s_xor_b32 s0, s0, s6
+; GFX9-NEXT: v_mul_lo_u32 v4, s5, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX9-NEXT: s_abs_i32 s5, s1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 31
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX9-NEXT: s_xor_b32 s1, s1, s8
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_mul_lo_u32 v3, v0, s7
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, s9
+; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
+; GFX9-NEXT: v_subrev_u32_e32 v6, s7, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_sub_u32_e32 v3, s5, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_subrev_u32_e32 v5, s9, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
+; GFX9-NEXT: v_subrev_u32_e32 v0, s0, v0
+; GFX9-NEXT: s_ashr_i32 s0, s1, 31
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1
+; GFX9-NEXT: v_subrev_u32_e32 v1, s0, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
@@ -6631,18 +6507,17 @@ define amdgpu_kernel void @srem_i32_oddk_denom(ptr addrspace(1) %out, i32 %x) {
; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX6-NEXT: v_mov_b32_e32 v0, 0xd9528441
+; GFX6-NEXT: s_mov_b32 s2, 0x12d8fb
; GFX6-NEXT: s_mov_b32 s3, 0xf000
-; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mul_hi_i32 v0, s6, v0
-; GFX6-NEXT: v_readfirstlane_b32 s4, v0
-; GFX6-NEXT: s_add_i32 s4, s4, s6
-; GFX6-NEXT: s_lshr_b32 s5, s4, 31
-; GFX6-NEXT: s_ashr_i32 s4, s4, 20
-; GFX6-NEXT: s_add_i32 s4, s4, s5
-; GFX6-NEXT: s_mul_i32 s4, s4, 0x12d8fb
-; GFX6-NEXT: s_sub_i32 s4, s6, s4
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s6, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v0, 20, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
@@ -6737,54 +6612,50 @@ define amdgpu_kernel void @srem_i32_pow2_shl_denom(ptr addrspace(1) %out, i32 %x
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
-; GFX6-NEXT: v_readfirstlane_b32 s7, v0
-; GFX6-NEXT: s_mul_i32 s7, s7, s4
-; GFX6-NEXT: s_sub_i32 s6, s6, s7
-; GFX6-NEXT: s_sub_i32 s7, s6, s4
-; GFX6-NEXT: s_cmp_ge_u32 s6, s4
-; GFX6-NEXT: s_cselect_b32 s6, s7, s6
-; GFX6-NEXT: s_sub_i32 s7, s6, s4
-; GFX6-NEXT: s_cmp_ge_u32 s6, s4
-; GFX6-NEXT: s_cselect_b32 s4, s7, s6
-; GFX6-NEXT: s_xor_b32 s4, s4, s5
-; GFX6-NEXT: s_sub_i32 s4, s4, s5
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s4
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s4, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s5, v0
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: srem_i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_i32 s3, s3, s4
; GFX9-NEXT: s_xor_b32 s3, s3, s4
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX9-NEXT: s_sub_i32 s5, 0, s3
-; GFX9-NEXT: s_ashr_i32 s4, s2, 31
-; GFX9-NEXT: s_add_i32 s2, s2, s4
+; GFX9-NEXT: s_sub_i32 s4, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_xor_b32 s2, s2, s4
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s6
-; GFX9-NEXT: s_mul_i32 s5, s5, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: s_ashr_i32 s4, s2, 31
+; GFX9-NEXT: s_add_i32 s2, s2, s4
; GFX9-NEXT: s_xor_b32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3
+; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v2, s3, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v0, s4, v0
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%shl.y = shl i32 4096, %y
@@ -6937,118 +6808,110 @@ define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b32 s2, 0x1000, s2
; GFX6-NEXT: s_abs_i32 s2, s2
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT: s_sub_i32 s6, 0, s2
; GFX6-NEXT: s_lshl_b32 s3, 0x1000, s3
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0
-; GFX6-NEXT: s_abs_i32 s6, s0
-; GFX6-NEXT: s_ashr_i32 s0, s0, 31
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0
-; GFX6-NEXT: v_readfirstlane_b32 s7, v0
-; GFX6-NEXT: s_mul_i32 s7, s7, s2
-; GFX6-NEXT: s_sub_i32 s6, s6, s7
-; GFX6-NEXT: s_sub_i32 s7, s6, s2
-; GFX6-NEXT: s_cmp_ge_u32 s6, s2
-; GFX6-NEXT: s_cselect_b32 s6, s7, s6
-; GFX6-NEXT: s_sub_i32 s7, s6, s2
-; GFX6-NEXT: s_cmp_ge_u32 s6, s2
-; GFX6-NEXT: s_cselect_b32 s2, s7, s6
; GFX6-NEXT: s_abs_i32 s3, s3
-; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX6-NEXT: s_sub_i32 s6, 0, s3
-; GFX6-NEXT: s_abs_i32 s8, s1
-; GFX6-NEXT: s_xor_b32 s2, s2, s0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: s_sub_i32 s0, s2, s0
-; GFX6-NEXT: s_ashr_i32 s1, s1, 31
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_sub_i32 s8, 0, s2
+; GFX6-NEXT: s_sub_i32 s9, 0, s3
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0
-; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s8, v0
+; GFX6-NEXT: s_abs_i32 s8, s0
+; GFX6-NEXT: s_ashr_i32 s0, s0, 31
+; GFX6-NEXT: v_mul_lo_u32 v3, s9, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_abs_i32 s9, s1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s3
-; GFX6-NEXT: s_sub_i32 s2, s8, s2
-; GFX6-NEXT: s_sub_i32 s8, s2, s3
-; GFX6-NEXT: s_cmp_ge_u32 s2, s3
-; GFX6-NEXT: s_cselect_b32 s2, s8, s2
-; GFX6-NEXT: s_sub_i32 s8, s2, s3
-; GFX6-NEXT: s_cmp_ge_u32 s2, s3
-; GFX6-NEXT: s_cselect_b32 s2, s8, s2
-; GFX6-NEXT: s_xor_b32 s2, s2, s1
-; GFX6-NEXT: s_sub_i32 s1, s2, s1
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: s_ashr_i32 s0, s1, 31
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_xor_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s2, 0x1000, s2
-; GFX9-NEXT: s_abs_i32 s2, s2
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX9-NEXT: s_sub_i32 s7, 0, s2
-; GFX9-NEXT: s_ashr_i32 s6, s0, 31
-; GFX9-NEXT: s_abs_i32 s0, s0
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_lshl_b32 s3, 0x1000, s3
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s8
-; GFX9-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX9-NEXT: s_add_i32 s8, s8, s7
-; GFX9-NEXT: s_mul_hi_u32 s7, s0, s8
-; GFX9-NEXT: s_mul_i32 s7, s7, s2
-; GFX9-NEXT: s_sub_i32 s0, s0, s7
-; GFX9-NEXT: s_sub_i32 s7, s0, s2
-; GFX9-NEXT: s_cmp_ge_u32 s0, s2
-; GFX9-NEXT: s_cselect_b32 s0, s7, s0
-; GFX9-NEXT: s_sub_i32 s7, s0, s2
-; GFX9-NEXT: s_cmp_ge_u32 s0, s2
-; GFX9-NEXT: s_cselect_b32 s0, s7, s0
+; GFX9-NEXT: s_abs_i32 s6, s2
; GFX9-NEXT: s_abs_i32 s7, s3
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
-; GFX9-NEXT: s_xor_b32 s0, s0, s6
-; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX9-NEXT: s_sub_i32 s5, 0, s7
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: s_sub_i32 s2, 0, s6
+; GFX9-NEXT: s_sub_i32 s3, 0, s7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s0, s0, s6
-; GFX9-NEXT: s_ashr_i32 s4, s1, 31
-; GFX9-NEXT: s_abs_i32 s1, s1
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX9-NEXT: s_abs_i32 s8, s0
+; GFX9-NEXT: s_abs_i32 s9, s1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s6, s6, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s1, s6
-; GFX9-NEXT: s_mul_i32 s5, s5, s7
-; GFX9-NEXT: s_sub_i32 s1, s1, s5
-; GFX9-NEXT: s_sub_i32 s5, s1, s7
-; GFX9-NEXT: s_cmp_ge_u32 s1, s7
-; GFX9-NEXT: s_cselect_b32 s1, s5, s1
-; GFX9-NEXT: s_sub_i32 s5, s1, s7
-; GFX9-NEXT: s_cmp_ge_u32 s1, s7
-; GFX9-NEXT: s_cselect_b32 s1, s5, s1
-; GFX9-NEXT: s_xor_b32 s1, s1, s4
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: s_ashr_i32 s0, s0, 31
+; GFX9-NEXT: s_ashr_i32 s1, s1, 31
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s3, v1
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, s7
+; GFX9-NEXT: v_sub_u32_e32 v0, s8, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s9, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s6, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX9-NEXT: v_subrev_u32_e32 v4, s7, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s6, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s7, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
+; GFX9-NEXT: v_subrev_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_subrev_u32_e32 v1, s1, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
@@ -7940,139 +7803,121 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
; GFX9-NEXT: s_sub_u32 s0, 0, s6
; GFX9-NEXT: s_subb_u32 s1, 0, s7
+; GFX9-NEXT: s_ashr_i32 s4, s11, 31
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
-; GFX9-NEXT: v_rcp_f32_e32 v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
-; GFX9-NEXT: v_trunc_f32_e32 v2, v2
-; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s4, v2
-; GFX9-NEXT: v_readfirstlane_b32 s5, v1
-; GFX9-NEXT: s_mul_i32 s12, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s14, s0, s5
-; GFX9-NEXT: s_mul_i32 s13, s1, s5
-; GFX9-NEXT: s_add_i32 s12, s14, s12
-; GFX9-NEXT: s_mul_i32 s15, s0, s5
-; GFX9-NEXT: s_add_i32 s12, s12, s13
-; GFX9-NEXT: s_mul_hi_u32 s14, s5, s15
-; GFX9-NEXT: s_mul_hi_u32 s13, s5, s12
-; GFX9-NEXT: s_mul_i32 s5, s5, s12
-; GFX9-NEXT: s_add_u32 s5, s14, s5
-; GFX9-NEXT: s_addc_u32 s13, 0, s13
-; GFX9-NEXT: s_mul_hi_u32 s16, s4, s15
-; GFX9-NEXT: s_mul_i32 s15, s4, s15
-; GFX9-NEXT: s_add_u32 s5, s5, s15
-; GFX9-NEXT: s_mul_hi_u32 s14, s4, s12
-; GFX9-NEXT: s_addc_u32 s5, s13, s16
-; GFX9-NEXT: s_addc_u32 s13, s14, 0
-; GFX9-NEXT: s_mul_i32 s12, s4, s12
-; GFX9-NEXT: s_add_u32 s5, s5, s12
-; GFX9-NEXT: s_addc_u32 s12, 0, s13
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s5, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s4, s12
-; GFX9-NEXT: v_readfirstlane_b32 s12, v1
-; GFX9-NEXT: s_mul_i32 s5, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12
-; GFX9-NEXT: s_add_i32 s5, s13, s5
-; GFX9-NEXT: s_mul_i32 s1, s1, s12
-; GFX9-NEXT: s_add_i32 s5, s5, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s12
-; GFX9-NEXT: s_mul_hi_u32 s13, s4, s0
-; GFX9-NEXT: s_mul_i32 s14, s4, s0
-; GFX9-NEXT: s_mul_i32 s16, s12, s5
-; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0
-; GFX9-NEXT: s_mul_hi_u32 s15, s12, s5
-; GFX9-NEXT: s_add_u32 s0, s0, s16
-; GFX9-NEXT: s_addc_u32 s12, 0, s15
-; GFX9-NEXT: s_add_u32 s0, s0, s14
-; GFX9-NEXT: s_mul_hi_u32 s1, s4, s5
-; GFX9-NEXT: s_addc_u32 s0, s12, s13
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s5, s4, s5
-; GFX9-NEXT: s_add_u32 s0, s0, s5
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s12, s4, s1
-; GFX9-NEXT: s_ashr_i32 s4, s11, 31
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: s_add_u32 s0, s10, s4
-; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s1, s11, s4
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[4:5]
-; GFX9-NEXT: v_readfirstlane_b32 s13, v1
-; GFX9-NEXT: s_mul_i32 s1, s10, s12
-; GFX9-NEXT: s_mul_hi_u32 s14, s10, s13
-; GFX9-NEXT: s_mul_hi_u32 s0, s10, s12
-; GFX9-NEXT: s_add_u32 s1, s14, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s15, s11, s13
-; GFX9-NEXT: s_mul_i32 s13, s11, s13
-; GFX9-NEXT: s_add_u32 s1, s1, s13
-; GFX9-NEXT: s_mul_hi_u32 s14, s11, s12
-; GFX9-NEXT: s_addc_u32 s0, s0, s15
-; GFX9-NEXT: s_addc_u32 s1, s14, 0
-; GFX9-NEXT: s_mul_i32 s12, s11, s12
-; GFX9-NEXT: s_add_u32 s12, s0, s12
-; GFX9-NEXT: s_addc_u32 s13, 0, s1
-; GFX9-NEXT: s_mul_i32 s0, s6, s13
-; GFX9-NEXT: s_mul_hi_u32 s1, s6, s12
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_mul_i32 s1, s7, s12
-; GFX9-NEXT: s_add_i32 s14, s0, s1
-; GFX9-NEXT: s_mul_i32 s1, s6, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
-; GFX9-NEXT: s_sub_i32 s0, s11, s14
-; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s10, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s10, s0, s7
-; GFX9-NEXT: v_subrev_co_u32_e64 v2, s[0:1], s6, v1
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s10, s10, 0
-; GFX9-NEXT: s_cmp_ge_u32 s10, s7
-; GFX9-NEXT: s_cselect_b32 s15, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v2
-; GFX9-NEXT: s_cmp_eq_u32 s10, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v3, s15
-; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1]
-; GFX9-NEXT: s_add_u32 s0, s12, 1
-; GFX9-NEXT: s_addc_u32 s10, s13, 0
-; GFX9-NEXT: s_add_u32 s1, s12, 2
-; GFX9-NEXT: s_addc_u32 s15, s13, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_mov_b32_e32 v4, s15
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s11, s14
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
-; GFX9-NEXT: s_cmp_eq_u32 s0, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v4, s13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s11, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, s7
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, s6, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, s11, v2
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s10, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v6, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s6, v3
+; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 1, v0
+; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v0
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v1, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v7, s11
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s7, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3]
-; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2
-; GFX9-NEXT: v_xor_b32_e32 v3, s1, v1
-; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v4, vcc
-; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[8:9]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
+; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = sdiv i64 %x, %shl.y
@@ -8533,291 +8378,255 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s12
-; GFX9-NEXT: s_lshl_b64 s[6:7], 0x1000, s14
+; GFX9-NEXT: s_lshl_b64 s[14:15], 0x1000, s14
; GFX9-NEXT: s_ashr_i32 s12, s1, 31
; GFX9-NEXT: s_add_u32 s0, s0, s12
; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_addc_u32 s1, s1, s12
-; GFX9-NEXT: s_xor_b64 s[14:15], s[0:1], s[12:13]
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15
-; GFX9-NEXT: s_sub_u32 s0, 0, s14
-; GFX9-NEXT: s_subb_u32 s1, 0, s15
+; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GFX9-NEXT: s_sub_u32 s0, 0, s6
+; GFX9-NEXT: s_subb_u32 s1, 0, s7
+; GFX9-NEXT: s_ashr_i32 s16, s9, 31
; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s17, s16
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s16, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s18, s0, s5
-; GFX9-NEXT: s_mul_i32 s17, s1, s5
-; GFX9-NEXT: s_add_i32 s16, s18, s16
-; GFX9-NEXT: s_mul_i32 s19, s0, s5
-; GFX9-NEXT: s_add_i32 s16, s16, s17
-; GFX9-NEXT: s_mul_hi_u32 s17, s5, s16
-; GFX9-NEXT: s_mul_i32 s18, s5, s16
-; GFX9-NEXT: s_mul_hi_u32 s5, s5, s19
-; GFX9-NEXT: s_add_u32 s5, s5, s18
-; GFX9-NEXT: s_addc_u32 s17, 0, s17
-; GFX9-NEXT: s_mul_hi_u32 s20, s4, s19
-; GFX9-NEXT: s_mul_i32 s19, s4, s19
-; GFX9-NEXT: s_add_u32 s5, s5, s19
-; GFX9-NEXT: s_mul_hi_u32 s18, s4, s16
-; GFX9-NEXT: s_addc_u32 s5, s17, s20
-; GFX9-NEXT: s_addc_u32 s17, s18, 0
-; GFX9-NEXT: s_mul_i32 s16, s4, s16
-; GFX9-NEXT: s_add_u32 s5, s5, s16
-; GFX9-NEXT: s_addc_u32 s16, 0, s17
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s5, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s4, s4, s16
-; GFX9-NEXT: v_readfirstlane_b32 s16, v0
-; GFX9-NEXT: s_mul_i32 s5, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s17, s0, s16
-; GFX9-NEXT: s_add_i32 s5, s17, s5
-; GFX9-NEXT: s_mul_i32 s1, s1, s16
-; GFX9-NEXT: s_add_i32 s5, s5, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s16
-; GFX9-NEXT: s_mul_hi_u32 s17, s4, s0
-; GFX9-NEXT: s_mul_i32 s18, s4, s0
-; GFX9-NEXT: s_mul_i32 s20, s16, s5
-; GFX9-NEXT: s_mul_hi_u32 s0, s16, s0
-; GFX9-NEXT: s_mul_hi_u32 s19, s16, s5
-; GFX9-NEXT: s_add_u32 s0, s0, s20
-; GFX9-NEXT: s_addc_u32 s16, 0, s19
-; GFX9-NEXT: s_add_u32 s0, s0, s18
-; GFX9-NEXT: s_mul_hi_u32 s1, s4, s5
-; GFX9-NEXT: s_addc_u32 s0, s16, s17
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s5, s4, s5
-; GFX9-NEXT: s_add_u32 s0, s0, s5
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s16, s4, s1
-; GFX9-NEXT: s_ashr_i32 s4, s9, 31
-; GFX9-NEXT: s_add_u32 s0, s8, s4
-; GFX9-NEXT: s_mov_b32 s5, s4
-; GFX9-NEXT: s_addc_u32 s1, s9, s4
-; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[4:5]
-; GFX9-NEXT: v_readfirstlane_b32 s17, v0
-; GFX9-NEXT: s_mul_i32 s1, s8, s16
-; GFX9-NEXT: s_mul_hi_u32 s18, s8, s17
-; GFX9-NEXT: s_mul_hi_u32 s0, s8, s16
-; GFX9-NEXT: s_add_u32 s1, s18, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s19, s9, s17
-; GFX9-NEXT: s_mul_i32 s17, s9, s17
-; GFX9-NEXT: s_add_u32 s1, s1, s17
-; GFX9-NEXT: s_mul_hi_u32 s18, s9, s16
-; GFX9-NEXT: s_addc_u32 s0, s0, s19
-; GFX9-NEXT: s_addc_u32 s1, s18, 0
-; GFX9-NEXT: s_mul_i32 s16, s9, s16
-; GFX9-NEXT: s_add_u32 s16, s0, s16
-; GFX9-NEXT: s_addc_u32 s17, 0, s1
-; GFX9-NEXT: s_mul_i32 s0, s14, s17
-; GFX9-NEXT: s_mul_hi_u32 s1, s14, s16
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_mul_i32 s1, s15, s16
-; GFX9-NEXT: s_add_i32 s18, s0, s1
-; GFX9-NEXT: s_mul_i32 s1, s14, s16
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: s_sub_i32 s0, s9, s18
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s8, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s8, s0, s15
-; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s14, v0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s8, s8, 0
-; GFX9-NEXT: s_cmp_ge_u32 s8, s15
-; GFX9-NEXT: s_cselect_b32 s19, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v1
-; GFX9-NEXT: s_cmp_eq_u32 s8, s15
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
-; GFX9-NEXT: s_add_u32 s0, s16, 1
-; GFX9-NEXT: s_addc_u32 s8, s17, 0
-; GFX9-NEXT: s_add_u32 s1, s16, 2
-; GFX9-NEXT: s_addc_u32 s19, s17, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s8
-; GFX9-NEXT: v_mov_b32_e32 v3, s19
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s9, s18
-; GFX9-NEXT: s_cmp_ge_u32 s0, s15
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v0
-; GFX9-NEXT: s_cmp_eq_u32 s0, s15
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[12:13]
-; GFX9-NEXT: s_ashr_i32 s4, s7, 31
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; GFX9-NEXT: s_add_u32 s6, s6, s4
-; GFX9-NEXT: v_mov_b32_e32 v3, s17
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
+; GFX9-NEXT: s_add_u32 s0, s8, s16
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_addc_u32 s1, s9, s16
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[16:17]
+; GFX9-NEXT: v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s9, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s9, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX9-NEXT: v_mov_b32_e32 v6, s7
+; GFX9-NEXT: s_ashr_i32 s4, s15, 31
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v3, s6, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s7, v1
; GFX9-NEXT: s_mov_b32 s5, s4
-; GFX9-NEXT: s_addc_u32 s7, s7, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, s16
-; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s6
-; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s7
-; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1
-; GFX9-NEXT: v_xor_b32_e32 v5, s1, v0
-; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v1
-; GFX9-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
-; GFX9-NEXT: v_rcp_f32_e32 v2, v2
-; GFX9-NEXT: s_sub_u32 s0, 0, s6
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: s_subb_u32 s1, 0, s7
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; GFX9-NEXT: v_trunc_f32_e32 v3, v3
-; GFX9-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
+; GFX9-NEXT: v_sub_u32_e32 v5, s9, v3
+; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s8, v4
+; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s6, v4
+; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], 1, v1
+; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 2, v1
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v2, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1]
+; GFX9-NEXT: s_xor_b64 s[0:1], s[16:17], s[12:13]
+; GFX9-NEXT: s_add_u32 s8, s14, s4
+; GFX9-NEXT: v_mov_b32_e32 v7, s9
+; GFX9-NEXT: s_addc_u32 s9, s15, s4
+; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5]
+; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s8
+; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s9
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_mac_f32_e32 v7, 0x4f800000, v8
+; GFX9-NEXT: v_rcp_f32_e32 v7, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v7
+; GFX9-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GFX9-NEXT: v_trunc_f32_e32 v4, v4
+; GFX9-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v6, vcc
-; GFX9-NEXT: v_readfirstlane_b32 s8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s13, v3
-; GFX9-NEXT: s_mul_hi_u32 s12, s0, s8
-; GFX9-NEXT: s_mul_i32 s14, s0, s13
-; GFX9-NEXT: s_mul_i32 s9, s1, s8
-; GFX9-NEXT: s_add_i32 s12, s12, s14
-; GFX9-NEXT: s_add_i32 s12, s12, s9
-; GFX9-NEXT: s_mul_i32 s15, s0, s8
-; GFX9-NEXT: s_mul_hi_u32 s9, s8, s12
-; GFX9-NEXT: s_mul_i32 s14, s8, s12
-; GFX9-NEXT: s_mul_hi_u32 s8, s8, s15
-; GFX9-NEXT: s_add_u32 s8, s8, s14
-; GFX9-NEXT: s_addc_u32 s9, 0, s9
-; GFX9-NEXT: s_mul_hi_u32 s16, s13, s15
-; GFX9-NEXT: s_mul_i32 s15, s13, s15
-; GFX9-NEXT: s_add_u32 s8, s8, s15
-; GFX9-NEXT: s_mul_hi_u32 s14, s13, s12
-; GFX9-NEXT: s_addc_u32 s8, s9, s16
-; GFX9-NEXT: s_addc_u32 s9, s14, 0
-; GFX9-NEXT: s_mul_i32 s12, s13, s12
-; GFX9-NEXT: s_add_u32 s8, s8, s12
-; GFX9-NEXT: s_addc_u32 s9, 0, s9
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s8, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s8, s13, s9
-; GFX9-NEXT: v_readfirstlane_b32 s12, v2
-; GFX9-NEXT: s_mul_i32 s9, s0, s8
-; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12
-; GFX9-NEXT: s_add_i32 s9, s13, s9
-; GFX9-NEXT: s_mul_i32 s1, s1, s12
-; GFX9-NEXT: s_add_i32 s9, s9, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s12
-; GFX9-NEXT: s_mul_hi_u32 s13, s8, s0
-; GFX9-NEXT: s_mul_i32 s14, s8, s0
-; GFX9-NEXT: s_mul_i32 s16, s12, s9
-; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0
-; GFX9-NEXT: s_mul_hi_u32 s15, s12, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s16
-; GFX9-NEXT: s_addc_u32 s12, 0, s15
-; GFX9-NEXT: s_add_u32 s0, s0, s14
-; GFX9-NEXT: s_mul_hi_u32 s1, s8, s9
-; GFX9-NEXT: s_addc_u32 s0, s12, s13
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s9, s8, s9
-; GFX9-NEXT: s_add_u32 s0, s0, s9
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s12, s8, s1
-; GFX9-NEXT: s_ashr_i32 s8, s11, 31
-; GFX9-NEXT: s_add_u32 s0, s10, s8
-; GFX9-NEXT: s_mov_b32 s9, s8
-; GFX9-NEXT: s_addc_u32 s1, s11, s8
-; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9]
-; GFX9-NEXT: v_readfirstlane_b32 s13, v2
-; GFX9-NEXT: s_mul_i32 s1, s10, s12
-; GFX9-NEXT: s_mul_hi_u32 s14, s10, s13
-; GFX9-NEXT: s_mul_hi_u32 s0, s10, s12
-; GFX9-NEXT: s_add_u32 s1, s14, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s15, s11, s13
-; GFX9-NEXT: s_mul_i32 s13, s11, s13
-; GFX9-NEXT: s_add_u32 s1, s1, s13
-; GFX9-NEXT: s_mul_hi_u32 s14, s11, s12
-; GFX9-NEXT: s_addc_u32 s0, s0, s15
-; GFX9-NEXT: s_addc_u32 s1, s14, 0
-; GFX9-NEXT: s_mul_i32 s12, s11, s12
-; GFX9-NEXT: s_add_u32 s12, s0, s12
-; GFX9-NEXT: s_addc_u32 s13, 0, s1
-; GFX9-NEXT: s_mul_i32 s0, s6, s13
-; GFX9-NEXT: s_mul_hi_u32 s1, s6, s12
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_mul_i32 s1, s7, s12
-; GFX9-NEXT: s_add_i32 s14, s0, s1
-; GFX9-NEXT: s_mul_i32 s1, s6, s12
-; GFX9-NEXT: v_mov_b32_e32 v2, s1
-; GFX9-NEXT: s_sub_i32 s0, s11, s14
-; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s10, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s10, s0, s7
-; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s6, v2
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s10, s10, 0
-; GFX9-NEXT: s_cmp_ge_u32 s10, s7
-; GFX9-NEXT: s_cselect_b32 s15, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3
-; GFX9-NEXT: s_cmp_eq_u32 s10, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v5, s15
-; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[0:1]
-; GFX9-NEXT: s_add_u32 s0, s12, 1
-; GFX9-NEXT: s_addc_u32 s10, s13, 0
-; GFX9-NEXT: s_add_u32 s1, s12, 2
-; GFX9-NEXT: s_addc_u32 s15, s13, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, s0
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v5, s10
-; GFX9-NEXT: v_mov_b32_e32 v6, s15
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s11, s14
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v2
-; GFX9-NEXT: s_cmp_eq_u32 s0, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v6, s13
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, s12
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], s[4:5]
+; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GFX9-NEXT: s_sub_u32 s6, 0, s8
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX9-NEXT: s_subb_u32 s7, 0, s9
+; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, s6, v4
+; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s6, v3
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v8, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v10, v4, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v4, v6
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, v4, v5
+; GFX9-NEXT: v_mul_hi_u32 v5, v4, v5
+; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1
+; GFX9-NEXT: v_xor_b32_e32 v2, s1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, s7, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, s6, v3
+; GFX9-NEXT: s_ashr_i32 s6, s11, 31
+; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v7
+; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8
+; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT: s_add_u32 s10, s10, s6
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: s_mov_b32 s7, s6
+; GFX9-NEXT: s_addc_u32 s11, s11, s6
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
+; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[6:7]
+; GFX9-NEXT: v_mul_lo_u32 v5, s10, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, s10, v3
+; GFX9-NEXT: v_mul_hi_u32 v8, s10, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, s11, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v4
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3
+; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX9-NEXT: v_mov_b32_e32 v7, s1
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v9, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s8, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, s8, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, s9, v3
+; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v1
+; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
+; GFX9-NEXT: v_mul_lo_u32 v6, s8, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v8
+; GFX9-NEXT: v_sub_u32_e32 v7, s11, v5
+; GFX9-NEXT: v_mov_b32_e32 v8, s9
+; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s10, v6
+; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s8, v6
+; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[0:1], 0, v7, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v8, s[0:1], 1, v3
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], 2, v3
+; GFX9-NEXT: v_addc_co_u32_e64 v11, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, v11, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v9, s11
+; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3
-; GFX9-NEXT: v_xor_b32_e32 v5, s1, v2
-; GFX9-NEXT: v_mov_b32_e32 v6, s1
-; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v3
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v6, vcc
-; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX9-NEXT: v_xor_b32_e32 v4, s1, v4
+; GFX9-NEXT: v_mov_b32_e32 v5, s1
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s0, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
+; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[2:3]
; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y
@@ -9129,136 +8938,119 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7
; GFX9-NEXT: s_sub_u32 s0, 0, s6
; GFX9-NEXT: s_subb_u32 s1, 0, s7
+; GFX9-NEXT: s_ashr_i32 s4, s11, 31
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
-; GFX9-NEXT: v_rcp_f32_e32 v1, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
-; GFX9-NEXT: v_trunc_f32_e32 v2, v2
-; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s2, v2
-; GFX9-NEXT: v_readfirstlane_b32 s3, v1
-; GFX9-NEXT: s_mul_i32 s4, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s12, s0, s3
-; GFX9-NEXT: s_mul_i32 s5, s1, s3
-; GFX9-NEXT: s_add_i32 s4, s12, s4
-; GFX9-NEXT: s_mul_i32 s13, s0, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s12, s3, s13
-; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4
-; GFX9-NEXT: s_mul_i32 s3, s3, s4
-; GFX9-NEXT: s_add_u32 s3, s12, s3
-; GFX9-NEXT: s_addc_u32 s5, 0, s5
-; GFX9-NEXT: s_mul_hi_u32 s14, s2, s13
-; GFX9-NEXT: s_mul_i32 s13, s2, s13
-; GFX9-NEXT: s_add_u32 s3, s3, s13
-; GFX9-NEXT: s_mul_hi_u32 s12, s2, s4
-; GFX9-NEXT: s_addc_u32 s3, s5, s14
-; GFX9-NEXT: s_addc_u32 s5, s12, 0
-; GFX9-NEXT: s_mul_i32 s4, s2, s4
-; GFX9-NEXT: s_add_u32 s3, s3, s4
-; GFX9-NEXT: s_addc_u32 s4, 0, s5
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s3, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s2, s4
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: s_mul_i32 s3, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s5, s0, s4
-; GFX9-NEXT: s_add_i32 s3, s5, s3
-; GFX9-NEXT: s_mul_i32 s1, s1, s4
-; GFX9-NEXT: s_add_i32 s3, s3, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s0
-; GFX9-NEXT: s_mul_i32 s12, s2, s0
-; GFX9-NEXT: s_mul_i32 s14, s4, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s4, s0
-; GFX9-NEXT: s_mul_hi_u32 s13, s4, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s14
-; GFX9-NEXT: s_addc_u32 s4, 0, s13
-; GFX9-NEXT: s_add_u32 s0, s0, s12
-; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3
-; GFX9-NEXT: s_addc_u32 s0, s4, s5
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s3, s2, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s3
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s2, s1
-; GFX9-NEXT: s_ashr_i32 s4, s11, 31
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: s_add_u32 s0, s10, s4
-; GFX9-NEXT: s_mov_b32 s5, s4
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s1, s11, s4
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[4:5]
-; GFX9-NEXT: v_readfirstlane_b32 s3, v1
-; GFX9-NEXT: s_mul_i32 s1, s10, s2
-; GFX9-NEXT: s_mul_hi_u32 s5, s10, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s10, s2
-; GFX9-NEXT: s_add_u32 s1, s5, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s12, s11, s3
-; GFX9-NEXT: s_mul_i32 s3, s11, s3
-; GFX9-NEXT: s_add_u32 s1, s1, s3
-; GFX9-NEXT: s_mul_hi_u32 s5, s11, s2
-; GFX9-NEXT: s_addc_u32 s0, s0, s12
-; GFX9-NEXT: s_addc_u32 s1, s5, 0
-; GFX9-NEXT: s_mul_i32 s2, s11, s2
-; GFX9-NEXT: s_add_u32 s0, s0, s2
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: s_mul_i32 s1, s6, s1
-; GFX9-NEXT: s_mul_hi_u32 s2, s6, s0
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: s_mul_i32 s2, s7, s0
-; GFX9-NEXT: s_mul_i32 s0, s6, s0
-; GFX9-NEXT: s_add_i32 s5, s1, s2
-; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: s_sub_i32 s1, s11, s5
-; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s10, v1
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s10, s1, s7
-; GFX9-NEXT: v_subrev_co_u32_e64 v2, s[0:1], s6, v1
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s12, s10, 0
-; GFX9-NEXT: s_cmp_ge_u32 s12, s7
-; GFX9-NEXT: s_cselect_b32 s13, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v2
-; GFX9-NEXT: s_cmp_eq_u32 s12, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v4, s13
-; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3]
-; GFX9-NEXT: s_subb_u32 s2, s10, s7
-; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s6, v2
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s2, s2, 0
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_mov_b32_e32 v4, s2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s11, s5
-; GFX9-NEXT: s_cmp_ge_u32 s0, s7
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1
-; GFX9-NEXT: s_cmp_eq_u32 s0, s7
-; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s0
+; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s11, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, s6, v1
+; GFX9-NEXT: v_mul_hi_u32 v2, s6, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, s7, v0
+; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v2, s11, v1
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s10, v0
+; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s6, v0
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s7, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v5
+; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s7, v6
+; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s6, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v5, s11
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
-; GFX9-NEXT: v_xor_b32_e32 v2, s4, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
-; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s4, v1
-; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v3, vcc
-; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[8:9]
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm
%shl.y = shl i64 4096, %y
%r = srem i64 %x, %shl.y
@@ -9606,285 +9398,251 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s12
-; GFX9-NEXT: s_lshl_b64 s[14:15], 0x1000, s14
+; GFX9-NEXT: s_lshl_b64 s[16:17], 0x1000, s14
; GFX9-NEXT: s_ashr_i32 s2, s1, 31
; GFX9-NEXT: s_add_u32 s0, s0, s2
; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_addc_u32 s1, s1, s2
-; GFX9-NEXT: s_xor_b64 s[12:13], s[0:1], s[2:3]
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GFX9-NEXT: s_sub_u32 s0, 0, s12
-; GFX9-NEXT: s_subb_u32 s1, 0, s13
+; GFX9-NEXT: s_xor_b64 s[14:15], s[0:1], s[2:3]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15
+; GFX9-NEXT: s_sub_u32 s0, 0, s14
+; GFX9-NEXT: s_subb_u32 s1, 0, s15
+; GFX9-NEXT: s_ashr_i32 s12, s9, 31
; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: s_mul_i32 s4, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s16, s0, s3
-; GFX9-NEXT: s_mul_i32 s5, s1, s3
-; GFX9-NEXT: s_add_i32 s4, s16, s4
-; GFX9-NEXT: s_mul_i32 s17, s0, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4
-; GFX9-NEXT: s_mul_i32 s16, s3, s4
-; GFX9-NEXT: s_mul_hi_u32 s3, s3, s17
-; GFX9-NEXT: s_add_u32 s3, s3, s16
-; GFX9-NEXT: s_addc_u32 s5, 0, s5
-; GFX9-NEXT: s_mul_hi_u32 s18, s2, s17
-; GFX9-NEXT: s_mul_i32 s17, s2, s17
-; GFX9-NEXT: s_add_u32 s3, s3, s17
-; GFX9-NEXT: s_mul_hi_u32 s16, s2, s4
-; GFX9-NEXT: s_addc_u32 s3, s5, s18
-; GFX9-NEXT: s_addc_u32 s5, s16, 0
-; GFX9-NEXT: s_mul_i32 s4, s2, s4
-; GFX9-NEXT: s_add_u32 s3, s3, s4
-; GFX9-NEXT: s_addc_u32 s4, 0, s5
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s2, s4
-; GFX9-NEXT: v_readfirstlane_b32 s4, v0
-; GFX9-NEXT: s_mul_i32 s3, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s5, s0, s4
-; GFX9-NEXT: s_add_i32 s3, s5, s3
-; GFX9-NEXT: s_mul_i32 s1, s1, s4
-; GFX9-NEXT: s_add_i32 s3, s3, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s4
-; GFX9-NEXT: s_mul_hi_u32 s5, s2, s0
-; GFX9-NEXT: s_mul_i32 s16, s2, s0
-; GFX9-NEXT: s_mul_i32 s18, s4, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s4, s0
-; GFX9-NEXT: s_mul_hi_u32 s17, s4, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s18
-; GFX9-NEXT: s_addc_u32 s4, 0, s17
-; GFX9-NEXT: s_add_u32 s0, s0, s16
-; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3
-; GFX9-NEXT: s_addc_u32 s0, s4, s5
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s3, s2, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s3
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s2, s1
-; GFX9-NEXT: s_ashr_i32 s16, s9, 31
-; GFX9-NEXT: s_add_u32 s0, s8, s16
-; GFX9-NEXT: s_mov_b32 s17, s16
-; GFX9-NEXT: s_addc_u32 s1, s9, s16
-; GFX9-NEXT: s_xor_b64 s[4:5], s[0:1], s[16:17]
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: s_mul_i32 s1, s4, s2
-; GFX9-NEXT: s_mul_hi_u32 s8, s4, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s4, s2
-; GFX9-NEXT: s_add_u32 s1, s8, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s9, s5, s3
-; GFX9-NEXT: s_mul_i32 s3, s5, s3
-; GFX9-NEXT: s_add_u32 s1, s1, s3
-; GFX9-NEXT: s_mul_hi_u32 s8, s5, s2
-; GFX9-NEXT: s_addc_u32 s0, s0, s9
-; GFX9-NEXT: s_addc_u32 s1, s8, 0
-; GFX9-NEXT: s_mul_i32 s2, s5, s2
-; GFX9-NEXT: s_add_u32 s0, s0, s2
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: s_mul_i32 s1, s12, s1
-; GFX9-NEXT: s_mul_hi_u32 s2, s12, s0
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: s_mul_i32 s2, s13, s0
-; GFX9-NEXT: s_mul_i32 s0, s12, s0
-; GFX9-NEXT: s_add_i32 s8, s1, s2
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: s_sub_i32 s1, s5, s8
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s4, s1, s13
-; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s12, v0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s9, s4, 0
-; GFX9-NEXT: s_cmp_ge_u32 s9, s13
-; GFX9-NEXT: s_cselect_b32 s17, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v1
-; GFX9-NEXT: s_cmp_eq_u32 s9, s13
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v3, s17
-; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3]
-; GFX9-NEXT: s_subb_u32 s2, s4, s13
-; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v1
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s2, s2, 0
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s9
-; GFX9-NEXT: v_mov_b32_e32 v3, s2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s5, s8
-; GFX9-NEXT: s_cmp_ge_u32 s0, s13
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
-; GFX9-NEXT: s_cmp_eq_u32 s0, s13
-; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v5, s0
-; GFX9-NEXT: s_ashr_i32 s0, s15, 31
-; GFX9-NEXT: s_add_u32 s2, s14, s0
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
+; GFX9-NEXT: s_add_u32 s0, s8, s12
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: s_addc_u32 s1, s9, s12
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
+; GFX9-NEXT: v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s8, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s9, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s9, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s14, v0
+; GFX9-NEXT: v_mul_hi_u32 v3, s14, v1
+; GFX9-NEXT: v_mul_lo_u32 v4, s15, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s14, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v3, s9, v2
+; GFX9-NEXT: v_mov_b32_e32 v4, s15
+; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s8, v1
+; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s14, v1
+; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s15, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s14, v5
+; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s15, v6
+; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s14, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1]
+; GFX9-NEXT: s_ashr_i32 s0, s17, 31
+; GFX9-NEXT: s_add_u32 s2, s16, s0
; GFX9-NEXT: s_mov_b32 s1, s0
-; GFX9-NEXT: s_addc_u32 s3, s15, s0
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX9-NEXT: s_addc_u32 s3, s17, s0
+; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s5
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX9-NEXT: v_xor_b32_e32 v0, s16, v0
-; GFX9-NEXT: v_xor_b32_e32 v2, s16, v2
-; GFX9-NEXT: v_mac_f32_e32 v1, 0x4f800000, v3
-; GFX9-NEXT: v_rcp_f32_e32 v3, v1
-; GFX9-NEXT: v_mov_b32_e32 v5, s16
-; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s16, v0
-; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v5, vcc
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; GFX9-NEXT: v_trunc_f32_e32 v3, v3
-; GFX9-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
+; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s5
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v1
+; GFX9-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
+; GFX9-NEXT: v_rcp_f32_e32 v5, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v5
+; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v3
+; GFX9-NEXT: v_trunc_f32_e32 v5, v5
+; GFX9-NEXT: v_mac_f32_e32 v3, 0xcf800000, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_sub_u32 s0, 0, s4
; GFX9-NEXT: s_subb_u32 s1, 0, s5
-; GFX9-NEXT: v_readfirstlane_b32 s2, v2
-; GFX9-NEXT: v_readfirstlane_b32 s9, v3
-; GFX9-NEXT: s_mul_hi_u32 s8, s0, s2
-; GFX9-NEXT: s_mul_i32 s12, s0, s9
-; GFX9-NEXT: s_mul_i32 s3, s1, s2
-; GFX9-NEXT: s_add_i32 s8, s8, s12
-; GFX9-NEXT: s_add_i32 s8, s8, s3
-; GFX9-NEXT: s_mul_i32 s13, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s3, s2, s8
-; GFX9-NEXT: s_mul_i32 s12, s2, s8
-; GFX9-NEXT: s_mul_hi_u32 s2, s2, s13
-; GFX9-NEXT: s_add_u32 s2, s2, s12
-; GFX9-NEXT: s_addc_u32 s3, 0, s3
-; GFX9-NEXT: s_mul_hi_u32 s14, s9, s13
-; GFX9-NEXT: s_mul_i32 s13, s9, s13
-; GFX9-NEXT: s_add_u32 s2, s2, s13
-; GFX9-NEXT: s_mul_hi_u32 s12, s9, s8
-; GFX9-NEXT: s_addc_u32 s2, s3, s14
-; GFX9-NEXT: s_addc_u32 s3, s12, 0
-; GFX9-NEXT: s_mul_i32 s8, s9, s8
-; GFX9-NEXT: s_add_u32 s2, s2, s8
-; GFX9-NEXT: s_addc_u32 s3, 0, s3
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s2, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s9, s3
-; GFX9-NEXT: v_readfirstlane_b32 s8, v2
-; GFX9-NEXT: s_mul_i32 s3, s0, s2
-; GFX9-NEXT: s_mul_hi_u32 s9, s0, s8
-; GFX9-NEXT: s_add_i32 s3, s9, s3
-; GFX9-NEXT: s_mul_i32 s1, s1, s8
-; GFX9-NEXT: s_add_i32 s3, s3, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s8
-; GFX9-NEXT: s_mul_hi_u32 s9, s2, s0
-; GFX9-NEXT: s_mul_i32 s12, s2, s0
-; GFX9-NEXT: s_mul_i32 s14, s8, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s8, s0
-; GFX9-NEXT: s_mul_hi_u32 s13, s8, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s14
-; GFX9-NEXT: s_addc_u32 s8, 0, s13
-; GFX9-NEXT: s_add_u32 s0, s0, s12
-; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3
-; GFX9-NEXT: s_addc_u32 s0, s8, s9
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s3, s2, s3
-; GFX9-NEXT: s_add_u32 s0, s0, s3
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s2, s2, s1
+; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5
+; GFX9-NEXT: v_mul_lo_u32 v8, s1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v3
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_mul_lo_u32 v7, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v8, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, v3, v6
+; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT: v_mul_lo_u32 v9, v5, v4
+; GFX9-NEXT: v_mul_hi_u32 v4, v5, v4
; GFX9-NEXT: s_ashr_i32 s8, s11, 31
-; GFX9-NEXT: s_add_u32 s0, s10, s8
; GFX9-NEXT: s_mov_b32 s9, s8
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3
+; GFX9-NEXT: v_mul_lo_u32 v7, s1, v3
+; GFX9-NEXT: v_mul_lo_u32 v8, s0, v3
+; GFX9-NEXT: s_add_u32 s0, s10, s8
+; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v7
+; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8
+; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5
+; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8
+; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5
+; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: s_addc_u32 s1, s11, s8
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc
; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9]
-; GFX9-NEXT: v_readfirstlane_b32 s3, v2
-; GFX9-NEXT: s_mul_i32 s1, s10, s2
-; GFX9-NEXT: s_mul_hi_u32 s9, s10, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s10, s2
-; GFX9-NEXT: s_add_u32 s1, s9, s1
-; GFX9-NEXT: s_addc_u32 s0, 0, s0
-; GFX9-NEXT: s_mul_hi_u32 s12, s11, s3
-; GFX9-NEXT: s_mul_i32 s3, s11, s3
-; GFX9-NEXT: s_add_u32 s1, s1, s3
-; GFX9-NEXT: s_mul_hi_u32 s9, s11, s2
-; GFX9-NEXT: s_addc_u32 s0, s0, s12
-; GFX9-NEXT: s_addc_u32 s1, s9, 0
-; GFX9-NEXT: s_mul_i32 s2, s11, s2
-; GFX9-NEXT: s_add_u32 s0, s0, s2
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: s_mul_i32 s1, s4, s1
-; GFX9-NEXT: s_mul_hi_u32 s2, s4, s0
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: s_mul_i32 s2, s5, s0
-; GFX9-NEXT: s_mul_i32 s0, s4, s0
-; GFX9-NEXT: s_add_i32 s9, s1, s2
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: s_sub_i32 s1, s11, s9
-; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s10, v2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s10, s1, s5
-; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s4, v2
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s12, s10, 0
-; GFX9-NEXT: s_cmp_ge_u32 s12, s5
-; GFX9-NEXT: s_cselect_b32 s13, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v3
-; GFX9-NEXT: s_cmp_eq_u32 s12, s5
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[2:3]
-; GFX9-NEXT: v_mov_b32_e32 v6, s13
-; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[2:3]
-; GFX9-NEXT: s_subb_u32 s2, s10, s5
-; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s4, v3
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s2, s2, 0
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v5, s12
-; GFX9-NEXT: v_mov_b32_e32 v6, s2
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s11, s9
-; GFX9-NEXT: s_cmp_ge_u32 s0, s5
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
-; GFX9-NEXT: s_cmp_eq_u32 s0, s5
-; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v7, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s0
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX9-NEXT: v_xor_b32_e32 v2, s8, v2
-; GFX9-NEXT: v_xor_b32_e32 v3, s8, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, s10, v4
+; GFX9-NEXT: v_mul_hi_u32 v6, s10, v3
+; GFX9-NEXT: v_mul_hi_u32 v8, s10, v4
+; GFX9-NEXT: v_mul_hi_u32 v9, s11, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v4
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3
+; GFX9-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX9-NEXT: v_xor_b32_e32 v1, s12, v1
+; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v9, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s4, v4
+; GFX9-NEXT: v_mul_hi_u32 v5, s4, v3
+; GFX9-NEXT: v_mul_lo_u32 v6, s5, v3
+; GFX9-NEXT: v_mul_lo_u32 v3, s4, v3
+; GFX9-NEXT: v_mov_b32_e32 v7, s12
+; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v1
+; GFX9-NEXT: v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_sub_u32_e32 v5, s11, v4
+; GFX9-NEXT: v_mov_b32_e32 v6, s5
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s10, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s4, v3
+; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v7
+; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s5, v8
+; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s4, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[2:3]
+; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v7, s11
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s5, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s5, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; GFX9-NEXT: v_xor_b32_e32 v3, s8, v3
+; GFX9-NEXT: v_xor_b32_e32 v4, s8, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s8
-; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s8, v2
-; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc
-; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s8, v3
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v5, vcc
+; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[6:7]
; GFX9-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y
diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
index afcd9b5fcdc7e..59f6602e4a8f2 100644
--- a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
@@ -737,9 +737,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX908-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX908-NEXT: s_mov_b64 s[4:5], -1
; GFX908-NEXT: s_mov_b32 s6, 1
-; GFX908-NEXT: v_readfirstlane_b32 s7, v2
-; GFX908-NEXT: s_cmp_lg_u32 s7, s6
-; GFX908-NEXT: s_cselect_b64 s[6:7], -1, 0
+; GFX908-NEXT: v_cmp_ne_u32_e64 s[6:7], v2, s6
; GFX908-NEXT: s_and_b64 vcc, exec, s[6:7]
; GFX908-NEXT: ; implicit-def: $vgpr3_vgpr4
; GFX908-NEXT: s_cbranch_vccnz .LBB5_2
@@ -808,9 +806,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX90A-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX90A-NEXT: s_mov_b64 s[4:5], -1
; GFX90A-NEXT: s_mov_b32 s6, 1
-; GFX90A-NEXT: v_readfirstlane_b32 s7, v2
-; GFX90A-NEXT: s_cmp_lg_u32 s7, s6
-; GFX90A-NEXT: s_cselect_b64 s[6:7], -1, 0
+; GFX90A-NEXT: v_cmp_ne_u32_e64 s[6:7], v2, s6
; GFX90A-NEXT: s_and_b64 vcc, exec, s[6:7]
; GFX90A-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX90A-NEXT: s_cbranch_vccnz .LBB5_2
@@ -877,9 +873,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
; GFX942-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX942-NEXT: s_mov_b64 s[0:1], -1
; GFX942-NEXT: s_mov_b32 s2, 1
-; GFX942-NEXT: v_readfirstlane_b32 s3, v2
-; GFX942-NEXT: s_cmp_lg_u32 s3, s2
-; GFX942-NEXT: s_cselect_b64 s[2:3], -1, 0
+; GFX942-NEXT: v_cmp_ne_u32_e64 s[2:3], v2, s2
; GFX942-NEXT: s_and_b64 vcc, exec, s[2:3]
; GFX942-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX942-NEXT: s_cbranch_vccnz .LBB5_2
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index efcaa8807367b..2ef88010bd157 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -18822,23 +18822,23 @@ define amdgpu_ps i32 @s_fneg_fabs_bf16(bfloat inreg %a) {
; GCN-LABEL: s_fneg_fabs_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: v_mul_f32_e64 v0, 1.0, s0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
-; GCN-NEXT: s_bitset0_b32 s0, 31
-; GCN-NEXT: s_and_b32 s0, s0, 0xffff0000
-; GCN-NEXT: s_xor_b32 s0, s0, 0x80000000
-; GCN-NEXT: s_lshr_b32 s0, s0, 16
; GCN-NEXT: ; return to shader part epilog
;
; GFX7-LABEL: s_fneg_fabs_bf16:
; GFX7: ; %bb.0:
; GFX7-NEXT: v_mul_f32_e64 v0, 1.0, s0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX7-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
-; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
-; GFX7-NEXT: s_bitset0_b32 s0, 31
-; GFX7-NEXT: s_and_b32 s0, s0, 0xffff0000
-; GFX7-NEXT: s_xor_b32 s0, s0, 0x80000000
-; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fneg_fabs_bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
index aabcd69c88ca3..dac78a727d72c 100644
--- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
+++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll
@@ -1896,19 +1896,16 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; CISI-NEXT: v_mul_hi_u32 v1, v0, v1
; CISI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CISI-NEXT: v_mul_hi_u32 v0, s10, v0
-; CISI-NEXT: v_readfirstlane_b32 s0, v0
-; CISI-NEXT: s_mul_i32 s0, s0, s2
-; CISI-NEXT: s_sub_i32 s0, s10, s0
-; CISI-NEXT: s_sub_i32 s1, s0, s2
-; CISI-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; CISI-NEXT: s_cmp_ge_u32 s0, s2
-; CISI-NEXT: s_cselect_b64 vcc, -1, 0
-; CISI-NEXT: s_cselect_b32 s0, s1, s0
-; CISI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; CISI-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; CISI-NEXT: s_cmp_ge_u32 s0, s2
-; CISI-NEXT: s_cselect_b64 vcc, -1, 0
-; CISI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; CISI-NEXT: v_mul_lo_u32 v1, v0, s2
+; CISI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; CISI-NEXT: v_sub_i32_e32 v1, vcc, s10, v1
+; CISI-NEXT: v_subrev_i32_e32 v3, vcc, s2, v1
+; CISI-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; CISI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; CISI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; CISI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; CISI-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; CISI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; CISI-NEXT: v_mov_b32_e32 v1, 0
; CISI-NEXT: .LBB16_3:
; CISI-NEXT: s_mov_b32 s11, 0xf000
@@ -1979,69 +1976,50 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; VI-NEXT: v_addc_u32_e32 v3, vcc, v7, v1, vcc
; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s10, v3, 0
; VI-NEXT: v_mul_hi_u32 v4, s10, v2
-; VI-NEXT: v_readfirstlane_b32 s4, v1
-; VI-NEXT: v_readfirstlane_b32 s5, v0
-; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s11, v3, 0
-; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s11, v2, 0
-; VI-NEXT: v_readfirstlane_b32 s6, v4
-; VI-NEXT: s_add_u32 s0, s6, s5
-; VI-NEXT: s_addc_u32 s1, 0, s4
-; VI-NEXT: v_readfirstlane_b32 s6, v2
-; VI-NEXT: v_readfirstlane_b32 s5, v3
-; VI-NEXT: s_add_u32 s0, s0, s6
-; VI-NEXT: v_readfirstlane_b32 s4, v1
-; VI-NEXT: s_addc_u32 s0, s1, s5
-; VI-NEXT: s_addc_u32 s6, s4, 0
-; VI-NEXT: v_readfirstlane_b32 s1, v0
-; VI-NEXT: s_add_u32 s7, s0, s1
-; VI-NEXT: v_mov_b32_e32 v2, s7
+; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s11, v2, 0
+; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s11, v3, 0
+; VI-NEXT: v_add_u32_e32 v0, vcc, v4, v0
+; VI-NEXT: v_addc_u32_e32 v0, vcc, v5, v1, vcc
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT: v_add_u32_e32 v2, vcc, v0, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
+; VI-NEXT: v_mul_lo_u32 v4, s2, v3
; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v2, 0
-; VI-NEXT: s_addc_u32 s6, 0, s6
-; VI-NEXT: s_mul_i32 s0, s2, s6
-; VI-NEXT: v_readfirstlane_b32 s1, v1
-; VI-NEXT: s_add_i32 s0, s1, s0
-; VI-NEXT: s_mul_i32 s1, s3, s7
-; VI-NEXT: s_add_i32 s12, s0, s1
-; VI-NEXT: s_sub_i32 s0, s11, s12
+; VI-NEXT: v_mul_lo_u32 v5, s3, v2
+; VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1
+; VI-NEXT: v_add_u32_e32 v1, vcc, v5, v1
+; VI-NEXT: v_sub_u32_e32 v4, vcc, s11, v1
+; VI-NEXT: v_mov_b32_e32 v5, s3
; VI-NEXT: v_sub_u32_e32 v0, vcc, s10, v0
-; VI-NEXT: s_cmp_lg_u64 vcc, 0
-; VI-NEXT: s_subb_u32 s13, s0, s3
-; VI-NEXT: v_subrev_u32_e64 v1, s[0:1], s2, v0
-; VI-NEXT: s_cmp_lg_u64 s[0:1], 0
-; VI-NEXT: s_subb_u32 s13, s13, 0
-; VI-NEXT: s_cmp_ge_u32 s13, s3
-; VI-NEXT: s_cselect_b32 s14, -1, 0
-; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1
-; VI-NEXT: s_cmp_eq_u32 s13, s3
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1]
-; VI-NEXT: v_mov_b32_e32 v3, s14
-; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
-; VI-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1]
-; VI-NEXT: s_add_u32 s0, s7, 1
-; VI-NEXT: s_addc_u32 s13, s6, 0
-; VI-NEXT: s_add_u32 s1, s7, 2
-; VI-NEXT: s_addc_u32 s7, s6, 0
-; VI-NEXT: v_mov_b32_e32 v3, s0
-; VI-NEXT: v_mov_b32_e32 v4, s1
-; VI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
-; VI-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; VI-NEXT: v_mov_b32_e32 v1, s13
-; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: s_cmp_lg_u64 vcc, 0
-; VI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; VI-NEXT: s_subb_u32 s0, s11, s12
-; VI-NEXT: s_cmp_ge_u32 s0, s3
-; VI-NEXT: s_cselect_b32 s1, -1, 0
+; VI-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
+; VI-NEXT: v_subrev_u32_e64 v5, s[0:1], s2, v0
+; VI-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
+; VI-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
+; VI-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; VI-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
+; VI-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; VI-NEXT: v_add_u32_e64 v5, s[0:1], 1, v2
+; VI-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v3, s[0:1]
+; VI-NEXT: v_add_u32_e64 v7, s[0:1], 2, v2
+; VI-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
+; VI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
+; VI-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
+; VI-NEXT: v_mov_b32_e32 v6, s11
+; VI-NEXT: v_subb_u32_e32 v1, vcc, v6, v1, vcc
+; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; VI-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; VI-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
-; VI-NEXT: s_cmp_eq_u32 s0, s3
; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; VI-NEXT: v_mov_b32_e32 v4, s1
-; VI-NEXT: s_cselect_b64 vcc, -1, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; VI-NEXT: v_mov_b32_e32 v4, s6
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
+; VI-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; VI-NEXT: s_cbranch_execnz .LBB16_3
; VI-NEXT: .LBB16_2:
; VI-NEXT: v_cvt_f32_u32_e32 v0, s2
@@ -2053,19 +2031,16 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; VI-NEXT: v_mul_hi_u32 v1, v0, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; VI-NEXT: v_mul_hi_u32 v0, s10, v0
-; VI-NEXT: v_readfirstlane_b32 s0, v0
-; VI-NEXT: s_mul_i32 s0, s0, s2
-; VI-NEXT: s_sub_i32 s0, s10, s0
-; VI-NEXT: s_sub_i32 s1, s0, s2
-; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; VI-NEXT: s_cmp_ge_u32 s0, s2
-; VI-NEXT: s_cselect_b64 vcc, -1, 0
-; VI-NEXT: s_cselect_b32 s0, s1, s0
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; VI-NEXT: s_cmp_ge_u32 s0, s2
-; VI-NEXT: s_cselect_b64 vcc, -1, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-NEXT: v_mul_lo_u32 v1, v0, s2
+; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; VI-NEXT: v_sub_u32_e32 v1, vcc, s10, v1
+; VI-NEXT: v_subrev_u32_e32 v3, vcc, s2, v1
+; VI-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; VI-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: .LBB16_3:
; VI-NEXT: v_mov_b32_e32 v2, s8
@@ -2098,143 +2073,122 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v1
-; GFX9-NEXT: v_readfirstlane_b32 s7, v0
-; GFX9-NEXT: s_mul_i32 s12, s0, s6
-; GFX9-NEXT: s_mul_hi_u32 s14, s0, s7
-; GFX9-NEXT: s_mul_i32 s13, s1, s7
-; GFX9-NEXT: s_add_i32 s12, s14, s12
-; GFX9-NEXT: s_add_i32 s12, s12, s13
-; GFX9-NEXT: s_mul_i32 s15, s0, s7
-; GFX9-NEXT: s_mul_hi_u32 s13, s7, s12
-; GFX9-NEXT: s_mul_i32 s14, s7, s12
-; GFX9-NEXT: s_mul_hi_u32 s7, s7, s15
-; GFX9-NEXT: s_add_u32 s7, s7, s14
-; GFX9-NEXT: s_addc_u32 s13, 0, s13
-; GFX9-NEXT: s_mul_hi_u32 s16, s6, s15
-; GFX9-NEXT: s_mul_i32 s15, s6, s15
-; GFX9-NEXT: s_add_u32 s7, s7, s15
-; GFX9-NEXT: s_mul_hi_u32 s14, s6, s12
-; GFX9-NEXT: s_addc_u32 s7, s13, s16
-; GFX9-NEXT: s_addc_u32 s13, s14, 0
-; GFX9-NEXT: s_mul_i32 s12, s6, s12
-; GFX9-NEXT: s_add_u32 s7, s7, s12
-; GFX9-NEXT: s_addc_u32 s12, 0, s13
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s7, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s6, s6, s12
-; GFX9-NEXT: v_readfirstlane_b32 s12, v0
-; GFX9-NEXT: s_mul_i32 s7, s0, s6
-; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12
-; GFX9-NEXT: s_add_i32 s7, s13, s7
-; GFX9-NEXT: s_mul_i32 s1, s1, s12
-; GFX9-NEXT: s_add_i32 s7, s7, s1
-; GFX9-NEXT: s_mul_i32 s0, s0, s12
-; GFX9-NEXT: s_mul_hi_u32 s13, s6, s0
-; GFX9-NEXT: s_mul_i32 s14, s6, s0
-; GFX9-NEXT: s_mul_i32 s16, s12, s7
-; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0
-; GFX9-NEXT: s_mul_hi_u32 s15, s12, s7
-; GFX9-NEXT: s_add_u32 s0, s0, s16
-; GFX9-NEXT: s_addc_u32 s12, 0, s15
-; GFX9-NEXT: s_add_u32 s0, s0, s14
-; GFX9-NEXT: s_mul_hi_u32 s1, s6, s7
-; GFX9-NEXT: s_addc_u32 s0, s12, s13
-; GFX9-NEXT: s_addc_u32 s1, s1, 0
-; GFX9-NEXT: s_mul_i32 s7, s6, s7
-; GFX9-NEXT: s_add_u32 s0, s0, s7
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_addc_u32 s0, s6, s1
-; GFX9-NEXT: v_readfirstlane_b32 s7, v0
-; GFX9-NEXT: s_mul_i32 s6, s10, s0
-; GFX9-NEXT: s_mul_hi_u32 s12, s10, s7
-; GFX9-NEXT: s_mul_hi_u32 s1, s10, s0
-; GFX9-NEXT: s_add_u32 s6, s12, s6
-; GFX9-NEXT: s_addc_u32 s1, 0, s1
-; GFX9-NEXT: s_mul_hi_u32 s13, s11, s7
-; GFX9-NEXT: s_mul_i32 s7, s11, s7
-; GFX9-NEXT: s_add_u32 s6, s6, s7
-; GFX9-NEXT: s_mul_hi_u32 s12, s11, s0
-; GFX9-NEXT: s_addc_u32 s1, s1, s13
-; GFX9-NEXT: s_addc_u32 s6, s12, 0
-; GFX9-NEXT: s_mul_i32 s0, s11, s0
-; GFX9-NEXT: s_add_u32 s7, s1, s0
-; GFX9-NEXT: s_addc_u32 s6, 0, s6
-; GFX9-NEXT: s_mul_i32 s0, s2, s6
-; GFX9-NEXT: s_mul_hi_u32 s1, s2, s7
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_mul_i32 s1, s3, s7
-; GFX9-NEXT: s_add_i32 s12, s0, s1
-; GFX9-NEXT: s_mul_i32 s1, s2, s7
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: s_sub_i32 s0, s11, s12
-; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s10, v0
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: s_subb_u32 s13, s0, s3
-; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s2, v0
-; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX9-NEXT: s_subb_u32 s13, s13, 0
-; GFX9-NEXT: s_cmp_ge_u32 s13, s3
-; GFX9-NEXT: s_cselect_b32 s14, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1
-; GFX9-NEXT: s_cmp_eq_u32 s13, s3
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v2, s14
-; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
-; GFX9-NEXT: s_add_u32 s0, s7, 1
-; GFX9-NEXT: s_addc_u32 s13, s6, 0
-; GFX9-NEXT: s_add_u32 s1, s7, 2
-; GFX9-NEXT: s_addc_u32 s14, s6, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX9-NEXT: v_mov_b32_e32 v1, s13
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
-; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX9-NEXT: s_subb_u32 s0, s11, s12
-; GFX9-NEXT: s_cmp_ge_u32 s0, s3
-; GFX9-NEXT: s_cselect_b32 s1, -1, 0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
-; GFX9-NEXT: s_cmp_eq_u32 s0, s3
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s1
-; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_mov_b32_e32 v0, s7
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
+; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
+; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v6, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v0, v5
+; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v4, v1, v5
+; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
+; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
+; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s10, v0
+; GFX9-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX9-NEXT: v_mul_hi_u32 v5, s11, v1
+; GFX9-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v4, s11, v0
+; GFX9-NEXT: v_mul_hi_u32 v0, s11, v0
+; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
+; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1
+; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX9-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
+; GFX9-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
+; GFX9-NEXT: v_sub_u32_e32 v4, s11, v2
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s10, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc
+; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s2, v3
+; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], 1, v0
+; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], 2, v0
+; GFX9-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v1, s[0:1]
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v6, s11
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v6, v2, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: s_cbranch_execnz .LBB16_3
; GFX9-NEXT: .LBB16_2:
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: s_sub_i32 s0, 0, s2
-; GFX9-NEXT: s_mov_b32 s1, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s3, v0
-; GFX9-NEXT: s_mul_i32 s0, s0, s3
-; GFX9-NEXT: s_mul_hi_u32 s0, s3, s0
-; GFX9-NEXT: s_add_i32 s3, s3, s0
-; GFX9-NEXT: s_mul_hi_u32 s0, s10, s3
-; GFX9-NEXT: s_mul_i32 s4, s0, s2
-; GFX9-NEXT: s_sub_i32 s4, s10, s4
-; GFX9-NEXT: s_add_i32 s3, s0, 1
-; GFX9-NEXT: s_sub_i32 s5, s4, s2
-; GFX9-NEXT: s_cmp_ge_u32 s4, s2
-; GFX9-NEXT: s_cselect_b32 s0, s3, s0
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s3, s0, 1
-; GFX9-NEXT: s_cmp_ge_u32 s4, s2
-; GFX9-NEXT: s_cselect_b32 s0, s3, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s10, v1
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: .LBB16_3:
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
@@ -2256,8 +2210,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1010-NEXT: ; %bb.1:
; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX1010-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX1010-NEXT: s_sub_u32 s5, 0, s2
-; GFX1010-NEXT: s_subb_u32 s6, 0, s3
+; GFX1010-NEXT: s_sub_u32 s0, 0, s2
+; GFX1010-NEXT: s_subb_u32 s1, 0, s3
; GFX1010-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
; GFX1010-NEXT: v_rcp_f32_e32 v0, v0
; GFX1010-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -2266,137 +2220,121 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1010-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX1010-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1010-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1010-NEXT: v_readfirstlane_b32 s0, v1
-; GFX1010-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1010-NEXT: s_mul_i32 s7, s5, s0
-; GFX1010-NEXT: s_mul_hi_u32 s13, s5, s1
-; GFX1010-NEXT: s_mul_i32 s12, s6, s1
-; GFX1010-NEXT: s_add_i32 s7, s13, s7
-; GFX1010-NEXT: s_mul_i32 s14, s5, s1
-; GFX1010-NEXT: s_add_i32 s7, s7, s12
-; GFX1010-NEXT: s_mul_hi_u32 s13, s1, s14
-; GFX1010-NEXT: s_mul_hi_u32 s15, s0, s14
-; GFX1010-NEXT: s_mul_i32 s12, s0, s14
-; GFX1010-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX1010-NEXT: s_mul_i32 s1, s1, s7
-; GFX1010-NEXT: s_mul_hi_u32 s16, s0, s7
-; GFX1010-NEXT: s_add_u32 s1, s13, s1
-; GFX1010-NEXT: s_addc_u32 s13, 0, s14
-; GFX1010-NEXT: s_add_u32 s1, s1, s12
-; GFX1010-NEXT: s_mul_i32 s7, s0, s7
-; GFX1010-NEXT: s_addc_u32 s1, s13, s15
-; GFX1010-NEXT: s_addc_u32 s12, s16, 0
-; GFX1010-NEXT: s_add_u32 s1, s1, s7
-; GFX1010-NEXT: s_addc_u32 s7, 0, s12
-; GFX1010-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1010-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1010-NEXT: s_addc_u32 s0, s0, s7
-; GFX1010-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1010-NEXT: s_mul_i32 s7, s5, s0
-; GFX1010-NEXT: s_mul_hi_u32 s12, s5, s1
-; GFX1010-NEXT: s_mul_i32 s6, s6, s1
-; GFX1010-NEXT: s_add_i32 s7, s12, s7
-; GFX1010-NEXT: s_mul_i32 s5, s5, s1
-; GFX1010-NEXT: s_add_i32 s7, s7, s6
-; GFX1010-NEXT: s_mul_hi_u32 s12, s0, s5
-; GFX1010-NEXT: s_mul_i32 s13, s0, s5
-; GFX1010-NEXT: s_mul_hi_u32 s5, s1, s5
-; GFX1010-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX1010-NEXT: s_mul_i32 s1, s1, s7
-; GFX1010-NEXT: s_mul_hi_u32 s6, s0, s7
-; GFX1010-NEXT: s_add_u32 s1, s5, s1
-; GFX1010-NEXT: s_addc_u32 s5, 0, s14
-; GFX1010-NEXT: s_add_u32 s1, s1, s13
-; GFX1010-NEXT: s_mul_i32 s7, s0, s7
-; GFX1010-NEXT: s_addc_u32 s1, s5, s12
-; GFX1010-NEXT: s_addc_u32 s5, s6, 0
-; GFX1010-NEXT: s_add_u32 s1, s1, s7
-; GFX1010-NEXT: s_addc_u32 s5, 0, s5
-; GFX1010-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1010-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1010-NEXT: s_addc_u32 s0, s0, s5
-; GFX1010-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1010-NEXT: s_mul_i32 s6, s10, s0
-; GFX1010-NEXT: s_mul_hi_u32 s5, s10, s0
-; GFX1010-NEXT: s_mul_hi_u32 s7, s11, s0
-; GFX1010-NEXT: s_mul_i32 s0, s11, s0
-; GFX1010-NEXT: s_mul_hi_u32 s12, s10, s1
-; GFX1010-NEXT: s_mul_hi_u32 s13, s11, s1
-; GFX1010-NEXT: s_mul_i32 s1, s11, s1
-; GFX1010-NEXT: s_add_u32 s6, s12, s6
-; GFX1010-NEXT: s_addc_u32 s5, 0, s5
-; GFX1010-NEXT: s_add_u32 s1, s6, s1
-; GFX1010-NEXT: s_addc_u32 s1, s5, s13
-; GFX1010-NEXT: s_addc_u32 s5, s7, 0
-; GFX1010-NEXT: s_add_u32 s1, s1, s0
-; GFX1010-NEXT: s_addc_u32 s5, 0, s5
-; GFX1010-NEXT: s_mul_hi_u32 s0, s2, s1
-; GFX1010-NEXT: s_mul_i32 s7, s2, s5
-; GFX1010-NEXT: s_mul_i32 s12, s2, s1
-; GFX1010-NEXT: s_add_i32 s0, s0, s7
-; GFX1010-NEXT: v_sub_co_u32 v0, s7, s10, s12
-; GFX1010-NEXT: s_mul_i32 s6, s3, s1
-; GFX1010-NEXT: s_add_i32 s0, s0, s6
-; GFX1010-NEXT: v_sub_co_u32 v1, s12, v0, s2
-; GFX1010-NEXT: s_sub_i32 s6, s11, s0
-; GFX1010-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1010-NEXT: s_subb_u32 s6, s6, s3
-; GFX1010-NEXT: s_cmp_lg_u32 s12, 0
-; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
-; GFX1010-NEXT: s_subb_u32 s6, s6, 0
-; GFX1010-NEXT: s_cmp_ge_u32 s6, s3
-; GFX1010-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX1010-NEXT: s_cselect_b32 s12, -1, 0
-; GFX1010-NEXT: s_cmp_eq_u32 s6, s3
-; GFX1010-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1010-NEXT: s_add_u32 s6, s1, 1
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1010-NEXT: s_addc_u32 s12, s5, 0
-; GFX1010-NEXT: s_add_u32 s13, s1, 2
-; GFX1010-NEXT: s_addc_u32 s14, s5, 0
-; GFX1010-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0
-; GFX1010-NEXT: s_subb_u32 s0, s11, s0
-; GFX1010-NEXT: v_mov_b32_e32 v2, s13
-; GFX1010-NEXT: s_cmp_ge_u32 s0, s3
-; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX1010-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1010-NEXT: s_cmp_eq_u32 s0, s3
-; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX1010-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1010-NEXT: v_mov_b32_e32 v1, s14
-; GFX1010-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0
-; GFX1010-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1010-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX1010-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo
+; GFX1010-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX1010-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX1010-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX1010-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1010-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1010-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1010-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1010-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1010-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1010-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1010-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1010-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1010-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX1010-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1010-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1010-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1010-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1010-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1010-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1010-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1010-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1010-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1010-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1010-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1010-NEXT: v_mul_hi_u32 v2, s10, v0
+; GFX1010-NEXT: v_mul_hi_u32 v5, s11, v0
+; GFX1010-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX1010-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX1010-NEXT: v_mul_lo_u32 v0, s11, v0
+; GFX1010-NEXT: v_mul_hi_u32 v6, s11, v1
+; GFX1010-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX1010-NEXT: v_add_co_u32 v2, vcc_lo, v2, v3
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v3, v5, vcc_lo
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v0, vcc_lo, v0, v1
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
+; GFX1010-NEXT: v_mul_hi_u32 v2, s2, v0
+; GFX1010-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX1010-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1010-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1010-NEXT: v_sub_co_u32 v3, vcc_lo, s10, v3
+; GFX1010-NEXT: v_sub_nc_u32_e32 v4, s11, v2
+; GFX1010-NEXT: v_subrev_co_ci_u32_e64 v4, s0, s3, v4, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v5, s0, v0, 1
+; GFX1010-NEXT: v_add_co_ci_u32_e64 v6, s0, 0, v1, s0
+; GFX1010-NEXT: v_sub_co_u32 v7, s0, v3, s2
+; GFX1010-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
+; GFX1010-NEXT: v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v7
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s0, s3, v2
+; GFX1010-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v4
+; GFX1010-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX1010-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc_lo
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v2
+; GFX1010-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
+; GFX1010-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v4
+; GFX1010-NEXT: v_cndmask_b32_e64 v2, v9, v3, s0
+; GFX1010-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo
+; GFX1010-NEXT: v_add_co_u32 v7, vcc_lo, v0, 2
+; GFX1010-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX1010-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
+; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1010-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
; GFX1010-NEXT: s_cbranch_vccnz .LBB16_3
; GFX1010-NEXT: .LBB16_2:
; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX1010-NEXT: s_sub_i32 s1, 0, s2
+; GFX1010-NEXT: s_sub_i32 s0, 0, s2
; GFX1010-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1010-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1010-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1010-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1010-NEXT: s_mul_i32 s1, s1, s0
-; GFX1010-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX1010-NEXT: s_add_i32 s0, s0, s1
-; GFX1010-NEXT: s_mul_hi_u32 s0, s10, s0
-; GFX1010-NEXT: s_mul_i32 s1, s0, s2
-; GFX1010-NEXT: s_add_i32 s3, s0, 1
-; GFX1010-NEXT: s_sub_i32 s1, s10, s1
-; GFX1010-NEXT: s_sub_i32 s4, s1, s2
-; GFX1010-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1010-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1010-NEXT: s_cselect_b32 s1, s4, s1
-; GFX1010-NEXT: s_add_i32 s3, s0, 1
-; GFX1010-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1010-NEXT: s_mov_b32 s1, 0
-; GFX1010-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1010-NEXT: v_mov_b32_e32 v0, s0
-; GFX1010-NEXT: v_mov_b32_e32 v1, s1
+; GFX1010-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX1010-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1010-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1010-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX1010-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1010-NEXT: v_sub_nc_u32_e32 v1, s10, v1
+; GFX1010-NEXT: v_subrev_nc_u32_e32 v3, s2, v1
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX1010-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX1010-NEXT: .LBB16_3:
; GFX1010-NEXT: v_mov_b32_e32 v2, 0
; GFX1010-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
@@ -2418,8 +2356,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W32-NEXT: ; %bb.1:
; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX1030W32-NEXT: s_sub_u32 s5, 0, s2
-; GFX1030W32-NEXT: s_subb_u32 s6, 0, s3
+; GFX1030W32-NEXT: s_sub_u32 s0, 0, s2
+; GFX1030W32-NEXT: s_subb_u32 s1, 0, s3
; GFX1030W32-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0
; GFX1030W32-NEXT: v_rcp_f32_e32 v0, v0
; GFX1030W32-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -2428,137 +2366,121 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W32-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0
; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030W32-NEXT: v_readfirstlane_b32 s0, v1
-; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1030W32-NEXT: s_mul_i32 s7, s5, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s13, s5, s1
-; GFX1030W32-NEXT: s_mul_i32 s12, s6, s1
-; GFX1030W32-NEXT: s_add_i32 s7, s13, s7
-; GFX1030W32-NEXT: s_mul_i32 s14, s5, s1
-; GFX1030W32-NEXT: s_add_i32 s7, s7, s12
-; GFX1030W32-NEXT: s_mul_hi_u32 s13, s1, s14
-; GFX1030W32-NEXT: s_mul_hi_u32 s15, s0, s14
-; GFX1030W32-NEXT: s_mul_i32 s12, s0, s14
-; GFX1030W32-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX1030W32-NEXT: s_mul_i32 s1, s1, s7
-; GFX1030W32-NEXT: s_mul_hi_u32 s16, s0, s7
-; GFX1030W32-NEXT: s_add_u32 s1, s13, s1
-; GFX1030W32-NEXT: s_addc_u32 s13, 0, s14
-; GFX1030W32-NEXT: s_add_u32 s1, s1, s12
-; GFX1030W32-NEXT: s_mul_i32 s7, s0, s7
-; GFX1030W32-NEXT: s_addc_u32 s1, s13, s15
-; GFX1030W32-NEXT: s_addc_u32 s12, s16, 0
-; GFX1030W32-NEXT: s_add_u32 s1, s1, s7
-; GFX1030W32-NEXT: s_addc_u32 s7, 0, s12
-; GFX1030W32-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1030W32-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1030W32-NEXT: s_addc_u32 s0, s0, s7
-; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1030W32-NEXT: s_mul_i32 s7, s5, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s12, s5, s1
-; GFX1030W32-NEXT: s_mul_i32 s6, s6, s1
-; GFX1030W32-NEXT: s_add_i32 s7, s12, s7
-; GFX1030W32-NEXT: s_mul_i32 s5, s5, s1
-; GFX1030W32-NEXT: s_add_i32 s7, s7, s6
-; GFX1030W32-NEXT: s_mul_hi_u32 s12, s0, s5
-; GFX1030W32-NEXT: s_mul_i32 s13, s0, s5
-; GFX1030W32-NEXT: s_mul_hi_u32 s5, s1, s5
-; GFX1030W32-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX1030W32-NEXT: s_mul_i32 s1, s1, s7
-; GFX1030W32-NEXT: s_mul_hi_u32 s6, s0, s7
-; GFX1030W32-NEXT: s_add_u32 s1, s5, s1
-; GFX1030W32-NEXT: s_addc_u32 s5, 0, s14
-; GFX1030W32-NEXT: s_add_u32 s1, s1, s13
-; GFX1030W32-NEXT: s_mul_i32 s7, s0, s7
-; GFX1030W32-NEXT: s_addc_u32 s1, s5, s12
-; GFX1030W32-NEXT: s_addc_u32 s5, s6, 0
-; GFX1030W32-NEXT: s_add_u32 s1, s1, s7
-; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5
-; GFX1030W32-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1030W32-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1030W32-NEXT: s_addc_u32 s0, s0, s5
-; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1030W32-NEXT: s_mul_i32 s6, s10, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s5, s10, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s7, s11, s0
-; GFX1030W32-NEXT: s_mul_i32 s0, s11, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s12, s10, s1
-; GFX1030W32-NEXT: s_mul_hi_u32 s13, s11, s1
-; GFX1030W32-NEXT: s_mul_i32 s1, s11, s1
-; GFX1030W32-NEXT: s_add_u32 s6, s12, s6
-; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5
-; GFX1030W32-NEXT: s_add_u32 s1, s6, s1
-; GFX1030W32-NEXT: s_addc_u32 s1, s5, s13
-; GFX1030W32-NEXT: s_addc_u32 s5, s7, 0
-; GFX1030W32-NEXT: s_add_u32 s1, s1, s0
-; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5
-; GFX1030W32-NEXT: s_mul_hi_u32 s0, s2, s1
-; GFX1030W32-NEXT: s_mul_i32 s7, s2, s5
-; GFX1030W32-NEXT: s_mul_i32 s12, s2, s1
-; GFX1030W32-NEXT: s_add_i32 s0, s0, s7
-; GFX1030W32-NEXT: v_sub_co_u32 v0, s7, s10, s12
-; GFX1030W32-NEXT: s_mul_i32 s6, s3, s1
-; GFX1030W32-NEXT: s_add_i32 s0, s0, s6
-; GFX1030W32-NEXT: v_sub_co_u32 v1, s12, v0, s2
-; GFX1030W32-NEXT: s_sub_i32 s6, s11, s0
-; GFX1030W32-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1030W32-NEXT: s_subb_u32 s6, s6, s3
-; GFX1030W32-NEXT: s_cmp_lg_u32 s12, 0
-; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
-; GFX1030W32-NEXT: s_subb_u32 s6, s6, 0
-; GFX1030W32-NEXT: s_cmp_ge_u32 s6, s3
-; GFX1030W32-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX1030W32-NEXT: s_cselect_b32 s12, -1, 0
-; GFX1030W32-NEXT: s_cmp_eq_u32 s6, s3
-; GFX1030W32-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1030W32-NEXT: s_add_u32 s6, s1, 1
-; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1030W32-NEXT: s_addc_u32 s12, s5, 0
-; GFX1030W32-NEXT: s_add_u32 s13, s1, 2
-; GFX1030W32-NEXT: s_addc_u32 s14, s5, 0
-; GFX1030W32-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0
-; GFX1030W32-NEXT: s_subb_u32 s0, s11, s0
-; GFX1030W32-NEXT: v_mov_b32_e32 v2, s13
-; GFX1030W32-NEXT: s_cmp_ge_u32 s0, s3
-; GFX1030W32-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX1030W32-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1030W32-NEXT: s_cmp_eq_u32 s0, s3
-; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX1030W32-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1030W32-NEXT: v_mov_b32_e32 v1, s14
-; GFX1030W32-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0
-; GFX1030W32-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo
-; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX1030W32-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo
+; GFX1030W32-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX1030W32-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W32-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1030W32-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1030W32-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1030W32-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1030W32-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1030W32-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1030W32-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W32-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1030W32-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1030W32-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1030W32-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1030W32-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1030W32-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1030W32-NEXT: v_mul_hi_u32 v2, s10, v0
+; GFX1030W32-NEXT: v_mul_hi_u32 v5, s11, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX1030W32-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX1030W32-NEXT: v_mul_lo_u32 v0, s11, v0
+; GFX1030W32-NEXT: v_mul_hi_u32 v6, s11, v1
+; GFX1030W32-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX1030W32-NEXT: v_add_co_u32 v2, vcc_lo, v2, v3
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v3, v5, vcc_lo
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v0, vcc_lo, v0, v1
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
+; GFX1030W32-NEXT: v_mul_hi_u32 v2, s2, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1030W32-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W32-NEXT: v_sub_co_u32 v3, vcc_lo, s10, v3
+; GFX1030W32-NEXT: v_sub_nc_u32_e32 v4, s11, v2
+; GFX1030W32-NEXT: v_subrev_co_ci_u32_e64 v4, s0, s3, v4, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v5, s0, v0, 1
+; GFX1030W32-NEXT: v_add_co_ci_u32_e64 v6, s0, 0, v1, s0
+; GFX1030W32-NEXT: v_sub_co_u32 v7, s0, v3, s2
+; GFX1030W32-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
+; GFX1030W32-NEXT: v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v7
+; GFX1030W32-NEXT: v_cmp_eq_u32_e64 s0, s3, v2
+; GFX1030W32-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v4
+; GFX1030W32-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX1030W32-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc_lo
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v2
+; GFX1030W32-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
+; GFX1030W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v4
+; GFX1030W32-NEXT: v_cndmask_b32_e64 v2, v9, v3, s0
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo
+; GFX1030W32-NEXT: v_add_co_u32 v7, vcc_lo, v0, 2
+; GFX1030W32-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
+; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1030W32-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
; GFX1030W32-NEXT: s_cbranch_vccnz .LBB16_3
; GFX1030W32-NEXT: .LBB16_2:
; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX1030W32-NEXT: s_sub_i32 s1, 0, s2
+; GFX1030W32-NEXT: s_sub_i32 s0, 0, s2
; GFX1030W32-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1030W32-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030W32-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1030W32-NEXT: s_mul_i32 s1, s1, s0
-; GFX1030W32-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX1030W32-NEXT: s_add_i32 s0, s0, s1
-; GFX1030W32-NEXT: s_mul_hi_u32 s0, s10, s0
-; GFX1030W32-NEXT: s_mul_i32 s1, s0, s2
-; GFX1030W32-NEXT: s_add_i32 s3, s0, 1
-; GFX1030W32-NEXT: s_sub_i32 s1, s10, s1
-; GFX1030W32-NEXT: s_sub_i32 s4, s1, s2
-; GFX1030W32-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1030W32-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1030W32-NEXT: s_cselect_b32 s1, s4, s1
-; GFX1030W32-NEXT: s_add_i32 s3, s0, 1
-; GFX1030W32-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1030W32-NEXT: s_mov_b32 s1, 0
-; GFX1030W32-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1030W32-NEXT: v_mov_b32_e32 v0, s0
-; GFX1030W32-NEXT: v_mov_b32_e32 v1, s1
+; GFX1030W32-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX1030W32-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1030W32-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX1030W32-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030W32-NEXT: v_sub_nc_u32_e32 v1, s10, v1
+; GFX1030W32-NEXT: v_subrev_nc_u32_e32 v3, s2, v1
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX1030W32-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX1030W32-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX1030W32-NEXT: .LBB16_3:
; GFX1030W32-NEXT: v_mov_b32_e32 v2, 0
; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
@@ -2580,8 +2502,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W64-NEXT: ; %bb.1:
; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX1030W64-NEXT: s_sub_u32 s5, 0, s2
-; GFX1030W64-NEXT: s_subb_u32 s6, 0, s3
+; GFX1030W64-NEXT: s_sub_u32 s0, 0, s2
+; GFX1030W64-NEXT: s_subb_u32 s1, 0, s3
; GFX1030W64-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0
; GFX1030W64-NEXT: v_rcp_f32_e32 v0, v0
; GFX1030W64-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -2590,136 +2512,120 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX1030W64-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0
; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030W64-NEXT: v_readfirstlane_b32 s4, v1
-; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1030W64-NEXT: s_mul_i32 s1, s5, s4
-; GFX1030W64-NEXT: s_mul_hi_u32 s12, s5, s0
-; GFX1030W64-NEXT: s_mul_i32 s7, s6, s0
-; GFX1030W64-NEXT: s_add_i32 s1, s12, s1
-; GFX1030W64-NEXT: s_mul_i32 s13, s5, s0
-; GFX1030W64-NEXT: s_add_i32 s1, s1, s7
-; GFX1030W64-NEXT: s_mul_hi_u32 s12, s0, s13
-; GFX1030W64-NEXT: s_mul_hi_u32 s14, s4, s13
-; GFX1030W64-NEXT: s_mul_i32 s7, s4, s13
-; GFX1030W64-NEXT: s_mul_hi_u32 s13, s0, s1
-; GFX1030W64-NEXT: s_mul_i32 s0, s0, s1
-; GFX1030W64-NEXT: s_mul_hi_u32 s15, s4, s1
-; GFX1030W64-NEXT: s_add_u32 s0, s12, s0
-; GFX1030W64-NEXT: s_addc_u32 s12, 0, s13
-; GFX1030W64-NEXT: s_add_u32 s0, s0, s7
-; GFX1030W64-NEXT: s_mul_i32 s1, s4, s1
-; GFX1030W64-NEXT: s_addc_u32 s0, s12, s14
-; GFX1030W64-NEXT: s_addc_u32 s7, s15, 0
-; GFX1030W64-NEXT: s_add_u32 s0, s0, s1
-; GFX1030W64-NEXT: s_addc_u32 s7, 0, s7
-; GFX1030W64-NEXT: v_add_co_u32 v0, s[0:1], v0, s0
-; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1030W64-NEXT: s_addc_u32 s4, s4, s7
-; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1030W64-NEXT: s_mul_i32 s1, s5, s4
-; GFX1030W64-NEXT: s_mul_hi_u32 s7, s5, s0
-; GFX1030W64-NEXT: s_mul_i32 s6, s6, s0
-; GFX1030W64-NEXT: s_add_i32 s1, s7, s1
-; GFX1030W64-NEXT: s_mul_i32 s5, s5, s0
-; GFX1030W64-NEXT: s_add_i32 s1, s1, s6
-; GFX1030W64-NEXT: s_mul_hi_u32 s7, s4, s5
-; GFX1030W64-NEXT: s_mul_i32 s12, s4, s5
-; GFX1030W64-NEXT: s_mul_hi_u32 s5, s0, s5
-; GFX1030W64-NEXT: s_mul_hi_u32 s13, s0, s1
-; GFX1030W64-NEXT: s_mul_i32 s0, s0, s1
-; GFX1030W64-NEXT: s_mul_hi_u32 s6, s4, s1
-; GFX1030W64-NEXT: s_add_u32 s0, s5, s0
-; GFX1030W64-NEXT: s_addc_u32 s5, 0, s13
-; GFX1030W64-NEXT: s_add_u32 s0, s0, s12
-; GFX1030W64-NEXT: s_mul_i32 s1, s4, s1
-; GFX1030W64-NEXT: s_addc_u32 s0, s5, s7
-; GFX1030W64-NEXT: s_addc_u32 s5, s6, 0
-; GFX1030W64-NEXT: s_add_u32 s0, s0, s1
-; GFX1030W64-NEXT: s_addc_u32 s5, 0, s5
-; GFX1030W64-NEXT: v_add_co_u32 v0, s[0:1], v0, s0
-; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1030W64-NEXT: s_addc_u32 s0, s4, s5
-; GFX1030W64-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1030W64-NEXT: s_mul_i32 s5, s10, s0
-; GFX1030W64-NEXT: s_mul_hi_u32 s4, s10, s0
-; GFX1030W64-NEXT: s_mul_hi_u32 s6, s11, s0
-; GFX1030W64-NEXT: s_mul_i32 s0, s11, s0
-; GFX1030W64-NEXT: s_mul_hi_u32 s7, s10, s1
-; GFX1030W64-NEXT: s_mul_hi_u32 s12, s11, s1
-; GFX1030W64-NEXT: s_mul_i32 s1, s11, s1
-; GFX1030W64-NEXT: s_add_u32 s5, s7, s5
-; GFX1030W64-NEXT: s_addc_u32 s4, 0, s4
-; GFX1030W64-NEXT: s_add_u32 s1, s5, s1
-; GFX1030W64-NEXT: s_addc_u32 s1, s4, s12
-; GFX1030W64-NEXT: s_addc_u32 s4, s6, 0
-; GFX1030W64-NEXT: s_add_u32 s6, s1, s0
-; GFX1030W64-NEXT: s_addc_u32 s7, 0, s4
-; GFX1030W64-NEXT: s_mul_hi_u32 s0, s2, s6
-; GFX1030W64-NEXT: s_mul_i32 s1, s2, s7
-; GFX1030W64-NEXT: s_mul_i32 s5, s2, s6
-; GFX1030W64-NEXT: s_add_i32 s12, s0, s1
-; GFX1030W64-NEXT: v_sub_co_u32 v0, s[0:1], s10, s5
-; GFX1030W64-NEXT: s_mul_i32 s4, s3, s6
-; GFX1030W64-NEXT: s_add_i32 s12, s12, s4
-; GFX1030W64-NEXT: v_sub_co_u32 v1, s[4:5], v0, s2
-; GFX1030W64-NEXT: s_sub_i32 s13, s11, s12
-; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1030W64-NEXT: s_subb_u32 s13, s13, s3
-; GFX1030W64-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
-; GFX1030W64-NEXT: s_subb_u32 s4, s13, 0
-; GFX1030W64-NEXT: s_cmp_ge_u32 s4, s3
-; GFX1030W64-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX1030W64-NEXT: s_cselect_b32 s5, -1, 0
-; GFX1030W64-NEXT: s_cmp_eq_u32 s4, s3
-; GFX1030W64-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX1030W64-NEXT: s_add_u32 s4, s6, 1
-; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc
-; GFX1030W64-NEXT: s_addc_u32 s5, s7, 0
-; GFX1030W64-NEXT: s_add_u32 s13, s6, 2
-; GFX1030W64-NEXT: s_addc_u32 s14, s7, 0
-; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
-; GFX1030W64-NEXT: s_subb_u32 s0, s11, s12
-; GFX1030W64-NEXT: v_mov_b32_e32 v2, s13
-; GFX1030W64-NEXT: s_cmp_ge_u32 s0, s3
-; GFX1030W64-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX1030W64-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1030W64-NEXT: s_cmp_eq_u32 s0, s3
-; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX1030W64-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1030W64-NEXT: v_mov_b32_e32 v1, s14
-; GFX1030W64-NEXT: v_cndmask_b32_e64 v0, s11, v0, s[0:1]
-; GFX1030W64-NEXT: v_cndmask_b32_e32 v2, s4, v2, vcc
-; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc
-; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s7, v1, vcc
-; GFX1030W64-NEXT: v_cndmask_b32_e32 v0, s6, v2, vcc
+; GFX1030W64-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX1030W64-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W64-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1030W64-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1030W64-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1030W64-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1030W64-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1030W64-NEXT: v_add_co_u32 v4, vcc, v4, v5
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v5, vcc, 0, v6, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v3, vcc, v4, v3
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v3, vcc, v5, v7, vcc
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v8, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v2, vcc, v3, v2
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v0, vcc, v0, v2
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v3, vcc
+; GFX1030W64-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W64-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1030W64-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1030W64-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1030W64-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1030W64-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1030W64-NEXT: v_add_co_u32 v4, vcc, v4, v5
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v5, vcc, 0, v6, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v3, vcc, v4, v3
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v3, vcc, v5, v7, vcc
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v8, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v2, vcc, v3, v2
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v0, vcc, v0, v2
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v3, vcc
+; GFX1030W64-NEXT: v_mul_hi_u32 v2, s10, v0
+; GFX1030W64-NEXT: v_mul_hi_u32 v5, s11, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX1030W64-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX1030W64-NEXT: v_mul_lo_u32 v0, s11, v0
+; GFX1030W64-NEXT: v_mul_hi_u32 v6, s11, v1
+; GFX1030W64-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX1030W64-NEXT: v_add_co_u32 v2, vcc, v2, v3
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v0, vcc, v2, v0
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v0, vcc, v3, v5, vcc
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, 0, v6, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v0, vcc, v0, v1
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v2, vcc
+; GFX1030W64-NEXT: v_mul_hi_u32 v2, s2, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1030W64-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1030W64-NEXT: v_sub_co_u32 v3, vcc, s10, v3
+; GFX1030W64-NEXT: v_sub_nc_u32_e32 v4, s11, v2
+; GFX1030W64-NEXT: v_subrev_co_ci_u32_e64 v4, s[0:1], s3, v4, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v5, s[0:1], v0, 1
+; GFX1030W64-NEXT: v_add_co_ci_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX1030W64-NEXT: v_sub_co_u32 v7, s[0:1], v3, s2
+; GFX1030W64-NEXT: v_sub_co_ci_u32_e32 v2, vcc, s11, v2, vcc
+; GFX1030W64-NEXT: v_subrev_co_ci_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v7
+; GFX1030W64-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v2
+; GFX1030W64-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s3, v4
+; GFX1030W64-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX1030W64-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX1030W64-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX1030W64-NEXT: v_cmp_eq_u32_e32 vcc, s3, v4
+; GFX1030W64-NEXT: v_cndmask_b32_e64 v2, v9, v3, s[0:1]
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc
+; GFX1030W64-NEXT: v_add_co_u32 v7, vcc, v0, 2
+; GFX1030W64-NEXT: v_add_co_ci_u32_e32 v8, vcc, 0, v1, vcc
+; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc
+; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX1030W64-NEXT: s_cbranch_execnz .LBB16_3
; GFX1030W64-NEXT: .LBB16_2:
; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX1030W64-NEXT: s_sub_i32 s1, 0, s2
+; GFX1030W64-NEXT: s_sub_i32 s0, 0, s2
; GFX1030W64-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1030W64-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1030W64-NEXT: s_mul_i32 s1, s1, s0
-; GFX1030W64-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX1030W64-NEXT: s_add_i32 s0, s0, s1
-; GFX1030W64-NEXT: s_mul_hi_u32 s0, s10, s0
-; GFX1030W64-NEXT: s_mul_i32 s1, s0, s2
-; GFX1030W64-NEXT: s_add_i32 s3, s0, 1
-; GFX1030W64-NEXT: s_sub_i32 s1, s10, s1
-; GFX1030W64-NEXT: s_sub_i32 s4, s1, s2
-; GFX1030W64-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1030W64-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1030W64-NEXT: s_cselect_b32 s1, s4, s1
-; GFX1030W64-NEXT: s_add_i32 s3, s0, 1
-; GFX1030W64-NEXT: s_cmp_ge_u32 s1, s2
-; GFX1030W64-NEXT: s_mov_b32 s1, 0
-; GFX1030W64-NEXT: s_cselect_b32 s0, s3, s0
-; GFX1030W64-NEXT: v_mov_b32_e32 v0, s0
-; GFX1030W64-NEXT: v_mov_b32_e32 v1, s1
+; GFX1030W64-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX1030W64-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1030W64-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX1030W64-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030W64-NEXT: v_sub_nc_u32_e32 v1, s10, v1
+; GFX1030W64-NEXT: v_subrev_nc_u32_e32 v3, s2, v1
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v1
+; GFX1030W64-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX1030W64-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX1030W64-NEXT: .LBB16_3:
; GFX1030W64-NEXT: v_mov_b32_e32 v2, 0
; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
@@ -2742,8 +2648,8 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX11-NEXT: ; %bb.1:
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX11-NEXT: s_sub_u32 s5, 0, s2
-; GFX11-NEXT: s_subb_u32 s6, 0, s3
+; GFX11-NEXT: s_sub_u32 s0, 0, s2
+; GFX11-NEXT: s_subb_u32 s1, 0, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0
; GFX11-NEXT: v_rcp_f32_e32 v0, v0
@@ -2757,147 +2663,147 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
-; GFX11-NEXT: s_mul_i32 s7, s5, s0
-; GFX11-NEXT: s_mul_hi_u32 s13, s5, s1
-; GFX11-NEXT: s_mul_i32 s12, s6, s1
-; GFX11-NEXT: s_add_i32 s7, s13, s7
-; GFX11-NEXT: s_mul_i32 s14, s5, s1
-; GFX11-NEXT: s_add_i32 s7, s7, s12
-; GFX11-NEXT: s_mul_hi_u32 s13, s1, s14
-; GFX11-NEXT: s_mul_hi_u32 s15, s0, s14
-; GFX11-NEXT: s_mul_i32 s12, s0, s14
-; GFX11-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX11-NEXT: s_mul_i32 s1, s1, s7
-; GFX11-NEXT: s_mul_hi_u32 s16, s0, s7
-; GFX11-NEXT: s_add_u32 s1, s13, s1
-; GFX11-NEXT: s_addc_u32 s13, 0, s14
-; GFX11-NEXT: s_add_u32 s1, s1, s12
-; GFX11-NEXT: s_mul_i32 s7, s0, s7
-; GFX11-NEXT: s_addc_u32 s1, s13, s15
-; GFX11-NEXT: s_addc_u32 s12, s16, 0
-; GFX11-NEXT: s_add_u32 s1, s1, s7
-; GFX11-NEXT: s_addc_u32 s7, 0, s12
-; GFX11-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: s_addc_u32 s0, s0, s7
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
-; GFX11-NEXT: s_mul_i32 s7, s5, s0
-; GFX11-NEXT: s_mul_hi_u32 s12, s5, s1
-; GFX11-NEXT: s_mul_i32 s6, s6, s1
-; GFX11-NEXT: s_add_i32 s7, s12, s7
-; GFX11-NEXT: s_mul_i32 s5, s5, s1
-; GFX11-NEXT: s_add_i32 s7, s7, s6
-; GFX11-NEXT: s_mul_hi_u32 s12, s0, s5
-; GFX11-NEXT: s_mul_i32 s13, s0, s5
-; GFX11-NEXT: s_mul_hi_u32 s5, s1, s5
-; GFX11-NEXT: s_mul_hi_u32 s14, s1, s7
-; GFX11-NEXT: s_mul_i32 s1, s1, s7
-; GFX11-NEXT: s_mul_hi_u32 s6, s0, s7
-; GFX11-NEXT: s_add_u32 s1, s5, s1
-; GFX11-NEXT: s_addc_u32 s5, 0, s14
-; GFX11-NEXT: s_add_u32 s1, s1, s13
-; GFX11-NEXT: s_mul_i32 s7, s0, s7
-; GFX11-NEXT: s_addc_u32 s1, s5, s12
-; GFX11-NEXT: s_addc_u32 s5, s6, 0
-; GFX11-NEXT: s_add_u32 s1, s1, s7
-; GFX11-NEXT: s_addc_u32 s5, 0, s5
-; GFX11-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: s_addc_u32 s0, s0, s5
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
-; GFX11-NEXT: s_mul_i32 s6, s10, s0
-; GFX11-NEXT: s_mul_hi_u32 s5, s10, s0
-; GFX11-NEXT: s_mul_hi_u32 s7, s11, s0
-; GFX11-NEXT: s_mul_i32 s0, s11, s0
-; GFX11-NEXT: s_mul_hi_u32 s12, s10, s1
-; GFX11-NEXT: s_mul_hi_u32 s13, s11, s1
-; GFX11-NEXT: s_mul_i32 s1, s11, s1
-; GFX11-NEXT: s_add_u32 s6, s12, s6
-; GFX11-NEXT: s_addc_u32 s5, 0, s5
-; GFX11-NEXT: s_add_u32 s1, s6, s1
-; GFX11-NEXT: s_addc_u32 s1, s5, s13
-; GFX11-NEXT: s_addc_u32 s5, s7, 0
-; GFX11-NEXT: s_add_u32 s1, s1, s0
-; GFX11-NEXT: s_addc_u32 s5, 0, s5
-; GFX11-NEXT: s_mul_hi_u32 s0, s2, s1
-; GFX11-NEXT: s_mul_i32 s7, s2, s5
-; GFX11-NEXT: s_mul_i32 s12, s2, s1
-; GFX11-NEXT: s_add_i32 s0, s0, s7
-; GFX11-NEXT: v_sub_co_u32 v0, s7, s10, s12
-; GFX11-NEXT: s_mul_i32 s6, s3, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s0, s0, s6
-; GFX11-NEXT: v_sub_co_u32 v1, s12, v0, s2
-; GFX11-NEXT: s_sub_i32 s6, s11, s0
-; GFX11-NEXT: s_cmp_lg_u32 s7, 0
-; GFX11-NEXT: s_subb_u32 s6, s6, s3
-; GFX11-NEXT: s_cmp_lg_u32 s12, 0
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
-; GFX11-NEXT: s_subb_u32 s6, s6, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s6, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX11-NEXT: s_cselect_b32 s12, -1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s6, s3
-; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX11-NEXT: s_add_u32 s6, s1, 1
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX11-NEXT: s_addc_u32 s12, s5, 0
-; GFX11-NEXT: s_add_u32 s13, s1, 2
-; GFX11-NEXT: s_addc_u32 s14, s5, 0
-; GFX11-NEXT: v_mov_b32_e32 v2, s13
-; GFX11-NEXT: s_cmp_lg_u32 s7, 0
-; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0
-; GFX11-NEXT: s_subb_u32 s0, s11, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_ge_u32 s0, s3
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX11-NEXT: s_cselect_b32 s7, -1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s0, s3
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT: s_cselect_b32 s0, -1, 0
-; GFX11-NEXT: v_mov_b32_e32 v1, s14
-; GFX11-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0
-; GFX11-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo
+; GFX11-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX11-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX11-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX11-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX11-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX11-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX11-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX11-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX11-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX11-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX11-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX11-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX11-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX11-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_hi_u32 v2, s10, v0
+; GFX11-NEXT: v_mul_hi_u32 v5, s11, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, s10, v1
+; GFX11-NEXT: v_mul_hi_u32 v4, s10, v1
+; GFX11-NEXT: v_mul_lo_u32 v0, s11, v0
+; GFX11-NEXT: v_mul_hi_u32 v6, s11, v1
+; GFX11-NEXT: v_mul_lo_u32 v1, s11, v1
+; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v3
+; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
+; GFX11-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v3, v5, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v1
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mul_hi_u32 v2, s2, v0
+; GFX11-NEXT: v_mul_lo_u32 v4, s3, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, s2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX11-NEXT: v_mul_lo_u32 v3, s2, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_co_u32 v3, vcc_lo, s10, v3
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, s11, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_co_ci_u32_e64 v4, s0, s3, v4, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v5, s0, v0, 1
+; GFX11-NEXT: v_add_co_ci_u32_e64 v6, s0, 0, v1, s0
+; GFX11-NEXT: v_sub_co_u32 v7, s0, v3, s2
+; GFX11-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
+; GFX11-NEXT: v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v7
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s3, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc_lo
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, s3, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v9, v3, s0
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v0, 2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v5, v7 :: v_dual_cndmask_b32 v4, v6, v8
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB16_3
; GFX11-NEXT: .LBB16_2:
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s1, 0, s2
+; GFX11-NEXT: s_sub_i32 s0, 0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: s_mul_i32 s1, s1, s0
-; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s0, s0, s1
-; GFX11-NEXT: s_mul_hi_u32 s0, s10, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_i32 s1, s0, s2
-; GFX11-NEXT: s_add_i32 s3, s0, 1
-; GFX11-NEXT: s_sub_i32 s1, s10, s1
-; GFX11-NEXT: s_sub_i32 s4, s1, s2
-; GFX11-NEXT: s_cmp_ge_u32 s1, s2
-; GFX11-NEXT: s_cselect_b32 s0, s3, s0
-; GFX11-NEXT: s_cselect_b32 s1, s4, s1
-; GFX11-NEXT: s_add_i32 s3, s0, 1
-; GFX11-NEXT: s_cmp_ge_u32 s1, s2
-; GFX11-NEXT: s_mov_b32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s0, s3, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_hi_u32 v0, s10, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_lo_u32 v1, v0, s2
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, s10, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s2, v1
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-NEXT: .LBB16_3:
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[8:9]
diff --git a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
index 7ce69fe2f4989..6ede57fb92f33 100644
--- a/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
@@ -368,13 +368,12 @@ define amdgpu_kernel void @loop_arg_0(ptr addrspace(3) %ptr, i32 %n) nounwind {
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_mov_b32 m0, -1
; GCN-NEXT: ds_read_u8 v0, v0
-; GCN-NEXT: s_load_dword s4, s[4:5], 0x9
+; GCN-NEXT: s_load_dword s0, s[4:5], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_bitcmp1_b32 s0, 0
-; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], -1
-; GCN-NEXT: s_add_i32 s0, s4, 0x80
+; GCN-NEXT: v_and_b32_e32 v0, 1, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT: s_xor_b64 s[2:3], vcc, -1
+; GCN-NEXT: s_addk_i32 s0, 0x80
; GCN-NEXT: s_and_b64 vcc, exec, s[2:3]
; GCN-NEXT: .LBB4_1: ; %for.body
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
@@ -404,11 +403,10 @@ define amdgpu_kernel void @loop_arg_0(ptr addrspace(3) %ptr, i32 %n) nounwind {
; GCN_DBG-NEXT: v_mov_b32_e32 v0, 0
; GCN_DBG-NEXT: s_mov_b32 m0, -1
; GCN_DBG-NEXT: ds_read_u8 v0, v0
+; GCN_DBG-NEXT: ; implicit-def: $sgpr0
; GCN_DBG-NEXT: s_waitcnt lgkmcnt(0)
-; GCN_DBG-NEXT: v_readfirstlane_b32 s0, v0
-; GCN_DBG-NEXT: s_and_b32 s0, 1, s0
-; GCN_DBG-NEXT: s_cmp_eq_u32 s0, 1
-; GCN_DBG-NEXT: s_cselect_b64 s[0:1], -1, 0
+; GCN_DBG-NEXT: v_and_b32_e64 v0, 1, v0
+; GCN_DBG-NEXT: v_cmp_eq_u32_e64 s[0:1], v0, 1
; GCN_DBG-NEXT: s_mov_b64 s[2:3], -1
; GCN_DBG-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GCN_DBG-NEXT: v_writelane_b32 v2, s0, 1
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
index 23fbd91c35a5b..05ca18a8f9a47 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
@@ -709,19 +709,16 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: flat_load_ubyte v0, v[0:1]
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_readfirstlane_b32 s2, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s3, v0
-; VI-NEXT: s_lshl_b32 s2, s2, 8
-; VI-NEXT: s_or_b32 s2, s2, s3
-; VI-NEXT: s_lshl_b32 s3, s2, 16
-; VI-NEXT: s_and_b32 s2, s2, 0xffff
-; VI-NEXT: s_flbit_i32_b32 s3, s3
-; VI-NEXT: s_cmp_lg_u32 s2, 0
-; VI-NEXT: s_cselect_b32 s2, s3, 32
+; VI-NEXT: v_or_b32_e32 v0, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; VI-NEXT: v_ffbh_u32_e32 v1, v1
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
index c4a742f4bf08d..c9dafc1deba7d 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_undef.ll
@@ -1557,20 +1557,18 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: flat_load_ubyte v0, v[0:1]
+; VI-NEXT: v_mov_b32_e32 v1, 0xffff
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_readfirstlane_b32 s2, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s3, v0
-; VI-NEXT: s_lshl_b32 s2, s2, 8
-; VI-NEXT: s_or_b32 s2, s2, s3
-; VI-NEXT: s_or_b32 s3, s2, 0x10000
-; VI-NEXT: s_and_b32 s2, s2, 0xffff
-; VI-NEXT: s_ff1_i32_b32 s3, s3
-; VI-NEXT: s_cmp_lg_u32 s2, 0
-; VI-NEXT: s_cselect_b32 s2, s3, 0xffff
+; VI-NEXT: v_or_b32_e32 v0, v2, v0
+; VI-NEXT: v_or_b32_e32 v2, 0x10000, v0
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; VI-NEXT: v_ffbl_b32_e32 v2, v2
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index 22bf6cd0c8ff2..a72e74167d564 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -729,264 +729,388 @@ define amdgpu_kernel void @bit128_extelt(ptr addrspace(1) %out, i32 %sel) {
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s2, 1
; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s2, 2
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 3
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 4
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 5
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 6
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 7
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 8
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 9
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 10
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 11
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 12
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 13
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 14
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 15
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 16
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 17
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 18
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 19
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 20
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 21
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 22
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 23
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 24
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 25
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 26
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 27
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 28
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 29
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 30
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 31
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 32
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 33
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 34
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 35
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 36
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 37
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 38
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 39
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 40
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 41
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 42
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 43
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 44
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 45
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 46
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 47
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 48
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 49
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 50
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 51
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 52
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 53
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 54
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 55
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 56
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 57
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 58
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 59
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 60
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 61
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 62
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 63
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmp_lg_u32 s2, 64
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x41
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x42
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x43
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x44
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x45
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x46
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x47
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x48
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x49
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4a
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4b
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4c
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4d
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4e
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x4f
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x50
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x51
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x52
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x53
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x54
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x55
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x56
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x57
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x58
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x59
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5a
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5b
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5c
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5d
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5e
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x5f
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x60
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x61
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x62
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x63
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x64
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x65
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x66
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x67
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x68
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x69
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6a
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6b
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6c
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6d
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6e
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x6f
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x70
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x71
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x72
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x73
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x74
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x75
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x76
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x77
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x78
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x79
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7a
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7b
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7c
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7d
-; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7e
-; GCN-NEXT: s_cselect_b32 s3, s3, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
; GCN-NEXT: s_cmpk_lg_i32 s2, 0x7f
-; GCN-NEXT: s_cselect_b32 s2, s3, 0
-; GCN-NEXT: s_and_b32 s2, s2, 1
+; GCN-NEXT: v_cndmask_b32_e32 v0, 1, v0, vcc
+; GCN-NEXT: s_cselect_b64 vcc, -1, 0
+; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-NEXT: v_and_b32_e32 v2, 1, v0
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: flat_store_dword v[0:1], v2
; GCN-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 620273a360439..7e4b1259db3aa 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -1775,42 +1775,44 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; SI-NEXT: s_cmp_lg_u32 s2, 0
; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
-; SI-NEXT: v_readfirstlane_b32 s2, v1
-; SI-NEXT: s_bfe_u32 s5, s3, 0xb0014
-; SI-NEXT: s_or_b32 s2, s6, s2
-; SI-NEXT: s_sub_i32 s6, 0x3f1, s5
-; SI-NEXT: v_med3_i32 v1, s6, 0, 13
-; SI-NEXT: s_or_b32 s4, s2, 0x1000
-; SI-NEXT: v_readfirstlane_b32 s6, v1
-; SI-NEXT: s_lshr_b32 s7, s4, s6
-; SI-NEXT: s_lshl_b32 s6, s7, s6
-; SI-NEXT: s_cmp_lg_u32 s6, s4
-; SI-NEXT: s_cselect_b32 s4, 1, 0
-; SI-NEXT: s_addk_i32 s5, 0xfc10
-; SI-NEXT: s_lshl_b32 s6, s5, 12
-; SI-NEXT: s_or_b32 s4, s7, s4
-; SI-NEXT: s_or_b32 s6, s2, s6
-; SI-NEXT: s_cmp_lt_i32 s5, 1
-; SI-NEXT: s_cselect_b32 s4, s4, s6
-; SI-NEXT: s_and_b32 s6, s4, 7
-; SI-NEXT: s_cmp_gt_i32 s6, 5
-; SI-NEXT: s_cselect_b32 s7, 1, 0
-; SI-NEXT: s_cmp_eq_u32 s6, 3
-; SI-NEXT: s_cselect_b32 s6, 1, 0
-; SI-NEXT: s_or_b32 s6, s6, s7
-; SI-NEXT: s_lshr_b32 s4, s4, 2
-; SI-NEXT: s_add_i32 s4, s4, s6
-; SI-NEXT: s_cmp_lt_i32 s5, 31
-; SI-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; SI-NEXT: s_cmp_lg_u32 s2, 0
-; SI-NEXT: s_movk_i32 s2, 0x7e00
-; SI-NEXT: s_cselect_b32 s2, s2, 0x7c00
-; SI-NEXT: s_cmpk_eq_i32 s5, 0x40f
-; SI-NEXT: s_cselect_b32 s2, s2, s4
-; SI-NEXT: s_lshr_b32 s3, s3, 16
-; SI-NEXT: s_and_b32 s3, s3, 0x8000
-; SI-NEXT: s_or_b32 s2, s3, s2
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s2
+; SI-NEXT: s_bfe_u32 s2, s3, 0xb0014
+; SI-NEXT: v_or_b32_e32 v1, s6, v1
+; SI-NEXT: s_sub_i32 s4, 0x3f1, s2
+; SI-NEXT: v_or_b32_e32 v2, 0x1000, v1
+; SI-NEXT: v_med3_i32 v3, s4, 0, 13
+; SI-NEXT: v_lshr_b32_e32 v4, v2, v3
+; SI-NEXT: v_lshl_b32_e32 v3, v4, v3
+; SI-NEXT: s_addk_i32 s2, 0xfc10
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, v3, v2
+; SI-NEXT: s_lshl_b32 s4, s2, 12
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; SI-NEXT: s_cmp_lt_i32 s2, 1
+; SI-NEXT: v_or_b32_e32 v2, v4, v2
+; SI-NEXT: v_or_b32_e32 v3, s4, v1
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_and_b32_e32 v3, 7, v2
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v3
+; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v3
+; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; SI-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; SI-NEXT: s_cmp_lt_i32 s2, 31
+; SI-NEXT: v_mov_b32_e32 v3, 0x7c00
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT: v_mov_b32_e32 v4, 0x7e00
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; SI-NEXT: s_cmpk_eq_i32 s2, 0x40f
+; SI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: s_lshr_b32 s2, s3, 16
+; SI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; SI-NEXT: s_and_b32 s2, s2, 0x8000
+; SI-NEXT: v_or_b32_e32 v1, s2, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_brev_b32 s2, -2
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: v_bfi_b32 v0, s2, v1, v0
@@ -1833,42 +1835,43 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; VI-NEXT: s_cmp_lg_u32 s0, 0
; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; VI-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; VI-NEXT: v_readfirstlane_b32 s0, v2
-; VI-NEXT: s_sub_i32 s3, 0x3f1, s2
-; VI-NEXT: s_or_b32 s0, s5, s0
-; VI-NEXT: v_med3_i32 v2, s3, 0, 13
-; VI-NEXT: s_or_b32 s1, s0, 0x1000
-; VI-NEXT: v_readfirstlane_b32 s3, v2
-; VI-NEXT: s_lshr_b32 s5, s1, s3
-; VI-NEXT: s_lshl_b32 s3, s5, s3
-; VI-NEXT: s_cmp_lg_u32 s3, s1
-; VI-NEXT: s_cselect_b32 s1, 1, 0
-; VI-NEXT: s_addk_i32 s2, 0xfc10
-; VI-NEXT: s_lshl_b32 s3, s2, 12
-; VI-NEXT: s_or_b32 s1, s5, s1
-; VI-NEXT: s_or_b32 s3, s0, s3
-; VI-NEXT: s_cmp_lt_i32 s2, 1
-; VI-NEXT: s_cselect_b32 s1, s1, s3
-; VI-NEXT: s_and_b32 s3, s1, 7
-; VI-NEXT: s_cmp_gt_i32 s3, 5
-; VI-NEXT: s_cselect_b32 s5, 1, 0
-; VI-NEXT: s_cmp_eq_u32 s3, 3
-; VI-NEXT: s_cselect_b32 s3, 1, 0
-; VI-NEXT: s_or_b32 s3, s3, s5
-; VI-NEXT: s_lshr_b32 s1, s1, 2
-; VI-NEXT: s_add_i32 s1, s1, s3
-; VI-NEXT: s_cmp_lt_i32 s2, 31
-; VI-NEXT: s_cselect_b32 s1, s1, 0x7c00
-; VI-NEXT: s_cmp_lg_u32 s0, 0
-; VI-NEXT: s_movk_i32 s0, 0x7e00
-; VI-NEXT: s_cselect_b32 s0, s0, 0x7c00
-; VI-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; VI-NEXT: s_cselect_b32 s0, s0, s1
-; VI-NEXT: s_movk_i32 s1, 0x7fff
-; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: s_bfe_u32 s0, s3, 0xb0014
+; VI-NEXT: v_or_b32_e32 v2, s5, v2
+; VI-NEXT: s_sub_i32 s1, 0x3f1, s0
+; VI-NEXT: v_or_b32_e32 v3, 0x1000, v2
+; VI-NEXT: v_med3_i32 v4, s1, 0, 13
+; VI-NEXT: v_lshrrev_b32_e32 v5, v4, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, v4, v5
+; VI-NEXT: s_addk_i32 s0, 0xfc10
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3
+; VI-NEXT: s_lshl_b32 s1, s0, 12
+; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; VI-NEXT: s_cmp_lt_i32 s0, 1
+; VI-NEXT: v_or_b32_e32 v3, v5, v3
+; VI-NEXT: v_or_b32_e32 v4, s1, v2
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT: v_and_b32_e32 v4, 7, v3
+; VI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v4
+; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v4
+; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, v4, v3
+; VI-NEXT: s_cmp_lt_i32 s0, 31
+; VI-NEXT: v_mov_b32_e32 v4, 0x7c00
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT: v_mov_b32_e32 v5, 0x7e00
+; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; VI-NEXT: s_cmpk_eq_i32 s0, 0x40f
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; VI-NEXT: s_movk_i32 s0, 0x7fff
; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_bfi_b32 v2, s1, v2, v3
+; VI-NEXT: v_bfi_b32 v2, s0, v2, v3
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
;
@@ -1885,42 +1888,43 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0xb0014
-; GFX9-NEXT: v_readfirstlane_b32 s2, v1
-; GFX9-NEXT: s_sub_i32 s5, 0x3f1, s3
-; GFX9-NEXT: s_or_b32 s2, s7, s2
-; GFX9-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX9-NEXT: s_or_b32 s4, s2, 0x1000
-; GFX9-NEXT: v_readfirstlane_b32 s5, v1
-; GFX9-NEXT: s_lshr_b32 s7, s4, s5
-; GFX9-NEXT: s_lshl_b32 s5, s7, s5
-; GFX9-NEXT: s_cmp_lg_u32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, 1, 0
-; GFX9-NEXT: s_addk_i32 s3, 0xfc10
-; GFX9-NEXT: s_lshl_b32 s5, s3, 12
-; GFX9-NEXT: s_or_b32 s4, s7, s4
-; GFX9-NEXT: s_or_b32 s5, s2, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, 1
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s4, 7
-; GFX9-NEXT: s_cmp_gt_i32 s5, 5
-; GFX9-NEXT: s_cselect_b32 s7, 1, 0
-; GFX9-NEXT: s_cmp_eq_u32 s5, 3
-; GFX9-NEXT: s_cselect_b32 s5, 1, 0
-; GFX9-NEXT: s_or_b32 s5, s5, s7
-; GFX9-NEXT: s_lshr_b32 s4, s4, 2
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, 31
-; GFX9-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_movk_i32 s2, 0x7e00
-; GFX9-NEXT: s_cselect_b32 s2, s2, 0x7c00
-; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x40f
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_movk_i32 s3, 0x7fff
-; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: s_bfe_u32 s2, s3, 0xb0014
+; GFX9-NEXT: v_or_b32_e32 v1, s7, v1
+; GFX9-NEXT: s_sub_i32 s3, 0x3f1, s2
+; GFX9-NEXT: v_or_b32_e32 v2, 0x1000, v1
+; GFX9-NEXT: v_med3_i32 v3, s3, 0, 13
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, v3, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, v3, v4
+; GFX9-NEXT: s_addk_i32 s2, 0xfc10
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v3, v2
+; GFX9-NEXT: s_lshl_b32 s3, s2, 12
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: s_cmp_lt_i32 s2, 1
+; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_or_b32_e32 v3, s3, v1
+; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT: v_and_b32_e32 v3, 7, v2
+; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, 5, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; GFX9-NEXT: s_cmp_lt_i32 s2, 31
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x7c00
+; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x7e00
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x40f
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX9-NEXT: s_movk_i32 s2, 0x7fff
; GFX9-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-NEXT: v_bfi_b32 v1, s3, v1, v2
+; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v2
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
@@ -1940,45 +1944,44 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
; GFX11-TRUE16-NEXT: s_bfe_u32 s2, s3, 0xb0014
; GFX11-TRUE16-NEXT: s_sub_i32 s3, 0x3f1, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_med3_i32 v1, s3, 0, 13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v1
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s5, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_or_b32 s5, s3, 0x1000
-; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s5, s6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s7, s6
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s6, s5
-; GFX11-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-TRUE16-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-TRUE16-NEXT: s_or_b32 s5, s7, s5
-; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s6, s3, s6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, s5, v0
+; GFX11-TRUE16-NEXT: v_med3_i32 v1, s3, 0, 13
+; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s2, 12
; GFX11-TRUE16-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-TRUE16-NEXT: s_cselect_b32 s5, s5, s6
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s5, 7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s5, 2
-; GFX11-TRUE16-NEXT: s_or_b32 s6, s6, s7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, s6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x1000, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, v1, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, v1, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, s3, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-TRUE16-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-TRUE16-NEXT: s_movk_i32 s6, 0x7e00
-; GFX11-TRUE16-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-TRUE16-NEXT: s_cselect_b32 s3, s6, 0x7c00
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 7, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7e00
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, 0x7c00, v3 :: v_dual_add_nc_u32 v1, v1, v2
+; GFX11-TRUE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-TRUE16-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s3, s5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, 0x7c00, v1, vcc_lo
+; GFX11-TRUE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -2000,46 +2003,45 @@ define amdgpu_kernel void @s_copysign_out_f16_mag_f64_sign_f16(ptr addrspace(1)
; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
; GFX11-FAKE16-NEXT: s_bfe_u32 s2, s3, 0xb0014
; GFX11-FAKE16-NEXT: s_sub_i32 s3, 0x3f1, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_med3_i32 v1, s3, 0, 13
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v0
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v1
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s5, s3
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s3, 0x1000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s5, s6
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s7, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s6, s5
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-FAKE16-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-FAKE16-NEXT: s_or_b32 s5, s7, s5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-FAKE16-NEXT: s_or_b32 s6, s3, s6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, s5, v0
+; GFX11-FAKE16-NEXT: v_med3_i32 v1, s3, 0, 13
+; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s2, 12
; GFX11-FAKE16-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s5, s6
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_and_b32 s6, s5, 7
-; GFX11-FAKE16-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s5, 2
-; GFX11-FAKE16-NEXT: s_or_b32 s6, s6, s7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x1000, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, v1, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, v1, v3
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, s3, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-FAKE16-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-FAKE16-NEXT: s_movk_i32 s6, 0x7e00
-; GFX11-FAKE16-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-FAKE16-NEXT: s_cselect_b32 s3, s6, 0x7c00
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 7, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-FAKE16-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s3, s5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, s2, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, 0x7e00 :: v_dual_add_nc_u32 v1, v1, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x7c00, v1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v2, vcc_lo
+; GFX11-FAKE16-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_mov_b32 v1, 0
+; GFX11-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, s4
; GFX11-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-FAKE16-NEXT: s_endpgm
%mag.trunc = fptrunc double %mag to half
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
new file mode 100644
index 0000000000000..c98226a45a181
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll
@@ -0,0 +1,168 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
+
+; SGPR phi ends up with VGPR inputs. Make sure we do not try to
+; process a copy which has already been erased (which was already
+; inserted by the pass).
+
+define double @issue130646(i64 %arg) {
+; CHECK-LABEL: issue130646:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v2, 0
+; CHECK-NEXT: v_mov_b32_e32 v4, 0
+; CHECK-NEXT: v_mov_b32_e32 v3, 0
+; CHECK-NEXT: v_mov_b32_e32 v5, 0
+; CHECK-NEXT: s_branch .LBB0_2
+; CHECK-NEXT: .LBB0_1: ; %Flow
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; CHECK-NEXT: s_cbranch_vccz .LBB0_4
+; CHECK-NEXT: .LBB0_2: ; %for.body
+; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; CHECK-NEXT: s_mov_b64 s[4:5], -1
+; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
+; CHECK-NEXT: ; %bb.3: ; %for.body.5
+; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT: v_lshrrev_b64 v[6:7], 1, v[2:3]
+; CHECK-NEXT: v_lshrrev_b64 v[8:9], 5, v[2:3]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v7
+; CHECK-NEXT: v_or_b32_e32 v4, v4, v6
+; CHECK-NEXT: v_or_b32_e32 v6, 1, v8
+; CHECK-NEXT: v_or3_b32 v5, v5, v1, v9
+; CHECK-NEXT: v_or3_b32 v4, v4, v0, v6
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[2:3]
+; CHECK-NEXT: s_mov_b64 s[4:5], 0
+; CHECK-NEXT: s_branch .LBB0_1
+; CHECK-NEXT: .LBB0_4: ; %for.cond.cleanup
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ br label %for.body
+
+for.cond.cleanup: ; preds = %for.body
+ %cmp3.not.i.i.i = icmp eq i64 %r.0108, 0
+ br i1 %cmp3.not.i.i.i, label %cleanup, label %if.end26.i.i
+
+if.end26.i.i: ; preds = %for.cond.cleanup
+ br label %cleanup
+
+for.body: ; preds = %for.body.5, %entry
+ %current_bit.01093 = phi i64 [ 0, %entry ], [ %shr.3.7, %for.body.5 ]
+ %r.0108 = phi i64 [ 0, %entry ], [ %shl28.3.7, %for.body.5 ]
+ %shr.3 = lshr i64 %current_bit.01093, 1
+ %i = or i64 %r.0108, %shr.3
+ %i3 = or i64 %i, %arg
+ %tobool27.not.3.4 = icmp ult i64 %current_bit.01093, 1
+ br i1 %tobool27.not.3.4, label %for.cond.cleanup, label %for.body.5
+
+for.body.5: ; preds = %for.body
+ %shr.3.4 = lshr i64 %current_bit.01093, 5
+ %i6 = or i64 %shr.3.4, 1
+ %shl28.3.7 = or i64 %i6, %i3
+ %shr.3.7 = lshr i64 %current_bit.01093, 8
+ br label %for.body
+
+cleanup: ; preds = %if.end26.i.i, %for.cond.cleanup
+ ret double 0.000000e+00
+}
+
+define amdgpu_cs void @issue130119(i1 %arg) {
+; CHECK-LABEL: issue130119:
+; CHECK: ; %bb.0: ; %bb
+; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v0
+; CHECK-NEXT: s_mov_b32 s16, 0
+; CHECK-NEXT: s_mov_b64 s[4:5], 0
+; CHECK-NEXT: s_branch .LBB1_2
+; CHECK-NEXT: .LBB1_1: ; %Flow2
+; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
+; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
+; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]
+; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]
+; CHECK-NEXT: s_cbranch_execz .LBB1_10
+; CHECK-NEXT: .LBB1_2: ; %bb1
+; CHECK-NEXT: ; =>This Loop Header: Depth=1
+; CHECK-NEXT: ; Child Loop BB1_4 Depth 2
+; CHECK-NEXT: s_and_b32 s2, s16, 1
+; CHECK-NEXT: s_cmp_eq_u32 s2, 0
+; CHECK-NEXT: s_cselect_b64 s[6:7], -1, 0
+; CHECK-NEXT: s_cmp_eq_u32 s2, 1
+; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]
+; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, v0
+; CHECK-NEXT: s_mov_b64 s[10:11], 0
+; CHECK-NEXT: ; implicit-def: $sgpr8_sgpr9
+; CHECK-NEXT: s_branch .LBB1_4
+; CHECK-NEXT: .LBB1_3: ; %Flow1
+; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT: s_xor_b64 s[14:15], s[14:15], -1
+; CHECK-NEXT: s_and_b64 s[12:13], exec, s[12:13]
+; CHECK-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
+; CHECK-NEXT: s_andn2_b64 s[8:9], s[8:9], exec
+; CHECK-NEXT: s_and_b64 s[12:13], s[14:15], exec
+; CHECK-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
+; CHECK-NEXT: s_andn2_b64 exec, exec, s[10:11]
+; CHECK-NEXT: s_cbranch_execz .LBB1_8
+; CHECK-NEXT: .LBB1_4: ; %bb3
+; CHECK-NEXT: ; Parent Loop BB1_2 Depth=1
+; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
+; CHECK-NEXT: s_and_b64 vcc, exec, s[2:3]
+; CHECK-NEXT: s_mov_b64 s[14:15], s[6:7]
+; CHECK-NEXT: s_cbranch_vccnz .LBB1_6
+; CHECK-NEXT: ; %bb.5: ; %bb7
+; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT: s_mov_b64 s[14:15], -1
+; CHECK-NEXT: .LBB1_6: ; %Flow
+; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT: s_mov_b64 s[12:13], -1
+; CHECK-NEXT: s_andn2_b64 vcc, exec, s[14:15]
+; CHECK-NEXT: s_mov_b64 s[14:15], -1
+; CHECK-NEXT: s_cbranch_vccnz .LBB1_3
+; CHECK-NEXT: ; %bb.7: ; %bb8
+; CHECK-NEXT: ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT: s_mov_b64 s[14:15], 0
+; CHECK-NEXT: s_orn2_b64 s[12:13], s[0:1], exec
+; CHECK-NEXT: s_branch .LBB1_3
+; CHECK-NEXT: .LBB1_8: ; %loop.exit.guard
+; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: s_or_b64 exec, exec, s[10:11]
+; CHECK-NEXT: s_mov_b64 s[2:3], -1
+; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
+; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; CHECK-NEXT: s_cbranch_execz .LBB1_1
+; CHECK-NEXT: ; %bb.9: ; %bb10
+; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT: s_or_b32 s16, s16, 1
+; CHECK-NEXT: s_xor_b64 s[2:3], exec, -1
+; CHECK-NEXT: s_branch .LBB1_1
+; CHECK-NEXT: .LBB1_10: ; %DummyReturnBlock
+; CHECK-NEXT: s_endpgm
+bb:
+ br label %bb1
+
+bb1: ; preds = %bb10, %bb
+ %i = phi i32 [ 0, %bb ], [ %i11, %bb10 ]
+ %i2 = phi i32 [ 0, %bb ], [ %i4, %bb10 ]
+ br label %bb3
+
+bb3: ; preds = %bb8, %bb1
+ %i4 = phi i32 [ %i2, %bb1 ], [ %i9, %bb8 ]
+ %i5 = and i32 %i, 1
+ %i6 = icmp eq i32 %i5, 0
+ br i1 %i6, label %bb8, label %bb7
+
+bb7: ; preds = %bb3
+ br label %bb8
+
+bb8: ; preds = %bb7, %bb3
+ %i9 = phi i32 [ %i2, %bb3 ], [ 0, %bb7 ]
+ br i1 %arg, label %bb10, label %bb3
+
+bb10: ; preds = %bb8
+ %i11 = or i32 %i, 1
+ br label %bb1
+}
diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
new file mode 100644
index 0000000000000..9d3bd4ca7f5cd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646.mir
@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s
+---
+name: issue130646
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: issue130646
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr10
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[COPY1]], implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY2]], %bb.3, %15, %bb.4
+ ; CHECK-NEXT: S_CMP_LG_U32 1, 1, implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY]]
+ ; CHECK-NEXT: SI_RETURN implicit $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vreg_64 = PHI [[COPY4]], %bb.0, [[PHI]], %bb.1
+ ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+ ; CHECK-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[PHI1]], killed [[S_MOV_B64_]], implicit $exec
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_EQ_U64_e64_]], implicit-def $scc
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+ ; CHECK-NEXT: S_BRANCH %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHRREV_B64_e64 [[COPY3]], [[PHI1]], implicit $exec
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[V_LSHRREV_B64_e64_]].sub1
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_1:%[0-9]+]]:vreg_64 = V_LSHRREV_B64_e64 killed [[COPY5]], [[PHI1]], implicit $exec
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[V_LSHRREV_B64_e64_1]].sub1
+ ; CHECK-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 killed [[COPY6]], [[COPY3]], implicit $exec
+ ; CHECK-NEXT: [[V_LSHRREV_B64_e64_2:%[0-9]+]]:vreg_64 = V_LSHRREV_B64_e64 killed [[V_OR_B32_e64_]], [[PHI1]], implicit $exec
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[V_LSHRREV_B64_e64_2]], implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ bb.0:
+ liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr10
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:sreg_64 = COPY $sgpr8_sgpr9
+ %2:vreg_64 = COPY $vgpr1_vgpr2
+ %3:sreg_32 = COPY $sgpr10
+ S_BRANCH %bb.3
+
+ bb.1:
+ %4:sreg_64 = PHI %2, %bb.3, %5, %bb.4
+ S_CMP_LG_U32 1, 1, implicit-def $scc
+ S_CBRANCH_SCC1 %bb.3, implicit $scc
+ S_BRANCH %bb.2
+
+ bb.2:
+ $vgpr0 = COPY %0
+ SI_RETURN implicit $vgpr0
+
+ bb.3:
+ %6:sreg_64 = PHI %1, %bb.0, %4, %bb.1
+ %7:sreg_64 = S_MOV_B64 0
+ S_CMP_EQ_U64 %6, killed %7, implicit-def $scc
+ S_CBRANCH_SCC1 %bb.1, implicit $scc
+ S_BRANCH %bb.4
+
+ bb.4:
+ %8:sreg_64 = S_LSHR_B64 %6, %3, implicit-def dead $scc
+ %9:sreg_32 = COPY %8.sub1
+ %10:sreg_64 = S_LSHR_B64 %6, killed %9, implicit-def dead $scc
+ %11:sreg_32 = COPY %10.sub1
+ %12:sreg_32 = S_OR_B32 killed %11, %3, implicit-def dead $scc
+ %5:sreg_64 = S_LSHR_B64 %6, killed %12, implicit-def dead $scc
+ S_BRANCH %bb.1
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index d1403b6c1a01d..67d8da59efdec 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -97,53 +97,54 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_movk_i32 s2, 0x7e00
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_lshr_b32 s0, s7, 8
-; SI-NEXT: s_and_b32 s1, s7, 0x1ff
-; SI-NEXT: s_and_b32 s8, s0, 0xffe
-; SI-NEXT: s_or_b32 s0, s1, s6
-; SI-NEXT: s_cmp_lg_u32 s0, 0
-; SI-NEXT: s_cselect_b64 s[0:1], -1, 0
-; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
-; SI-NEXT: s_bfe_u32 s0, s7, 0xb0014
-; SI-NEXT: v_readfirstlane_b32 s1, v0
-; SI-NEXT: s_sub_i32 s6, 0x3f1, s0
-; SI-NEXT: s_or_b32 s1, s8, s1
-; SI-NEXT: v_med3_i32 v0, s6, 0, 13
-; SI-NEXT: s_or_b32 s6, s1, 0x1000
-; SI-NEXT: v_readfirstlane_b32 s8, v0
-; SI-NEXT: s_lshr_b32 s9, s6, s8
-; SI-NEXT: s_lshl_b32 s8, s9, s8
-; SI-NEXT: s_cmp_lg_u32 s8, s6
-; SI-NEXT: s_cselect_b32 s6, 1, 0
-; SI-NEXT: s_addk_i32 s0, 0xfc10
-; SI-NEXT: s_or_b32 s6, s9, s6
-; SI-NEXT: s_lshl_b32 s8, s0, 12
-; SI-NEXT: s_or_b32 s8, s1, s8
-; SI-NEXT: s_cmp_lt_i32 s0, 1
-; SI-NEXT: s_cselect_b32 s6, s6, s8
-; SI-NEXT: s_and_b32 s8, s6, 7
-; SI-NEXT: s_cmp_gt_i32 s8, 5
-; SI-NEXT: s_cselect_b32 s9, 1, 0
-; SI-NEXT: s_cmp_eq_u32 s8, 3
-; SI-NEXT: s_cselect_b32 s8, 1, 0
-; SI-NEXT: s_lshr_b32 s6, s6, 2
-; SI-NEXT: s_or_b32 s8, s8, s9
-; SI-NEXT: s_add_i32 s6, s6, s8
-; SI-NEXT: s_cmp_lt_i32 s0, 31
-; SI-NEXT: s_cselect_b32 s6, s6, 0x7c00
-; SI-NEXT: s_cmp_lg_u32 s1, 0
-; SI-NEXT: s_cselect_b32 s1, s2, 0x7c00
-; SI-NEXT: s_cmpk_eq_i32 s0, 0x40f
-; SI-NEXT: s_cselect_b32 s0, s1, s6
-; SI-NEXT: s_lshr_b32 s1, s7, 16
-; SI-NEXT: s_and_b32 s1, s1, 0x8000
-; SI-NEXT: s_or_b32 s6, s1, s0
; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, 0x7c00
+; SI-NEXT: v_mov_b32_e32 v1, 0x7e00
+; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5
-; SI-NEXT: v_mov_b32_e32 v0, s6
+; SI-NEXT: s_lshr_b32 s4, s7, 8
+; SI-NEXT: s_and_b32 s5, s7, 0x1ff
+; SI-NEXT: s_and_b32 s8, s4, 0xffe
+; SI-NEXT: s_or_b32 s4, s5, s6
+; SI-NEXT: s_cmp_lg_u32 s4, 0
+; SI-NEXT: s_cselect_b64 s[4:5], -1, 0
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
+; SI-NEXT: s_bfe_u32 s4, s7, 0xb0014
+; SI-NEXT: v_or_b32_e32 v2, s8, v2
+; SI-NEXT: s_sub_i32 s5, 0x3f1, s4
+; SI-NEXT: s_addk_i32 s4, 0xfc10
+; SI-NEXT: v_or_b32_e32 v3, 0x1000, v2
+; SI-NEXT: v_med3_i32 v4, s5, 0, 13
+; SI-NEXT: s_lshl_b32 s5, s4, 12
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
+; SI-NEXT: v_lshr_b32_e32 v5, v3, v4
+; SI-NEXT: v_or_b32_e32 v2, s5, v2
+; SI-NEXT: s_cmp_lt_i32 s4, 1
+; SI-NEXT: v_lshl_b32_e32 v4, v5, v4
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, v4, v3
+; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; SI-NEXT: v_or_b32_e32 v3, v5, v3
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: s_cmp_lt_i32 s4, 31
+; SI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; SI-NEXT: v_and_b32_e32 v3, 7, v2
+; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 5, v3
+; SI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 3, v3
+; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; SI-NEXT: v_or_b32_e32 v3, v3, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, v3, v2
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: s_cmpk_eq_i32 s4, 0x40f
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: s_lshr_b32 s4, s7, 16
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_or_b32_e32 v0, s4, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
@@ -162,42 +163,43 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; VI-SAFE-SDAG-NEXT: s_mov_b32 s1, s5
; VI-SAFE-SDAG-NEXT: s_cselect_b64 s[4:5], -1, 0
; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; VI-SAFE-SDAG-NEXT: v_readfirstlane_b32 s4, v0
-; VI-SAFE-SDAG-NEXT: s_bfe_u32 s6, s7, 0xb0014
-; VI-SAFE-SDAG-NEXT: s_or_b32 s4, s8, s4
-; VI-SAFE-SDAG-NEXT: s_sub_i32 s8, 0x3f1, s6
-; VI-SAFE-SDAG-NEXT: v_med3_i32 v0, s8, 0, 13
-; VI-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
-; VI-SAFE-SDAG-NEXT: v_readfirstlane_b32 s8, v0
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s9, s5, s8
-; VI-SAFE-SDAG-NEXT: s_lshl_b32 s8, s9, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s8, s5
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
-; VI-SAFE-SDAG-NEXT: s_addk_i32 s6, 0xfc10
-; VI-SAFE-SDAG-NEXT: s_lshl_b32 s8, s6, 12
-; VI-SAFE-SDAG-NEXT: s_or_b32 s5, s9, s5
-; VI-SAFE-SDAG-NEXT: s_or_b32 s8, s4, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s6, 1
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s8
-; VI-SAFE-SDAG-NEXT: s_and_b32 s8, s5, 7
-; VI-SAFE-SDAG-NEXT: s_cmp_gt_i32 s8, 5
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s9, 1, 0
-; VI-SAFE-SDAG-NEXT: s_cmp_eq_u32 s8, 3
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s8, 1, 0
-; VI-SAFE-SDAG-NEXT: s_or_b32 s8, s8, s9
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; VI-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s8
-; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s6, 31
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; VI-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; VI-SAFE-SDAG-NEXT: s_movk_i32 s4, 0x7e00
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s4, s4, 0x7c00
-; VI-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s6, 0x40f
-; VI-SAFE-SDAG-NEXT: s_cselect_b32 s4, s4, s5
-; VI-SAFE-SDAG-NEXT: s_lshr_b32 s5, s7, 16
-; VI-SAFE-SDAG-NEXT: s_and_b32 s5, s5, 0x8000
-; VI-SAFE-SDAG-NEXT: s_or_b32 s4, s5, s4
-; VI-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; VI-SAFE-SDAG-NEXT: s_bfe_u32 s4, s7, 0xb0014
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s8, v0
+; VI-SAFE-SDAG-NEXT: s_sub_i32 s5, 0x3f1, s4
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v1, 0x1000, v0
+; VI-SAFE-SDAG-NEXT: v_med3_i32 v2, s5, 0, 13
+; VI-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v3, v2, v1
+; VI-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v2, v2, v3
+; VI-SAFE-SDAG-NEXT: s_addk_i32 s4, 0xfc10
+; VI-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v2, v1
+; VI-SAFE-SDAG-NEXT: s_lshl_b32 s5, s4, 12
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s4, 1
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v1, v3, v1
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v2, s5, v0
+; VI-SAFE-SDAG-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; VI-SAFE-SDAG-NEXT: v_and_b32_e32 v2, 7, v1
+; VI-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v2
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; VI-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; VI-SAFE-SDAG-NEXT: v_add_u32_e32 v1, vcc, v2, v1
+; VI-SAFE-SDAG-NEXT: s_cmp_lt_i32 s4, 31
+; VI-SAFE-SDAG-NEXT: v_mov_b32_e32 v2, 0x7c00
+; VI-SAFE-SDAG-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; VI-SAFE-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00
+; VI-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; VI-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s4, 0x40f
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; VI-SAFE-SDAG-NEXT: s_cselect_b64 vcc, -1, 0
+; VI-SAFE-SDAG-NEXT: s_lshr_b32 s4, s7, 16
+; VI-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; VI-SAFE-SDAG-NEXT: s_and_b32 s4, s4, 0x8000
+; VI-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s4, v0
; VI-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-SAFE-SDAG-NEXT: s_endpgm
;
@@ -287,42 +289,42 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s2, -1, 0
; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
; GFX10-SAFE-SDAG-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; GFX10-SAFE-SDAG-NEXT: s_sub_i32 s5, 0x3f1, s2
-; GFX10-SAFE-SDAG-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s5, v0
-; GFX10-SAFE-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s4, s4, s5
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s7, s5, s6
-; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s6, s7, s6
-; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s6, s5
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s4, v0
+; GFX10-SAFE-SDAG-NEXT: s_sub_i32 s4, 0x3f1, s2
; GFX10-SAFE-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s5, s7, s5
-; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX10-SAFE-SDAG-NEXT: v_med3_i32 v1, s4, 0, 13
+; GFX10-SAFE-SDAG-NEXT: s_lshl_b32 s4, s2, 12
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v2, 0x1000, v0
; GFX10-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 1
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s6, s5, 7
-; GFX10-SAFE-SDAG-NEXT: s_cmp_gt_i32 s6, 5
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s7, 1, 0
-; GFX10-SAFE-SDAG-NEXT: s_cmp_eq_u32 s6, 3
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s6, 1, 0
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s6, s6, s7
-; GFX10-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s6
+; GFX10-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v3, v1, v2
+; GFX10-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v1, v1, v3
+; GFX10-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v2
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v2, s4, v0
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 31
-; GFX10-SAFE-SDAG-NEXT: s_movk_i32 s6, 0x7e00
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX10-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s4, s6, 0x7c00
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: v_and_b32_e32 v2, 7, v1
+; GFX10-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; GFX10-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v2
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX10-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 s2, s4, s5
-; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-SAFE-SDAG-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX10-SAFE-SDAG-NEXT: s_or_b32 s2, s3, s2
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX10-SAFE-SDAG-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX10-SAFE-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x7c00, v1, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v2, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX10-SAFE-SDAG-NEXT: s_lshr_b32 s2, s3, 16
; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX10-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-SAFE-SDAG-NEXT: s_and_b32 s2, s2, 0x8000
+; GFX10-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX10-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s2, v0
; GFX10-SAFE-SDAG-NEXT: s_mov_b32 s2, -1
; GFX10-SAFE-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX10-SAFE-SDAG-NEXT: s_endpgm
@@ -411,52 +413,51 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX11-SAFE-SDAG-NEXT: s_and_b32 s4, s5, 0xffe
; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s2, 0
; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s2, -1, 0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
; GFX11-SAFE-SDAG-NEXT: s_bfe_u32 s2, s3, 0xb0014
-; GFX11-SAFE-SDAG-NEXT: s_sub_i32 s5, 0x3f1, s2
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SAFE-SDAG-NEXT: v_med3_i32 v1, s5, 0, 13
-; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s5, v0
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: v_readfirstlane_b32 s6, v1
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s4, s4, s5
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s5, s4, 0x1000
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s7, s5, s6
-; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s6, s7, s6
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s6, s5
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s4, v0
+; GFX11-SAFE-SDAG-NEXT: s_sub_i32 s4, 0x3f1, s2
; GFX11-SAFE-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s5, s7, s5
-; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX11-SAFE-SDAG-NEXT: v_med3_i32 v1, s4, 0, 13
+; GFX11-SAFE-SDAG-NEXT: s_lshl_b32 s4, s2, 12
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v2, 0x1000, v0
; GFX11-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, s6
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s6, s5, 7
-; GFX11-SAFE-SDAG-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-SAFE-SDAG-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s5, s5, 2
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s6, s6, s7
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_add_i32 s5, s5, s6
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v3, v1, v2
+; GFX11-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v1, v1, v3
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v1, v2
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v2, s4, v0
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-SAFE-SDAG-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-SAFE-SDAG-NEXT: s_movk_i32 s6, 0x7e00
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s5, s5, 0x7c00
-; GFX11-SAFE-SDAG-NEXT: s_cmp_lg_u32 s4, 0
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s4, s6, 0x7c00
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: v_and_b32_e32 v2, 7, v1
+; GFX11-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc_lo, 5, v2
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
; GFX11-SAFE-SDAG-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 s2, s4, s5
-; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-SDAG-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-SAFE-SDAG-NEXT: s_or_b32 s2, s3, s2
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-SAFE-SDAG-NEXT: v_dual_mov_b32 v2, 0x7e00 :: v_dual_add_nc_u32 v1, v1, v2
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x7c00, v1, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x7c00, v2, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX11-SAFE-SDAG-NEXT: s_lshr_b32 s2, s3, 16
; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-SAFE-SDAG-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-SAFE-SDAG-NEXT: s_and_b32 s2, s2, 0x8000
+; GFX11-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX11-SAFE-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SAFE-SDAG-NEXT: v_or_b32_e32 v0, s2, v0
; GFX11-SAFE-SDAG-NEXT: s_mov_b32 s2, -1
; GFX11-SAFE-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-SAFE-SDAG-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 5febd5256e794..7744e8215e05d 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -1181,26 +1181,21 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
; SI-NEXT: s_nop 1
; SI-NEXT: v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
; SI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
-; SI-NEXT: v_readfirstlane_b32 s2, v5
-; SI-NEXT: s_bfe_u32 s0, s2, 0xb0014
-; SI-NEXT: s_add_i32 s3, s0, 0xfffffc01
+; SI-NEXT: v_bfe_u32 v6, v5, 20, 11
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0xfffffc01, v6
; SI-NEXT: s_mov_b32 s1, 0xfffff
; SI-NEXT: s_mov_b32 s0, s6
-; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
-; SI-NEXT: v_not_b32_e32 v6, s0
+; SI-NEXT: v_lshr_b64 v[6:7], s[0:1], v8
+; SI-NEXT: v_not_b32_e32 v6, v6
; SI-NEXT: v_and_b32_e32 v6, v4, v6
-; SI-NEXT: v_not_b32_e32 v7, s1
-; SI-NEXT: v_and_b32_e32 v5, v5, v7
-; SI-NEXT: s_and_b32 s0, s2, 0x80000000
-; SI-NEXT: s_cmp_lt_i32 s3, 0
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_not_b32_e32 v7, v7
+; SI-NEXT: v_and_b32_e32 v7, v5, v7
+; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v5
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v7, s0
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; SI-NEXT: s_cmp_gt_i32 s3, 51
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_mov_b32_e32 v7, s2
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v8
+; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -1401,20 +1396,20 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
; SI-LABEL: fast_frem_f64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s0, s8
-; SI-NEXT: s_mov_b32 s1, s9
-; SI-NEXT: s_mov_b32 s8, s10
-; SI-NEXT: s_mov_b32 s9, s11
-; SI-NEXT: s_mov_b32 s10, s2
-; SI-NEXT: s_mov_b32 s11, s3
-; SI-NEXT: s_mov_b32 s6, s2
-; SI-NEXT: s_mov_b32 s7, s3
-; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; SI-NEXT: s_mov_b32 s8, s0
+; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_mov_b32 s0, s2
+; SI-NEXT: s_mov_b32 s1, s3
+; SI-NEXT: s_mov_b32 s2, s10
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
@@ -1425,29 +1420,24 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
; SI-NEXT: v_mul_f64 v[6:7], v[0:1], v[4:5]
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
; SI-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; SI-NEXT: v_readfirstlane_b32 s6, v5
-; SI-NEXT: s_bfe_u32 s4, s6, 0xb0014
-; SI-NEXT: s_add_i32 s7, s4, 0xfffffc01
-; SI-NEXT: s_mov_b32 s5, 0xfffff
-; SI-NEXT: s_mov_b32 s4, s2
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s7
-; SI-NEXT: v_not_b32_e32 v6, s4
+; SI-NEXT: v_bfe_u32 v6, v5, 20, 11
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0xfffffc01, v6
+; SI-NEXT: s_mov_b32 s1, 0xfffff
+; SI-NEXT: s_mov_b32 s0, s10
+; SI-NEXT: v_lshr_b64 v[6:7], s[0:1], v8
+; SI-NEXT: v_not_b32_e32 v6, v6
; SI-NEXT: v_and_b32_e32 v6, v4, v6
-; SI-NEXT: v_not_b32_e32 v7, s5
-; SI-NEXT: v_and_b32_e32 v5, v5, v7
-; SI-NEXT: s_and_b32 s4, s6, 0x80000000
-; SI-NEXT: s_cmp_lt_i32 s7, 0
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_not_b32_e32 v7, v7
+; SI-NEXT: v_and_b32_e32 v7, v5, v7
+; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v5
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v7, s4
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; SI-NEXT: s_cmp_gt_i32 s7, 51
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_mov_b32_e32 v7, s6
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v8
+; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: fast_frem_f64:
@@ -1622,20 +1612,20 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
; SI-LABEL: unsafe_frem_f64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s0, s8
-; SI-NEXT: s_mov_b32 s1, s9
-; SI-NEXT: s_mov_b32 s8, s10
-; SI-NEXT: s_mov_b32 s9, s11
-; SI-NEXT: s_mov_b32 s10, s2
-; SI-NEXT: s_mov_b32 s11, s3
-; SI-NEXT: s_mov_b32 s6, s2
-; SI-NEXT: s_mov_b32 s7, s3
-; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; SI-NEXT: s_mov_b32 s8, s0
+; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_mov_b32 s0, s2
+; SI-NEXT: s_mov_b32 s1, s3
+; SI-NEXT: s_mov_b32 s2, s10
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
@@ -1646,29 +1636,24 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
; SI-NEXT: v_mul_f64 v[6:7], v[0:1], v[4:5]
; SI-NEXT: v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
; SI-NEXT: v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; SI-NEXT: v_readfirstlane_b32 s6, v5
-; SI-NEXT: s_bfe_u32 s4, s6, 0xb0014
-; SI-NEXT: s_add_i32 s7, s4, 0xfffffc01
-; SI-NEXT: s_mov_b32 s5, 0xfffff
-; SI-NEXT: s_mov_b32 s4, s2
-; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s7
-; SI-NEXT: v_not_b32_e32 v6, s4
+; SI-NEXT: v_bfe_u32 v6, v5, 20, 11
+; SI-NEXT: v_add_i32_e32 v8, vcc, 0xfffffc01, v6
+; SI-NEXT: s_mov_b32 s1, 0xfffff
+; SI-NEXT: s_mov_b32 s0, s10
+; SI-NEXT: v_lshr_b64 v[6:7], s[0:1], v8
+; SI-NEXT: v_not_b32_e32 v6, v6
; SI-NEXT: v_and_b32_e32 v6, v4, v6
-; SI-NEXT: v_not_b32_e32 v7, s5
-; SI-NEXT: v_and_b32_e32 v5, v5, v7
-; SI-NEXT: s_and_b32 s4, s6, 0x80000000
-; SI-NEXT: s_cmp_lt_i32 s7, 0
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_not_b32_e32 v7, v7
+; SI-NEXT: v_and_b32_e32 v7, v5, v7
+; SI-NEXT: v_and_b32_e32 v9, 0x80000000, v5
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v8
; SI-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v7, s4
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
-; SI-NEXT: s_cmp_gt_i32 s7, 51
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_mov_b32_e32 v7, s6
-; SI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v8
+; SI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; SI-NEXT: v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; CI-LABEL: unsafe_frem_f64:
@@ -3896,25 +3881,20 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_nop 1
; SI-NEXT: v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
; SI-NEXT: v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; SI-NEXT: v_readfirstlane_b32 s8, v9
-; SI-NEXT: s_bfe_u32 s0, s8, 0xb0014
-; SI-NEXT: s_add_i32 s9, s0, 0xfffffc01
+; SI-NEXT: v_bfe_u32 v10, v9, 20, 11
+; SI-NEXT: v_add_i32_e32 v12, vcc, 0xfffffc01, v10
; SI-NEXT: s_mov_b32 s3, 0xfffff
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s9
-; SI-NEXT: v_not_b32_e32 v10, s0
+; SI-NEXT: v_lshr_b64 v[10:11], s[2:3], v12
+; SI-NEXT: v_not_b32_e32 v10, v10
; SI-NEXT: v_and_b32_e32 v10, v8, v10
-; SI-NEXT: v_not_b32_e32 v11, s1
-; SI-NEXT: v_and_b32_e32 v9, v9, v11
-; SI-NEXT: s_and_b32 s0, s8, 0x80000000
-; SI-NEXT: s_cmp_lt_i32 s9, 0
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_not_b32_e32 v11, v11
+; SI-NEXT: v_and_b32_e32 v11, v9, v11
+; SI-NEXT: v_and_b32_e32 v13, 0x80000000, v9
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v12
; SI-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v11, s0
-; SI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; SI-NEXT: s_cmp_gt_i32 s9, 51
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_mov_b32_e32 v11, s8
-; SI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; SI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v12
+; SI-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc
; SI-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc
; SI-NEXT: v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
; SI-NEXT: v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
@@ -3932,24 +3912,19 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_nop 1
; SI-NEXT: v_div_fmas_f64 v[6:7], v[14:15], v[8:9], v[12:13]
; SI-NEXT: v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; SI-NEXT: v_readfirstlane_b32 s8, v7
-; SI-NEXT: s_bfe_u32 s0, s8, 0xb0014
-; SI-NEXT: s_add_i32 s9, s0, 0xfffffc01
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s9
-; SI-NEXT: v_not_b32_e32 v8, s0
+; SI-NEXT: v_bfe_u32 v8, v7, 20, 11
+; SI-NEXT: v_add_i32_e32 v10, vcc, 0xfffffc01, v8
+; SI-NEXT: v_lshr_b64 v[8:9], s[2:3], v10
+; SI-NEXT: v_not_b32_e32 v8, v8
; SI-NEXT: v_and_b32_e32 v8, v6, v8
-; SI-NEXT: v_not_b32_e32 v9, s1
-; SI-NEXT: v_and_b32_e32 v7, v7, v9
-; SI-NEXT: s_and_b32 s0, s8, 0x80000000
-; SI-NEXT: s_cmp_lt_i32 s9, 0
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_not_b32_e32 v9, v9
+; SI-NEXT: v_and_b32_e32 v9, v7, v9
+; SI-NEXT: v_and_b32_e32 v11, 0x80000000, v7
+; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v10
; SI-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v9, s0
-; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; SI-NEXT: s_cmp_gt_i32 s9, 51
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_mov_b32_e32 v9, s8
-; SI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; SI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
+; SI-NEXT: v_cmp_lt_i32_e32 vcc, 51, v10
+; SI-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
; SI-NEXT: v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll b/llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
index cb5d6e732c701..4bfc11557af32 100644
--- a/llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ftrunc.f64.ll
@@ -11,7 +11,7 @@ declare <16 x double> @llvm.trunc.v16f64(<16 x double>) nounwind readnone
; FUNC-LABEL: {{^}}v_ftrunc_f64:
; CI: v_trunc_f64
-; SI: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0xb0014
+; SI: v_bfe_u32 {{v[0-9]+}}, {{v[0-9]+}}, 20, 11
; SI: s_endpgm
define amdgpu_kernel void @v_ftrunc_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
%x = load double, ptr addrspace(1) %in, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
index 96533bda8d07e..7f87184d77a7f 100644
--- a/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
@@ -82,8 +82,8 @@ define amdgpu_ps i32 @s_uitofp_i1_to_bf16(i1 inreg %num) {
; GFX7-NEXT: s_bitcmp1_b32 s0, 0
; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; GFX7-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
-; GFX7-NEXT: s_lshr_b32 s0, s0, 16
; GFX7-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uitofp_i1_to_bf16:
@@ -91,15 +91,16 @@ define amdgpu_ps i32 @s_uitofp_i1_to_bf16(i1 inreg %num) {
; GFX9-NEXT: s_bitcmp1_b32 s0, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
+; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_or_b32_e32 v1, 0x400000, v0
+; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX9-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_add_i32 s3, s0, 0x7fff
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
-; GFX9-NEXT: s_cselect_b32 s0, s2, s3
-; GFX9-NEXT: s_lshr_b32 s0, s0, 16
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_uitofp_i1_to_bf16:
@@ -108,16 +109,17 @@ define amdgpu_ps i32 @s_uitofp_i1_to_bf16(i1 inreg %num) {
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s1, s1, s0
-; GFX11-NEXT: s_bitset1_b32 s0, 22
-; GFX11-NEXT: s_addk_i32 s1, 0x7fff
-; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
-; GFX11-NEXT: s_cselect_b32 s0, s0, s1
-; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: s_uitofp_i1_to_bf16:
@@ -126,19 +128,18 @@ define amdgpu_ps i32 @s_uitofp_i1_to_bf16(i1 inreg %num) {
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0
+; GFX12-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX12-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX12-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s1, s1, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s0, s2, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp i1 %num to bfloat
%b16 = bitcast bfloat %op to i16
@@ -339,24 +340,24 @@ define amdgpu_ps <2 x i32> @s_uitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1]
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
+; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v1
+; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v1
+; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v0
+; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX9-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_add_i32 s3, s0, 0x7fff
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
; GFX9-NEXT: v_readfirstlane_b32 s1, v0
-; GFX9-NEXT: s_cselect_b32 s0, s2, s3
-; GFX9-NEXT: s_bfe_u32 s2, s1, 0x10010
-; GFX9-NEXT: s_or_b32 s4, s1, 0x400000
-; GFX9-NEXT: s_add_i32 s1, s2, s1
-; GFX9-NEXT: s_lshr_b32 s0, s0, 16
-; GFX9-NEXT: s_addk_i32 s1, 0x7fff
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; GFX9-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_lshr_b32 s1, s1, 16
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_uitofp_v2i1_to_v2bf16:
@@ -369,26 +370,28 @@ define amdgpu_ps <2 x i32> @s_uitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s0
-; GFX11-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-NEXT: v_cmp_u_f32_e64 s1, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: s_bfe_u32 s3, s0, 0x10010
-; GFX11-NEXT: s_add_i32 s3, s3, s0
-; GFX11-NEXT: s_bitset1_b32 s0, 22
-; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX11-NEXT: s_cselect_b32 s0, s0, s3
-; GFX11-NEXT: s_bfe_u32 s3, s2, 0x10010
-; GFX11-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-NEXT: s_add_i32 s3, s3, s2
-; GFX11-NEXT: s_bitset1_b32 s2, 22
-; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX11-NEXT: s_cselect_b32 s1, s2, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v0
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: s_uitofp_v2i1_to_v2bf16:
@@ -401,31 +404,30 @@ define amdgpu_ps <2 x i32> @s_uitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX12-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v0
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-NEXT: v_add_nc_u32_e32 v2, v2, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX12-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX12-NEXT: v_readfirstlane_b32 s0, v1
-; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX12-NEXT: s_or_b32 s3, s0, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s1, s1, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s0, s3, s1
-; GFX12-NEXT: s_bfe_u32 s1, s2, 0x10010
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-NEXT: s_add_co_i32 s1, s1, s2
-; GFX12-NEXT: s_or_b32 s3, s2, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s2, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s1, s3, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_lshr_b32 s1, s1, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: ; return to shader part epilog
%op = uitofp <2 x i1> %num to <2 x bfloat>
%b16 = bitcast <2 x bfloat> %op to <2 x i16>
@@ -1391,8 +1393,8 @@ define amdgpu_ps i32 @s_sitofp_i1_to_bf16(i1 inreg %num) {
; GFX7-NEXT: s_bitcmp1_b32 s0, 0
; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s[0:1]
+; GFX7-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX7-NEXT: v_readfirstlane_b32 s0, v0
-; GFX7-NEXT: s_ashr_i32 s0, s0, 16
; GFX7-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_sitofp_i1_to_bf16:
@@ -1400,15 +1402,16 @@ define amdgpu_ps i32 @s_sitofp_i1_to_bf16(i1 inreg %num) {
; GFX9-NEXT: s_bitcmp1_b32 s0, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s[0:1]
+; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v0
+; GFX9-NEXT: v_or_b32_e32 v1, 0x400000, v0
+; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX9-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_add_i32 s3, s0, 0x7fff
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
-; GFX9-NEXT: s_cselect_b32 s0, s2, s3
-; GFX9-NEXT: s_ashr_i32 s0, s0, 16
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_sitofp_i1_to_bf16:
@@ -1417,16 +1420,17 @@ define amdgpu_ps i32 @s_sitofp_i1_to_bf16(i1 inreg %num) {
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s1, s1, s0
-; GFX11-NEXT: s_bitset1_b32 s0, 22
-; GFX11-NEXT: s_addk_i32 s1, 0x7fff
-; GFX11-NEXT: s_and_b32 s2, vcc_lo, exec_lo
-; GFX11-NEXT: s_cselect_b32 s0, s0, s1
-; GFX11-NEXT: s_ashr_i32 s0, s0, 16
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: s_sitofp_i1_to_bf16:
@@ -1435,19 +1439,18 @@ define amdgpu_ps i32 @s_sitofp_i1_to_bf16(i1 inreg %num) {
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s0
+; GFX12-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX12-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX12-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
-; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX12-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s1, s1, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s0, s2, s1
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_ashr_i32 s0, s0, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp i1 %num to bfloat
%b16 = bitcast bfloat %op to i16
@@ -1648,24 +1651,24 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1.0, s[0:1]
; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s[0:1]
+; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v1
+; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v1
+; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX9-NEXT: s_or_b32 s2, s0, 0x400000
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_add_i32 s3, s0, 0x7fff
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX9-NEXT: s_or_b32 s3, s0, 0x400000
-; GFX9-NEXT: s_add_i32 s0, s1, s0
-; GFX9-NEXT: s_add_i32 s4, s0, 0x7fff
+; GFX9-NEXT: s_nop 1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
+; GFX9-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v0
+; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
-; GFX9-NEXT: s_and_b64 s[0:1], vcc, exec
-; GFX9-NEXT: s_cselect_b32 s0, s3, s4
-; GFX9-NEXT: s_ashr_i32 s0, s0, 16
-; GFX9-NEXT: s_ashr_i32 s1, s2, 16
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v1
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_sitofp_v2i1_to_v2bf16:
@@ -1678,26 +1681,27 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX11-NEXT: s_cselect_b32 s0, -1, 0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s0
-; GFX11-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-NEXT: v_cmp_u_f32_e64 s0, v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX11-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-NEXT: s_bfe_u32 s3, s1, 0x10010
-; GFX11-NEXT: s_add_i32 s3, s3, s1
-; GFX11-NEXT: s_bitset1_b32 s1, 22
-; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s4, vcc_lo, exec_lo
-; GFX11-NEXT: s_cselect_b32 s1, s1, s3
-; GFX11-NEXT: s_bfe_u32 s3, s2, 0x10010
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s2
-; GFX11-NEXT: s_bitset1_b32 s2, 22
-; GFX11-NEXT: s_addk_i32 s3, 0x7fff
-; GFX11-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX11-NEXT: s_cselect_b32 s0, s2, s3
-; GFX11-NEXT: s_ashr_i32 s1, s1, 16
-; GFX11-NEXT: s_ashr_i32 s0, s0, 16
+; GFX11-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: s_sitofp_v2i1_to_v2bf16:
@@ -1710,31 +1714,29 @@ define amdgpu_ps <2 x i32> @s_sitofp_v2i1_to_v2bf16(<2 x i1> inreg %num) {
; GFX12-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-NEXT: s_wait_alu 0xfffe
; GFX12-NEXT: v_cndmask_b32_e64 v1, 0, -1.0, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-NEXT: v_readfirstlane_b32 s0, v1
-; GFX12-NEXT: s_bfe_u32 s1, s0, 0x10010
-; GFX12-NEXT: s_or_b32 s3, s0, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s1, s1, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s1, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s0, s0
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s1, s3, s1
-; GFX12-NEXT: s_bfe_u32 s0, s2, 0x10010
-; GFX12-NEXT: s_or_b32 s3, s2, 0x400000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s0, s0, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_addk_co_i32 s0, 0x7fff
-; GFX12-NEXT: s_cmp_u_f32 s2, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s0, s3, s0
-; GFX12-NEXT: s_ashr_i32 s1, s1, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_ashr_i32 s0, s0, 16
-; GFX12-NEXT: s_wait_alu 0xfffe
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_bfe_u32 v2, v0, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v4, 0x400000, v0
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX12-NEXT: v_bfe_u32 v3, v1, 16, 1
+; GFX12-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v1
+; GFX12-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
+; GFX12-NEXT: v_add_nc_u32_e32 v2, v2, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX12-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 16, v1
+; GFX12-NEXT: v_readfirstlane_b32 s1, v1
+; GFX12-NEXT: s_wait_alu 0xf1ff
; GFX12-NEXT: ; return to shader part epilog
%op = sitofp <2 x i1> %num to <2 x bfloat>
%b16 = bitcast <2 x bfloat> %op to <2 x i16>
diff --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
index 0c5b8b096d910..63b5b0f76eaaa 100644
--- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
+++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
@@ -7,45 +7,44 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX9-LABEL: udiv32_invariant_denom:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-NEXT: s_mov_b32 s7, 0
-; GFX9-NEXT: s_mov_b64 s[2:3], 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX9-NEXT: s_sub_i32 s4, 0, s6
+; GFX9-NEXT: s_sub_i32 s0, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_mul_lo_u32 v0, s0, v3
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v1
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s8, s5, s4
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: .LBB0_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: s_not_b32 s10, s5
-; GFX9-NEXT: s_mul_i32 s9, s6, s5
-; GFX9-NEXT: s_mul_i32 s10, s6, s10
-; GFX9-NEXT: s_add_i32 s11, s5, 1
-; GFX9-NEXT: s_sub_i32 s9, s7, s9
-; GFX9-NEXT: s_add_i32 s10, s7, s10
-; GFX9-NEXT: s_cmp_ge_u32 s9, s6
-; GFX9-NEXT: s_cselect_b32 s11, s11, s5
-; GFX9-NEXT: s_cselect_b32 s9, s10, s9
-; GFX9-NEXT: s_add_i32 s10, s11, 1
-; GFX9-NEXT: s_cmp_ge_u32 s9, s6
-; GFX9-NEXT: s_cselect_b32 s9, s10, s11
-; GFX9-NEXT: s_add_u32 s10, s0, s2
-; GFX9-NEXT: s_addc_u32 s11, s1, s3
+; GFX9-NEXT: v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT: v_not_b32_e32 v5, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s6, v5
+; GFX9-NEXT: s_add_u32 s8, s2, s4
+; GFX9-NEXT: v_sub_u32_e32 v4, s7, v4
+; GFX9-NEXT: v_add_u32_e32 v6, 1, v1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT: s_addc_u32 s9, s3, s5
+; GFX9-NEXT: v_add_u32_e32 v5, s7, v5
+; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v4
; GFX9-NEXT: s_add_i32 s7, s7, 1
-; GFX9-NEXT: s_add_u32 s4, s4, s8
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v1, v6, s[0:1]
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX9-NEXT: s_add_u32 s4, s4, 4
+; GFX9-NEXT: v_add_u32_e32 v5, 1, v6
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v4
; GFX9-NEXT: s_addc_u32 s5, s5, 0
-; GFX9-NEXT: s_add_u32 s2, s2, 4
-; GFX9-NEXT: s_addc_u32 s3, s3, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc
+; GFX9-NEXT: s_cmpk_eq_i32 s4, 0x1000
+; GFX9-NEXT: global_store_dword v2, v4, s[8:9]
; GFX9-NEXT: s_cbranch_scc0 .LBB0_1
; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm
@@ -53,47 +52,45 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-LABEL: udiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX10-NEXT: s_mov_b32 s7, 0
+; GFX10-NEXT: s_load_dword s1, s[4:5], 0x2c
+; GFX10-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s6, 0
+; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX10-NEXT: s_sub_i32 s2, 0, s6
+; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX10-NEXT: s_sub_i32 s0, 0, s1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v0
+; GFX10-NEXT: v_mul_lo_u32 v0, s0, v2
+; GFX10-NEXT: v_mul_hi_u32 v3, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s2, s2, s4
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
-; GFX10-NEXT: s_mov_b64 s[2:3], 0
-; GFX10-NEXT: s_add_i32 s8, s4, s5
-; GFX10-NEXT: s_mov_b64 s[4:5], 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: .LBB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_not_b32 s10, s5
-; GFX10-NEXT: s_mul_i32 s9, s6, s5
-; GFX10-NEXT: s_mul_i32 s10, s6, s10
-; GFX10-NEXT: s_sub_i32 s9, s7, s9
-; GFX10-NEXT: s_add_i32 s11, s5, 1
-; GFX10-NEXT: s_add_i32 s10, s7, s10
-; GFX10-NEXT: s_cmp_ge_u32 s9, s6
-; GFX10-NEXT: s_cselect_b32 s11, s11, s5
-; GFX10-NEXT: s_cselect_b32 s9, s10, s9
-; GFX10-NEXT: s_add_i32 s10, s11, 1
-; GFX10-NEXT: s_cmp_ge_u32 s9, s6
-; GFX10-NEXT: s_cselect_b32 s9, s10, s11
-; GFX10-NEXT: s_add_u32 s10, s0, s2
-; GFX10-NEXT: s_addc_u32 s11, s1, s3
-; GFX10-NEXT: s_add_i32 s7, s7, 1
-; GFX10-NEXT: s_add_u32 s4, s4, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
+; GFX10-NEXT: v_not_b32_e32 v4, v1
+; GFX10-NEXT: v_mul_lo_u32 v5, s1, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v1
+; GFX10-NEXT: v_add_co_u32 v0, s0, v0, v2
+; GFX10-NEXT: v_mul_lo_u32 v4, s1, v4
+; GFX10-NEXT: s_add_u32 s8, s2, s4
+; GFX10-NEXT: s_addc_u32 s9, s3, s5
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, s6, v5
+; GFX10-NEXT: v_add_nc_u32_e32 v4, s6, v4
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v5
+; GFX10-NEXT: s_add_i32 s6, s6, 1
+; GFX10-NEXT: s_add_u32 s4, s4, 4
; GFX10-NEXT: s_addc_u32 s5, s5, 0
-; GFX10-NEXT: s_add_u32 s2, s2, 4
-; GFX10-NEXT: s_addc_u32 s3, s3, 0
-; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX10-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x1000
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v1, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10-NEXT: v_add_co_ci_u32_e64 v1, vcc_lo, 0, v1, s0
+; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v6
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
+; GFX10-NEXT: global_store_dword v3, v4, s[8:9]
; GFX10-NEXT: s_cbranch_scc0 .LBB0_1
; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm
@@ -101,51 +98,54 @@ define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-LABEL: udiv32_invariant_denom:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_mov_b32 s7, 0
+; GFX11-NEXT: s_load_b32 s1, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s6, 0
+; GFX11-NEXT: s_mov_b64 s[4:5], 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX11-NEXT: s_sub_i32 s2, 0, s6
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX11-NEXT: s_sub_i32 s0, 0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v0, s0, v2
+; GFX11-NEXT: v_mul_hi_u32 v3, v2, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s2, s2, s4
-; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
-; GFX11-NEXT: s_mov_b64 s[2:3], 0
-; GFX11-NEXT: s_add_i32 s8, s4, s5
-; GFX11-NEXT: s_mov_b64 s[4:5], 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, v2, v3
+; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB0_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_not_b32 s10, s5
-; GFX11-NEXT: s_mul_i32 s9, s6, s5
-; GFX11-NEXT: s_mul_i32 s10, s6, s10
-; GFX11-NEXT: s_sub_i32 s9, s7, s9
-; GFX11-NEXT: s_add_i32 s11, s5, 1
-; GFX11-NEXT: s_add_i32 s10, s7, s10
-; GFX11-NEXT: s_cmp_ge_u32 s9, s6
-; GFX11-NEXT: s_cselect_b32 s11, s11, s5
-; GFX11-NEXT: s_cselect_b32 s9, s10, s9
-; GFX11-NEXT: s_add_i32 s10, s11, 1
-; GFX11-NEXT: s_cmp_ge_u32 s9, s6
-; GFX11-NEXT: s_cselect_b32 s9, s10, s11
-; GFX11-NEXT: s_add_u32 s10, s0, s2
-; GFX11-NEXT: s_addc_u32 s11, s1, s3
-; GFX11-NEXT: s_add_i32 s7, s7, 1
-; GFX11-NEXT: s_add_u32 s4, s4, s8
-; GFX11-NEXT: v_mov_b32_e32 v1, s9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_not_b32_e32 v4, v1
+; GFX11-NEXT: v_mul_lo_u32 v5, s1, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 1, v1
+; GFX11-NEXT: v_add_co_u32 v0, s0, v0, v2
+; GFX11-NEXT: v_mul_lo_u32 v4, s1, v4
+; GFX11-NEXT: s_add_u32 s8, s2, s4
+; GFX11-NEXT: s_addc_u32 s9, s3, s5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, s6, v5
+; GFX11-NEXT: v_add_nc_u32_e32 v4, s6, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v5
+; GFX11-NEXT: s_add_i32 s6, s6, 1
+; GFX11-NEXT: s_add_u32 s4, s4, 4
; GFX11-NEXT: s_addc_u32 s5, s5, 0
-; GFX11-NEXT: s_add_u32 s2, s2, 4
-; GFX11-NEXT: s_addc_u32 s3, s3, 0
-; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX11-NEXT: global_store_b32 v0, v1, s[10:11]
+; GFX11-NEXT: s_cmpk_eq_i32 s4, 0x1000
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v1, v6, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX11-NEXT: v_add_co_ci_u32_e64 v1, vcc_lo, 0, v1, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v5, 1, v6
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v6, v5, vcc_lo
+; GFX11-NEXT: global_store_b32 v3, v4, s[8:9]
; GFX11-NEXT: s_cbranch_scc0 .LBB0_1
; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_endpgm
@@ -170,140 +170,139 @@ define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX9-LABEL: urem32_invariant_denom:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: s_mov_b32 s7, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX9-NEXT: s_sub_i32 s4, 0, s6
+; GFX9-NEXT: s_sub_i32 s0, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
+; GFX9-NEXT: v_mul_lo_u32 v0, s0, v3
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s4, 0
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v0
; GFX9-NEXT: v_mov_b32_e32 v0, 0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v1
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s8, s5, s4
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
; GFX9-NEXT: .LBB1_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: s_not_b32 s10, s5
-; GFX9-NEXT: s_mul_i32 s9, s6, s5
-; GFX9-NEXT: s_mul_i32 s10, s6, s10
-; GFX9-NEXT: s_sub_i32 s9, s7, s9
-; GFX9-NEXT: s_add_i32 s10, s7, s10
-; GFX9-NEXT: s_cmp_ge_u32 s9, s6
-; GFX9-NEXT: s_cselect_b32 s9, s10, s9
-; GFX9-NEXT: s_sub_i32 s10, s9, s6
-; GFX9-NEXT: s_cmp_ge_u32 s9, s6
-; GFX9-NEXT: s_cselect_b32 s9, s10, s9
-; GFX9-NEXT: s_add_u32 s10, s0, s2
-; GFX9-NEXT: s_addc_u32 s11, s1, s3
-; GFX9-NEXT: s_add_i32 s7, s7, 1
-; GFX9-NEXT: s_add_u32 s4, s4, s8
-; GFX9-NEXT: s_addc_u32 s5, s5, 0
+; GFX9-NEXT: v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT: v_not_b32_e32 v5, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, s6, v5
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_add_u32 s8, s0, s2
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
+; GFX9-NEXT: s_addc_u32 s9, s1, s3
+; GFX9-NEXT: v_add_u32_e32 v5, s4, v5
+; GFX9-NEXT: s_add_i32 s4, s4, 1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: s_add_u32 s2, s2, 4
+; GFX9-NEXT: v_subrev_u32_e32 v5, s6, v4
; GFX9-NEXT: s_addc_u32 s3, s3, 0
-; GFX9-NEXT: v_mov_b32_e32 v1, s9
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX9-NEXT: global_store_dword v2, v4, s[8:9]
; GFX9-NEXT: s_cbranch_scc0 .LBB1_1
; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: urem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb
-; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX10-NEXT: s_mov_b32 s7, 0
+; GFX10-NEXT: s_mov_b64 s[2:3], 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX10-NEXT: s_sub_i32 s2, 0, s6
+; GFX10-NEXT: s_sub_i32 s0, 0, s6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v0
+; GFX10-NEXT: v_mul_lo_u32 v0, s0, v2
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: v_mul_hi_u32 v3, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s2, s2, s4
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
-; GFX10-NEXT: s_mov_b64 s[2:3], 0
-; GFX10-NEXT: s_add_i32 s8, s4, s5
-; GFX10-NEXT: s_mov_b64 s[4:5], 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: .LBB1_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_not_b32 s9, s5
-; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_mul_i32 s10, s6, s5
-; GFX10-NEXT: s_mul_i32 s9, s6, s9
-; GFX10-NEXT: s_sub_i32 s10, s7, s10
-; GFX10-NEXT: s_add_i32 s9, s7, s9
-; GFX10-NEXT: s_cmp_ge_u32 s10, s6
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
-; GFX10-NEXT: s_sub_i32 s10, s9, s6
-; GFX10-NEXT: s_cmp_ge_u32 s9, s6
-; GFX10-NEXT: s_cselect_b32 s9, s10, s9
-; GFX10-NEXT: s_add_u32 s10, s0, s2
-; GFX10-NEXT: s_addc_u32 s11, s1, s3
-; GFX10-NEXT: s_add_i32 s7, s7, 1
-; GFX10-NEXT: s_add_u32 s4, s4, s8
-; GFX10-NEXT: v_mov_b32_e32 v1, s9
-; GFX10-NEXT: s_addc_u32 s5, s5, 0
+; GFX10-NEXT: v_not_b32_e32 v4, v1
+; GFX10-NEXT: v_mul_lo_u32 v5, s6, v1
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_add_u32 s8, s0, s2
+; GFX10-NEXT: s_addc_u32 s9, s1, s3
+; GFX10-NEXT: v_mul_lo_u32 v4, s6, v4
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, s4, v5
+; GFX10-NEXT: v_add_nc_u32_e32 v4, s4, v4
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s6, v5
+; GFX10-NEXT: s_add_i32 s4, s4, 1
; GFX10-NEXT: s_add_u32 s2, s2, 4
; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX10-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s6, v4
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s6, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX10-NEXT: global_store_dword v3, v4, s[8:9]
; GFX10-NEXT: s_cbranch_scc0 .LBB1_1
; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: urem32_invariant_denom:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: s_mov_b32 s7, 0
+; GFX11-NEXT: s_mov_b64 s[2:3], 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GFX11-NEXT: s_sub_i32 s2, 0, s6
+; GFX11-NEXT: s_sub_i32 s0, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v0, s0, v2
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: v_mul_hi_u32 v3, v2, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s2, s2, s4
-; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
-; GFX11-NEXT: s_mov_b64 s[2:3], 0
-; GFX11-NEXT: s_add_i32 s8, s4, s5
-; GFX11-NEXT: s_mov_b64 s[4:5], 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, v2, v3
+; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB1_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_not_b32 s9, s5
-; GFX11-NEXT: s_mul_i32 s10, s6, s5
-; GFX11-NEXT: s_mul_i32 s9, s6, s9
-; GFX11-NEXT: s_sub_i32 s10, s7, s10
-; GFX11-NEXT: s_add_i32 s9, s7, s9
-; GFX11-NEXT: s_cmp_ge_u32 s10, s6
-; GFX11-NEXT: s_cselect_b32 s9, s9, s10
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s10, s9, s6
-; GFX11-NEXT: s_cmp_ge_u32 s9, s6
-; GFX11-NEXT: s_cselect_b32 s9, s10, s9
-; GFX11-NEXT: s_add_u32 s10, s0, s2
-; GFX11-NEXT: s_addc_u32 s11, s1, s3
-; GFX11-NEXT: s_add_i32 s7, s7, 1
-; GFX11-NEXT: s_add_u32 s4, s4, s8
-; GFX11-NEXT: v_mov_b32_e32 v1, s9
-; GFX11-NEXT: s_addc_u32 s5, s5, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_not_b32_e32 v4, v1
+; GFX11-NEXT: v_mul_lo_u32 v5, s6, v1
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_add_u32 s8, s0, s2
+; GFX11-NEXT: s_addc_u32 s9, s1, s3
+; GFX11-NEXT: v_mul_lo_u32 v4, s6, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, s4, v5
+; GFX11-NEXT: v_add_nc_u32_e32 v4, s4, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s6, v5
+; GFX11-NEXT: s_add_i32 s4, s4, 1
; GFX11-NEXT: s_add_u32 s2, s2, 4
; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000
-; GFX11-NEXT: global_store_b32 v0, v1, s[10:11]
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v5, s6, v4
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s6, v4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX11-NEXT: global_store_b32 v3, v4, s[8:9]
; GFX11-NEXT: s_cbranch_scc0 .LBB1_1
; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_endpgm
@@ -328,39 +327,38 @@ define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX9-LABEL: sdiv32_invariant_denom:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_abs_i32 s2, s6
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX9-NEXT: s_ashr_i32 s4, s6, 31
-; GFX9-NEXT: s_sub_i32 s5, 0, s2
+; GFX9-NEXT: s_sub_i32 s0, 0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s5, s5, s6
-; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s5, s6, s5
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: s_ashr_i32 s4, s6, 31
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: .LBB2_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: s_mul_hi_u32 s6, s3, s5
-; GFX9-NEXT: s_mul_i32 s7, s6, s2
-; GFX9-NEXT: s_sub_i32 s7, s3, s7
-; GFX9-NEXT: s_add_i32 s8, s6, 1
-; GFX9-NEXT: s_sub_i32 s9, s7, s2
-; GFX9-NEXT: s_cmp_ge_u32 s7, s2
-; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_cselect_b32 s7, s9, s7
-; GFX9-NEXT: s_add_i32 s8, s6, 1
-; GFX9-NEXT: s_cmp_ge_u32 s7, s2
-; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_xor_b32 s6, s6, s4
-; GFX9-NEXT: s_sub_i32 s6, s6, s4
+; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX9-NEXT: v_mul_lo_u32 v3, v2, s2
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, s3, v3
+; GFX9-NEXT: v_subrev_u32_e32 v5, s2, v3
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v2, s4, v2
; GFX9-NEXT: s_add_i32 s3, s3, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, s6
-; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x400
@@ -370,41 +368,39 @@ define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %ar
;
; GFX10-LABEL: sdiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb
-; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s3, s[4:5], 0x2c
-; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_abs_i32 s2, s3
; GFX10-NEXT: s_ashr_i32 s3, s3, 31
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX10-NEXT: s_sub_i32 s4, 0, s2
+; GFX10-NEXT: s_sub_i32 s0, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s5, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s4, s4, s5
-; GFX10-NEXT: s_mul_hi_u32 s6, s5, s4
+; GFX10-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: s_mov_b32 s4, 0
-; GFX10-NEXT: s_add_i32 s5, s5, s6
+; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: .LBB2_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_mul_hi_u32 s6, s4, s5
-; GFX10-NEXT: s_mul_i32 s7, s6, s2
-; GFX10-NEXT: s_add_i32 s8, s6, 1
-; GFX10-NEXT: s_sub_i32 s7, s4, s7
-; GFX10-NEXT: s_sub_i32 s9, s7, s2
-; GFX10-NEXT: s_cmp_ge_u32 s7, s2
-; GFX10-NEXT: s_cselect_b32 s6, s8, s6
-; GFX10-NEXT: s_cselect_b32 s7, s9, s7
-; GFX10-NEXT: s_add_i32 s8, s6, 1
-; GFX10-NEXT: s_cmp_ge_u32 s7, s2
-; GFX10-NEXT: s_cselect_b32 s6, s8, s6
+; GFX10-NEXT: v_mul_hi_u32 v2, s4, v0
+; GFX10-NEXT: v_mul_lo_u32 v3, v2, s2
+; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, s4, v3
; GFX10-NEXT: s_add_i32 s4, s4, 1
-; GFX10-NEXT: s_xor_b32 s6, s6, s3
-; GFX10-NEXT: s_sub_i32 s6, s6, s3
-; GFX10-NEXT: v_mov_b32_e32 v1, s6
-; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s2, v3
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v2
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX10-NEXT: v_xor_b32_e32 v2, s3, v2
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, s3, v2
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0
@@ -415,48 +411,48 @@ define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %ar
;
; GFX11-LABEL: sdiv32_invariant_denom:
; GFX11: ; %bb.0: ; %bb
-; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x2c
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_abs_i32 s2, s3
; GFX11-NEXT: s_ashr_i32 s3, s3, 31
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s4, 0, s2
+; GFX11-NEXT: s_sub_i32 s0, 0, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s5, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s4, s4, s5
-; GFX11-NEXT: s_mul_hi_u32 s6, s5, s4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_mov_b32 s4, 0
-; GFX11-NEXT: s_add_i32 s5, s5, s6
+; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB2_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_hi_u32 s6, s4, s5
-; GFX11-NEXT: s_mul_i32 s7, s6, s2
-; GFX11-NEXT: s_add_i32 s8, s6, 1
-; GFX11-NEXT: s_sub_i32 s7, s4, s7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s9, s7, s2
-; GFX11-NEXT: s_cmp_ge_u32 s7, s2
-; GFX11-NEXT: s_cselect_b32 s6, s8, s6
-; GFX11-NEXT: s_cselect_b32 s7, s9, s7
-; GFX11-NEXT: s_add_i32 s8, s6, 1
-; GFX11-NEXT: s_cmp_ge_u32 s7, s2
-; GFX11-NEXT: s_cselect_b32 s6, s8, s6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v2, s4, v0
+; GFX11-NEXT: v_mul_lo_u32 v3, v2, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v3, s4, v3
; GFX11-NEXT: s_add_i32 s4, s4, 1
-; GFX11-NEXT: s_xor_b32 s6, s6, s3
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s6, s6, s3
-; GFX11-NEXT: v_mov_b32_e32 v1, s6
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: v_subrev_nc_u32_e32 v5, s2, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v4, 1, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX11-NEXT: v_xor_b32_e32 v2, s3, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v2, s3, v2
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s4, 0x400
@@ -488,31 +484,29 @@ define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_abs_i32 s2, s0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9-NEXT: s_sub_i32 s4, 0, s2
+; GFX9-NEXT: s_sub_i32 s0, 0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s4, s5, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: .LBB3_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4
-; GFX9-NEXT: s_mul_i32 s5, s5, s2
-; GFX9-NEXT: s_sub_i32 s5, s3, s5
-; GFX9-NEXT: s_sub_i32 s6, s5, s2
-; GFX9-NEXT: s_cmp_ge_u32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_sub_i32 s6, s5, s2
-; GFX9-NEXT: s_cmp_ge_u32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
+; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2
+; GFX9-NEXT: v_sub_u32_e32 v2, s3, v2
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, s2, v2
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
; GFX9-NEXT: s_add_i32 s3, s3, 1
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT: global_store_dword v1, v2, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x400
@@ -523,35 +517,33 @@ define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX10-LABEL: srem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_abs_i32 s2, s0
-; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX10-NEXT: s_sub_i32 s3, 0, s2
+; GFX10-NEXT: s_sub_i32 s0, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s4, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s3, s3, s4
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s3
-; GFX10-NEXT: s_mov_b32 s3, 0
-; GFX10-NEXT: s_add_i32 s4, s4, s5
+; GFX10-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: .LBB3_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_mul_hi_u32 s5, s3, s4
-; GFX10-NEXT: s_mul_i32 s5, s5, s2
-; GFX10-NEXT: s_sub_i32 s5, s3, s5
-; GFX10-NEXT: s_sub_i32 s6, s5, s2
-; GFX10-NEXT: s_cmp_ge_u32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: s_sub_i32 s6, s5, s2
-; GFX10-NEXT: s_cmp_ge_u32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
+; GFX10-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX10-NEXT: v_mul_lo_u32 v2, v2, s2
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v2
; GFX10-NEXT: s_add_i32 s3, s3, 1
-; GFX10-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0
@@ -563,42 +555,41 @@ define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %ar
; GFX11-LABEL: srem32_invariant_denom:
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_abs_i32 s2, s0
-; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX11-NEXT: s_sub_i32 s3, 0, s2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_sub_i32 s0, 0, s2
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s3, s3, s4
-; GFX11-NEXT: s_mul_hi_u32 s5, s4, s3
-; GFX11-NEXT: s_mov_b32 s3, 0
-; GFX11-NEXT: s_add_i32 s4, s4, s5
+; GFX11-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v1
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB3_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_hi_u32 s5, s3, s4
-; GFX11-NEXT: s_mul_i32 s5, s5, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s5, s3, s5
-; GFX11-NEXT: s_sub_i32 s6, s5, s2
-; GFX11-NEXT: s_cmp_ge_u32 s5, s2
-; GFX11-NEXT: s_cselect_b32 s5, s6, s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_sub_i32 s6, s5, s2
-; GFX11-NEXT: s_cmp_ge_u32 s5, s2
-; GFX11-NEXT: s_cselect_b32 s5, s6, s5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v2, s3, v0
+; GFX11-NEXT: v_mul_lo_u32 v2, v2, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_sub_nc_u32_e32 v2, s3, v2
; GFX11-NEXT: s_add_i32 s3, s3, 1
-; GFX11-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s2, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s3, 0x400
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 1f21a1a91fc89..c75dc539cdcee 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -9478,61 +9478,42 @@ define amdgpu_cs void @insert_or_disj_index(ptr addrspace(1) %out, ptr addrspace
; GENERIC-NEXT: s_mov_b32 s0, s2
; GENERIC-NEXT: s_mov_b32 s1, s2
; GENERIC-NEXT: s_waitcnt vmcnt(0)
-; GENERIC-NEXT: v_readfirstlane_b32 s4, v2
-; GENERIC-NEXT: s_or_b32 s4, s4, 1
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 3
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_or_b32_e32 v2, 1, v2
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v8, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 2
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v7, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 1
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v6, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 0
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 7
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 6
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v11, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 5
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 4
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v9, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 11
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: v_cndmask_b32_e32 v13, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 10
-; GENERIC-NEXT: buffer_store_dwordx4 v[9:12], v[0:1], s[0:3], 0 addr64 offset:16
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: s_waitcnt expcnt(0)
-; GENERIC-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 9
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: v_cndmask_b32_e32 v11, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 8
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: v_cndmask_b32_e32 v10, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 15
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 11, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v16, 0, v4, vcc
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 10, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v15, 0, v4, vcc
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 9, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v14, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 14
-; GENERIC-NEXT: buffer_store_dwordx4 v[10:13], v[0:1], s[0:3], 0 addr64 offset:32
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: s_waitcnt expcnt(0)
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 8, v2
; GENERIC-NEXT: v_cndmask_b32_e32 v13, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 13
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: v_cndmask_b32_e32 v12, 0, v4, vcc
-; GENERIC-NEXT: s_cmp_eq_u32 s4, 12
-; GENERIC-NEXT: s_cselect_b64 vcc, -1, 0
-; GENERIC-NEXT: v_cndmask_b32_e32 v11, 0, v4, vcc
-; GENERIC-NEXT: buffer_store_dwordx4 v[11:14], v[0:1], s[0:3], 0 addr64 offset:48
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 15, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v20, 0, v4, vcc
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 14, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v19, 0, v4, vcc
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 13, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v18, 0, v4, vcc
+; GENERIC-NEXT: v_cmp_eq_u32_e32 vcc, 12, v2
+; GENERIC-NEXT: v_cndmask_b32_e32 v17, 0, v4, vcc
+; GENERIC-NEXT: buffer_store_dwordx4 v[17:20], v[0:1], s[0:3], 0 addr64 offset:48
+; GENERIC-NEXT: buffer_store_dwordx4 v[13:16], v[0:1], s[0:3], 0 addr64 offset:32
+; GENERIC-NEXT: buffer_store_dwordx4 v[9:12], v[0:1], s[0:3], 0 addr64 offset:16
; GENERIC-NEXT: buffer_store_dwordx4 v[5:8], v[0:1], s[0:3], 0 addr64
; GENERIC-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
index 44b1bb25bc057..ff1e1b82cca94 100644
--- a/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
@@ -90,87 +90,77 @@ define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX11-NEXT: s_mov_b32 s14, s21
-; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: s_mov_b32 s1, -1
; GFX11-NEXT: s_cbranch_execz .LBB2_4
; GFX11-NEXT: s_branch .LBB2_12
; GFX11-NEXT: .LBB2_3:
-; GFX11-NEXT: s_mov_b32 s2, 0
+; GFX11-NEXT: s_mov_b32 s1, 0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-NEXT: s_cbranch_vccnz .LBB2_12
; GFX11-NEXT: .LBB2_4: ; %bb16
-; GFX11-NEXT: s_load_b32 s0, s[16:17], 0x54
+; GFX11-NEXT: s_load_b32 s2, s[16:17], 0x54
; GFX11-NEXT: s_bitcmp1_b32 s23, 0
-; GFX11-NEXT: s_cselect_b32 s9, -1, 0
-; GFX11-NEXT: s_and_b32 s1, s23, 1
+; GFX11-NEXT: s_mov_b32 s8, -1
+; GFX11-NEXT: s_cselect_b32 s0, -1, 0
+; GFX11-NEXT: s_and_b32 s9, s23, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bitcmp1_b32 s0, 0
-; GFX11-NEXT: s_mov_b32 s0, -1
-; GFX11-NEXT: s_cselect_b32 s8, -1, 0
-; GFX11-NEXT: s_cmp_eq_u32 s1, 0
+; GFX11-NEXT: s_bitcmp1_b32 s2, 0
+; GFX11-NEXT: s_cselect_b32 s2, -1, 0
+; GFX11-NEXT: s_cmp_eq_u32 s9, 0
; GFX11-NEXT: s_cbranch_scc0 .LBB2_8
; GFX11-NEXT: ; %bb.5: ; %bb18.preheader
; GFX11-NEXT: s_load_b128 s[28:31], s[16:17], 0x44
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_mul_hi_u32 s0, s29, s28
-; GFX11-NEXT: s_mul_i32 s1, s29, s28
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 1
-; GFX11-NEXT: s_mov_b32 s1, 0
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_or_b32 s0, s0, 1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshr_b32 s0, s0, s30
-; GFX11-NEXT: s_mul_i32 s0, s0, s22
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_i32 s0, s0, s20
-; GFX11-NEXT: s_or_b32 s0, s19, s0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshl_b64 s[20:21], s[0:1], 1
-; GFX11-NEXT: s_mov_b32 s0, s1
-; GFX11-NEXT: global_load_u16 v1, v0, s[20:21]
+; GFX11-NEXT: s_mul_hi_u32 s8, s29, s28
+; GFX11-NEXT: s_mul_i32 s9, s29, s28
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_alignbit_b32 v0, s8, s9, 1
+; GFX11-NEXT: v_or_b32_e32 v0, 1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, s30, v0
+; GFX11-NEXT: v_mul_lo_u32 v0, v0, s22
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v0, v0, s20
+; GFX11-NEXT: v_or_b32_e32 v0, s19, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s24
+; GFX11-NEXT: global_load_u16 v2, v[2:3], off
+; GFX11-NEXT: v_mov_b32_e32 v3, v1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-NEXT: s_mov_b32 vcc_lo, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB2_6: ; %bb18
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: v_readfirstlane_b32 s13, v0
-; GFX11-NEXT: s_cmp_lg_u32 s1, 0
-; GFX11-NEXT: s_cselect_b32 s1, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
-; GFX11-NEXT: s_and_b32 s1, s8, s1
-; GFX11-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_readfirstlane_b32 s19, v2
-; GFX11-NEXT: s_cselect_b32 s1, s19, s13
-; GFX11-NEXT: s_and_b32 s13, 0xffff, s0
-; GFX11-NEXT: s_and_b32 s1, s1, 1
-; GFX11-NEXT: s_cmp_lg_u32 s13, 0
-; GFX11-NEXT: s_cselect_b32 s13, -1, 0
-; GFX11-NEXT: s_and_b32 s20, s9, exec_lo
-; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s13
-; GFX11-NEXT: v_readfirstlane_b32 s13, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s19, v2
-; GFX11-NEXT: s_cselect_b32 s13, s19, s13
-; GFX11-NEXT: s_bitcmp1_b32 s13, 0
-; GFX11-NEXT: s_cselect_b32 s13, 0x100, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s13, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v3
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v2, v4, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_cndmask_b32 v1, v0, v1 :: v_dual_and_b32 v4, 1, v4
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x100, vcc_lo
+; GFX11-NEXT: s_mov_b32 vcc_lo, 0
+; GFX11-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-NEXT: s_cbranch_vccz .LBB2_6
; GFX11-NEXT: ; %bb.7: ; %Flow
-; GFX11-NEXT: s_mov_b32 s0, 0
+; GFX11-NEXT: s_mov_b32 s8, 0
; GFX11-NEXT: .LBB2_8: ; %Flow12
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s0
+; GFX11-NEXT: s_and_b32 vcc_lo, exec_lo, s8
; GFX11-NEXT: s_cbranch_vccz .LBB2_12
; GFX11-NEXT: ; %bb.9:
-; GFX11-NEXT: s_xor_b32 s0, s8, -1
+; GFX11-NEXT: s_xor_b32 s0, s2, -1
; GFX11-NEXT: .LBB2_10: ; %bb17
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -179,7 +169,7 @@ define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg
; GFX11-NEXT: ; %bb.11: ; %Flow6
; GFX11-NEXT: s_mov_b32 s18, -1
; GFX11-NEXT: .LBB2_12: ; %Flow11
-; GFX11-NEXT: s_and_b32 s20, s2, exec_lo
+; GFX11-NEXT: s_and_b32 s20, s1, exec_lo
; GFX11-NEXT: s_or_not1_b32 s0, s18, exec_lo
; GFX11-NEXT: .LBB2_13: ; %Flow9
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s3
diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
index efd4a0044c660..6fbcb6ba42e13 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
@@ -428,29 +428,27 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s4, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s4
-; GFX9-NEXT: s_mul_hi_u32 s4, s2, s5
-; GFX9-NEXT: s_mul_i32 s5, s4, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_add_i32 s6, s4, 1
-; GFX9-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_add_i32 s5, s4, 1
-; GFX9-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s5, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-NEXT: v_subrev_u32_e32 v4, s3, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
@@ -464,22 +462,20 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX90A-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX90A-NEXT: v_readfirstlane_b32 s5, v0
-; GFX90A-NEXT: s_mul_i32 s4, s4, s5
-; GFX90A-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX90A-NEXT: s_add_i32 s5, s5, s4
-; GFX90A-NEXT: s_mul_hi_u32 s4, s2, s5
-; GFX90A-NEXT: s_mul_i32 s5, s4, s3
-; GFX90A-NEXT: s_sub_i32 s2, s2, s5
-; GFX90A-NEXT: s_add_i32 s6, s4, 1
-; GFX90A-NEXT: s_sub_i32 s5, s2, s3
-; GFX90A-NEXT: s_cmp_ge_u32 s2, s3
-; GFX90A-NEXT: s_cselect_b32 s4, s6, s4
-; GFX90A-NEXT: s_cselect_b32 s2, s5, s2
-; GFX90A-NEXT: s_add_i32 s5, s4, 1
-; GFX90A-NEXT: s_cmp_ge_u32 s2, s3
-; GFX90A-NEXT: s_cselect_b32 s2, s5, s4
-; GFX90A-NEXT: v_mov_b32_e32 v0, s2
+; GFX90A-NEXT: v_mul_lo_u32 v2, s4, v0
+; GFX90A-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX90A-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX90A-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX90A-NEXT: v_mul_lo_u32 v2, v0, s3
+; GFX90A-NEXT: v_sub_u32_e32 v2, s2, v2
+; GFX90A-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX90A-NEXT: v_subrev_u32_e32 v4, s3, v2
+; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX90A-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s3, v2
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_endpgm
@@ -489,28 +485,26 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX10-NEXT: s_sub_i32 s5, 0, s3
+; GFX10-NEXT: s_sub_i32 s4, 0, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s4, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, 0
-; GFX10-NEXT: s_mul_i32 s5, s5, s4
-; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: s_mul_hi_u32 s4, s2, s4
-; GFX10-NEXT: s_mul_i32 s5, s4, s3
-; GFX10-NEXT: s_sub_i32 s2, s2, s5
-; GFX10-NEXT: s_add_i32 s5, s4, 1
-; GFX10-NEXT: s_sub_i32 s6, s2, s3
-; GFX10-NEXT: s_cmp_ge_u32 s2, s3
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_cselect_b32 s2, s6, s2
-; GFX10-NEXT: s_add_i32 s5, s4, 1
-; GFX10-NEXT: s_cmp_ge_u32 s2, s3
-; GFX10-NEXT: s_cselect_b32 s2, s5, s4
-; GFX10-NEXT: v_mov_b32_e32 v1, s2
-; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX10-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX10-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s2, v1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, s3, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v3, 0
+; GFX10-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: global_store_dword v3, v0, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm
;
@@ -518,29 +512,27 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX9-FLATSCR: ; %bb.0:
; GFX9-FLATSCR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; GFX9-FLATSCR-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-FLATSCR-NEXT: s_sub_i32 s4, 0, s3
; GFX9-FLATSCR-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-FLATSCR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-FLATSCR-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-FLATSCR-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-FLATSCR-NEXT: s_mul_i32 s4, s4, s5
-; GFX9-FLATSCR-NEXT: s_mul_hi_u32 s4, s5, s4
-; GFX9-FLATSCR-NEXT: s_add_i32 s5, s5, s4
-; GFX9-FLATSCR-NEXT: s_mul_hi_u32 s4, s2, s5
-; GFX9-FLATSCR-NEXT: s_mul_i32 s5, s4, s3
-; GFX9-FLATSCR-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-FLATSCR-NEXT: s_add_i32 s6, s4, 1
-; GFX9-FLATSCR-NEXT: s_sub_i32 s5, s2, s3
-; GFX9-FLATSCR-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-FLATSCR-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-FLATSCR-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-FLATSCR-NEXT: s_add_i32 s5, s4, 1
-; GFX9-FLATSCR-NEXT: s_cmp_ge_u32 s2, s3
-; GFX9-FLATSCR-NEXT: s_cselect_b32 s2, s5, s4
-; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s2
-; GFX9-FLATSCR-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9-FLATSCR-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX9-FLATSCR-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX9-FLATSCR-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-FLATSCR-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX9-FLATSCR-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX9-FLATSCR-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-FLATSCR-NEXT: v_sub_u32_e32 v1, s2, v1
+; GFX9-FLATSCR-NEXT: v_subrev_u32_e32 v4, s3, v1
+; GFX9-FLATSCR-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-FLATSCR-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-FLATSCR-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-FLATSCR-NEXT: v_add_u32_e32 v3, 1, v0
+; GFX9-FLATSCR-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX9-FLATSCR-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-FLATSCR-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX9-FLATSCR-NEXT: s_endpgm
;
@@ -549,34 +541,32 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX11-NEXT: s_sub_i32 s5, 0, s3
+; GFX11-NEXT: s_sub_i32 s4, 0, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v0
-; GFX11-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-NEXT: s_mul_i32 s5, s5, s4
-; GFX11-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s4, s4, s5
-; GFX11-NEXT: s_mul_hi_u32 s4, s2, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_mul_i32 s5, s4, s3
-; GFX11-NEXT: s_sub_i32 s2, s2, s5
-; GFX11-NEXT: s_add_i32 s5, s4, 1
-; GFX11-NEXT: s_sub_i32 s6, s2, s3
-; GFX11-NEXT: s_cmp_ge_u32 s2, s3
-; GFX11-NEXT: s_cselect_b32 s4, s5, s4
-; GFX11-NEXT: s_cselect_b32 s2, s6, s2
-; GFX11-NEXT: s_add_i32 s5, s4, 1
-; GFX11-NEXT: s_cmp_ge_u32 s2, s3
-; GFX11-NEXT: s_cselect_b32 s2, s5, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX11-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, s2, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_subrev_nc_u32_e32 v3, s3, v1
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 1, v0
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX11-NEXT: global_store_b32 v3, v0, s[0:1]
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_endpgm
;
@@ -585,40 +575,33 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) {
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_cvt_f32_u32 s4, s3
-; GFX12-NEXT: s_sub_co_i32 s5, 0, s3
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
; GFX12-NEXT: v_rcp_iflag_f32_e32 v0, s4
-; GFX12-NEXT: v_readfirstlane_b32 s4, v0
-; GFX12-NEXT: s_mul_f32 s4, s4, 0x4f7ffffe
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: s_cvt_u32_f32 s4, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_mul_i32 s5, s5, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s4, s4, s5
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_mul_hi_u32 s4, s2, s4
+; GFX12-NEXT: s_sub_co_i32 s4, 0, s3
+; GFX12-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_mul_i32 s5, s4, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_sub_co_i32 s2, s2, s5
-; GFX12-NEXT: s_add_co_i32 s5, s4, 1
-; GFX12-NEXT: s_sub_co_i32 s6, s2, s3
-; GFX12-NEXT: s_cmp_ge_u32 s2, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s4, s5, s4
-; GFX12-NEXT: s_cselect_b32 s2, s6, s2
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_add_co_i32 s5, s4, 1
-; GFX12-NEXT: s_cmp_ge_u32 s2, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_cselect_b32 s2, s5, s4
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX12-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX12-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX12-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_sub_nc_u32_e32 v1, s2, v1
+; GFX12-NEXT: v_subrev_nc_u32_e32 v3, s3, v1
+; GFX12-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
+; GFX12-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 1, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX12-NEXT: s_wait_alu 0xfffd
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX12-NEXT: global_store_b32 v3, v0, s[0:1]
; GFX12-NEXT: s_wait_storecnt 0x0
; GFX12-NEXT: s_endpgm
%r = udiv i32 %x, %y
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
index ab88c5fa36a12..ce79201fb8098 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
@@ -496,34 +496,32 @@ define amdgpu_kernel void @smulo_i64_s(i64 %x, i64 %y) {
; SI-NEXT: v_mul_hi_u32 v0, s0, v0
; SI-NEXT: v_mul_hi_i32 v2, s1, v2
; SI-NEXT: s_mul_i32 s6, s1, s3
+; SI-NEXT: s_cmp_lt_i32 s1, 0
; SI-NEXT: s_mul_i32 s8, s0, s2
-; SI-NEXT: v_readfirstlane_b32 s9, v1
-; SI-NEXT: v_readfirstlane_b32 s10, v3
-; SI-NEXT: v_readfirstlane_b32 s11, v0
-; SI-NEXT: v_readfirstlane_b32 s12, v2
+; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v0
+; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4
+; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; SI-NEXT: v_add_i32_e32 v0, vcc, s5, v0
-; SI-NEXT: s_add_u32 s5, s11, s5
-; SI-NEXT: v_add_i32_e32 v2, vcc, s4, v0
-; SI-NEXT: s_addc_u32 s10, 0, s10
-; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v2
-; SI-NEXT: s_add_u32 s4, s5, s4
-; SI-NEXT: v_mov_b32_e32 v1, v0
-; SI-NEXT: s_addc_u32 s4, s10, s9
-; SI-NEXT: s_addc_u32 s5, s12, 0
-; SI-NEXT: s_add_u32 s4, s4, s6
-; SI-NEXT: s_addc_u32 s5, 0, s5
-; SI-NEXT: s_sub_u32 s2, s4, s2
-; SI-NEXT: s_subb_u32 s6, s5, 0
-; SI-NEXT: s_cmp_lt_i32 s1, 0
-; SI-NEXT: s_cselect_b32 s1, s6, s5
-; SI-NEXT: s_cselect_b32 s2, s2, s4
-; SI-NEXT: s_sub_u32 s0, s2, s0
-; SI-NEXT: s_subb_u32 s4, s1, 0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
+; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v0
+; SI-NEXT: v_subrev_i32_e32 v3, vcc, s2, v1
+; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: s_cmp_lt_i32 s3, 0
-; SI-NEXT: s_cselect_b32 s1, s4, s1
-; SI-NEXT: s_cselect_b32 s0, s0, s2
-; SI-NEXT: v_cmp_ne_u64_e32 vcc, s[0:1], v[0:1]
-; SI-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc
+; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v4
+; SI-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; SI-NEXT: v_cndmask_b32_e32 v5, v1, v3, vcc
+; SI-NEXT: v_mov_b32_e32 v1, v0
+; SI-NEXT: v_subrev_i32_e32 v6, vcc, s0, v5
+; SI-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v2, vcc
+; SI-NEXT: s_cselect_b64 vcc, -1, 0
+; SI-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc
+; SI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[0:1]
+; SI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s0, 0, s8
; SI-NEXT: s_mov_b32 s6, -1
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index a9240eff8e691..0f01de74d217e 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1317,32 +1317,25 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: flat_load_ubyte v4, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v10, s2
; GFX8-NEXT: v_mov_b32_e32 v8, s0
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s2, v0
-; GFX8-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX8-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX8-NEXT: s_bfe_u32 s5, s2, 0x10005
-; GFX8-NEXT: s_and_b32 s6, s2, 1
-; GFX8-NEXT: s_bfe_u32 s7, s2, 0x10002
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x10004
-; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: v_mov_b32_e32 v11, s1
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 7, v0
-; GFX8-NEXT: v_bfe_u32 v2, v0, 6, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v1, s5
-; GFX8-NEXT: v_mov_b32_e32 v10, s0
-; GFX8-NEXT: v_mov_b32_e32 v4, s6
-; GFX8-NEXT: v_mov_b32_e32 v5, s4
-; GFX8-NEXT: v_mov_b32_e32 v6, s7
-; GFX8-NEXT: v_mov_b32_e32 v7, s3
-; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
-; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v4
+; GFX8-NEXT: v_bfe_u32 v3, v4, 3, 1
+; GFX8-NEXT: v_bfe_u32 v1, v4, 1, 1
+; GFX8-NEXT: v_bfe_u32 v5, v4, 5, 1
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX8-NEXT: v_bfe_u32 v2, v4, 2, 1
+; GFX8-NEXT: v_bfe_u32 v4, v4, 4, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 7, v6
+; GFX8-NEXT: v_bfe_u32 v6, v6, 6, 1
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v8i1_to_v8i32:
@@ -1382,26 +1375,20 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v8, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_u8 v0, v8, s[2:3]
+; GFX12-NEXT: global_load_u8 v2, v8, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v5, s4 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10005
-; GFX12-NEXT: s_and_b32 s6, s2, 1
-; GFX12-NEXT: s_bfe_u32 s7, s2, 0x10002
-; GFX12-NEXT: s_bfe_u32 s2, s2, 0x10004
-; GFX12-NEXT: v_lshrrev_b32_e32 v3, 7, v0
-; GFX12-NEXT: v_bfe_u32 v2, v0, 6, 1
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v7, s3
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v4, s6
-; GFX12-NEXT: v_mov_b32_e32 v6, s7
+; GFX12-NEXT: v_and_b32_e32 v6, 0xffff, v2
+; GFX12-NEXT: v_bfe_u32 v5, v2, 5, 1
+; GFX12-NEXT: v_bfe_u32 v4, v2, 4, 1
+; GFX12-NEXT: v_bfe_u32 v3, v2, 3, 1
+; GFX12-NEXT: v_bfe_u32 v1, v2, 1, 1
+; GFX12-NEXT: v_lshrrev_b32_e32 v7, 7, v6
+; GFX12-NEXT: v_bfe_u32 v6, v6, 6, 1
+; GFX12-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX12-NEXT: v_bfe_u32 v2, v2, 2, 1
; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: global_store_b128 v8, v[4:7], s[0:1]
+; GFX12-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = zext <8 x i1> %load to <8 x i32>
@@ -1573,60 +1560,43 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: flat_load_ushort v0, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v17, s1
-; GFX8-NEXT: v_mov_b32_e32 v16, s0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s2, v0
-; GFX8-NEXT: s_and_b32 s6, 0xffff, s2
-; GFX8-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX8-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX8-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX8-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX8-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX8-NEXT: s_and_b32 s9, s2, 1
-; GFX8-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX8-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX8-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX8-NEXT: s_lshr_b32 s13, s6, 15
-; GFX8-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX8-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX8-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX8-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX8-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: flat_load_ushort v2, v[0:1]
; GFX8-NEXT: s_add_u32 s2, s0, 48
-; GFX8-NEXT: v_mov_b32_e32 v15, s3
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v19, s3
-; GFX8-NEXT: v_mov_b32_e32 v1, s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v3, s13
-; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v5, s7
-; GFX8-NEXT: v_mov_b32_e32 v6, s10
-; GFX8-NEXT: v_mov_b32_e32 v4, s17
-; GFX8-NEXT: v_mov_b32_e32 v7, s12
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v12, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_mov_b32_e32 v15, s3
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_mov_b32_e32 v11, s5
-; GFX8-NEXT: v_mov_b32_e32 v8, s16
-; GFX8-NEXT: v_mov_b32_e32 v9, s11
-; GFX8-NEXT: v_mov_b32_e32 v10, s15
-; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_mov_b32_e32 v12, s9
-; GFX8-NEXT: v_mov_b32_e32 v13, s4
-; GFX8-NEXT: v_mov_b32_e32 v14, s14
-; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
-; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff, v2
+; GFX8-NEXT: v_bfe_u32 v5, v2, 13, 1
+; GFX8-NEXT: v_bfe_u32 v4, v2, 12, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 15, v18
+; GFX8-NEXT: v_bfe_u32 v6, v18, 14, 1
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NEXT: v_bfe_u32 v9, v2, 9, 1
+; GFX8-NEXT: v_bfe_u32 v10, v2, 10, 1
+; GFX8-NEXT: v_bfe_u32 v11, v18, 11, 1
+; GFX8-NEXT: v_bfe_u32 v8, v18, 8, 1
+; GFX8-NEXT: v_bfe_u32 v3, v2, 3, 1
+; GFX8-NEXT: v_bfe_u32 v1, v2, 1, 1
+; GFX8-NEXT: v_bfe_u32 v7, v2, 7, 1
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX8-NEXT: v_bfe_u32 v5, v18, 5, 1
+; GFX8-NEXT: v_bfe_u32 v2, v18, 2, 1
+; GFX8-NEXT: v_bfe_u32 v6, v18, 6, 1
+; GFX8-NEXT: v_bfe_u32 v4, v18, 4, 1
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v16i1_to_v16i32:
@@ -1687,40 +1657,30 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %o
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v16, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_u16 v0, v16, s[2:3]
+; GFX12-NEXT: global_load_u16 v2, v16, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-NEXT: s_and_b32 s6, 0xffff, s2
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX12-NEXT: s_bfe_u32 s7, s2, 0x10009
-; GFX12-NEXT: s_bfe_u32 s8, s2, 0x1000d
-; GFX12-NEXT: s_and_b32 s9, s2, 1
-; GFX12-NEXT: v_mov_b32_e32 v1, s8
-; GFX12-NEXT: s_bfe_u32 s10, s2, 0x1000a
-; GFX12-NEXT: s_bfe_u32 s2, s2, 0x1000c
-; GFX12-NEXT: s_bfe_u32 s11, s6, 0x10005
-; GFX12-NEXT: s_bfe_u32 s12, s6, 0x1000b
-; GFX12-NEXT: s_lshr_b32 s13, s6, 15
-; GFX12-NEXT: s_bfe_u32 s14, s6, 0x10002
-; GFX12-NEXT: s_bfe_u32 s15, s6, 0x10006
-; GFX12-NEXT: s_bfe_u32 s16, s6, 0x10004
-; GFX12-NEXT: s_bfe_u32 s17, s6, 0x10008
-; GFX12-NEXT: s_bfe_u32 s6, s6, 0x1000e
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s7
-; GFX12-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v2, s6
-; GFX12-NEXT: v_dual_mov_b32 v3, s13 :: v_dual_mov_b32 v4, s17
-; GFX12-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v11, s5
-; GFX12-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s16
-; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v10, s15
-; GFX12-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v13, s4
-; GFX12-NEXT: v_mov_b32_e32 v14, s14
+; GFX12-NEXT: v_and_b32_e32 v17, 0xffff, v2
+; GFX12-NEXT: v_bfe_u32 v13, v2, 13, 1
+; GFX12-NEXT: v_bfe_u32 v12, v2, 12, 1
+; GFX12-NEXT: v_bfe_u32 v9, v2, 9, 1
+; GFX12-NEXT: v_bfe_u32 v10, v2, 10, 1
+; GFX12-NEXT: v_lshrrev_b32_e32 v15, 15, v17
+; GFX12-NEXT: v_bfe_u32 v14, v17, 14, 1
+; GFX12-NEXT: v_bfe_u32 v11, v17, 11, 1
+; GFX12-NEXT: v_bfe_u32 v8, v17, 8, 1
+; GFX12-NEXT: v_bfe_u32 v7, v2, 7, 1
+; GFX12-NEXT: v_bfe_u32 v5, v17, 5, 1
+; GFX12-NEXT: v_bfe_u32 v6, v17, 6, 1
+; GFX12-NEXT: v_bfe_u32 v4, v17, 4, 1
+; GFX12-NEXT: v_bfe_u32 v3, v2, 3, 1
+; GFX12-NEXT: v_bfe_u32 v1, v2, 1, 1
+; GFX12-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX12-NEXT: v_bfe_u32 v2, v17, 2, 1
; GFX12-NEXT: s_clause 0x3
-; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i32>
@@ -4901,25 +4861,20 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_load_u8 v0, v1, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10002
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_lshrrev_b32_e32 v2, 3, v0
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v0, s3
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10001
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GFX12-NEXT: v_bfe_u32 v8, v0, 2, 1
+; GFX12-NEXT: v_bfe_u32 v4, v0, 1, 1
+; GFX12-NEXT: v_and_b32_e32 v9, 1, v0
+; GFX12-NEXT: v_mov_b32_e32 v3, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 3, v2
+; GFX12-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v8
+; GFX12-NEXT: v_dual_mov_b32 v7, v1 :: v_dual_and_b32 v6, 0xffff, v4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-NEXT: s_and_b32 s2, s2, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX12-NEXT: v_and_b32_e32 v4, 0xffff, v9
+; GFX12-NEXT: s_clause 0x1
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-NEXT: global_store_b128 v1, v[4:7], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = zext <4 x i1> %load to <4 x i64>
@@ -5264,58 +5219,49 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v17, s1
-; GFX8-NEXT: v_mov_b32_e32 v16, s0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_lshr_b32 s2, s3, 6
-; GFX8-NEXT: s_lshr_b32 s4, s3, 7
-; GFX8-NEXT: s_lshr_b32 s6, s3, 4
-; GFX8-NEXT: s_lshr_b32 s8, s3, 5
-; GFX8-NEXT: s_lshr_b32 s10, s3, 2
-; GFX8-NEXT: s_lshr_b32 s12, s3, 3
-; GFX8-NEXT: s_lshr_b32 s14, s3, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: flat_load_ubyte v1, v[0:1]
; GFX8-NEXT: s_add_u32 s2, s0, 48
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v19, s3
-; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NEXT: v_mov_b32_e32 v7, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: v_mov_b32_e32 v6, s4
-; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[4:7]
+; GFX8-NEXT: v_mov_b32_e32 v12, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v8, s6
-; GFX8-NEXT: v_mov_b32_e32 v9, s7
-; GFX8-NEXT: v_mov_b32_e32 v10, s8
-; GFX8-NEXT: v_mov_b32_e32 v11, s9
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v15, s3
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 6, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 7, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
-; GFX8-NEXT: v_mov_b32_e32 v12, s10
-; GFX8-NEXT: v_mov_b32_e32 v13, s11
-; GFX8-NEXT: v_mov_b32_e32 v14, s12
-; GFX8-NEXT: v_mov_b32_e32 v15, s13
-; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 4, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 5, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 2, v1
+; GFX8-NEXT: v_bfe_i32 v6, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v1, 0, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 3, v1
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, s14
-; GFX8-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v8, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v18, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v11, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[8:11]
; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v8i1_to_v8i64:
@@ -5377,41 +5323,36 @@ define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v16, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_u8 v0, v16, s[2:3]
+; GFX12-NEXT: global_load_u8 v1, v16, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_mov_b32_e32 v9, s3
-; GFX12-NEXT: s_lshr_b32 s2, s3, 6
-; GFX12-NEXT: s_lshr_b32 s4, s3, 7
-; GFX12-NEXT: s_lshr_b32 s6, s3, 4
-; GFX12-NEXT: s_lshr_b32 s8, s3, 5
-; GFX12-NEXT: s_lshr_b32 s10, s3, 2
-; GFX12-NEXT: s_lshr_b32 s12, s3, 3
-; GFX12-NEXT: s_lshr_b32 s14, s3, 1
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-NEXT: v_bfe_i32 v12, v9, 0, 1
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
-; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
-; GFX12-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
-; GFX12-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
-; GFX12-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
-; GFX12-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 6, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v5, 7, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v7, 4, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v4, 3, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v8, 2, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v9, 5, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 1, v1
+; GFX12-NEXT: v_bfe_i32 v14, v5, 0, 1
+; GFX12-NEXT: v_bfe_i32 v12, v3, 0, 1
+; GFX12-NEXT: v_bfe_i32 v6, v4, 0, 1
+; GFX12-NEXT: v_bfe_i32 v4, v8, 0, 1
+; GFX12-NEXT: v_bfe_i32 v10, v9, 0, 1
+; GFX12-NEXT: v_bfe_i32 v8, v7, 0, 1
+; GFX12-NEXT: v_bfe_i32 v0, v1, 0, 1
+; GFX12-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX12-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX12-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX12-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX12-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX12-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX12-NEXT: s_clause 0x3
-; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:32
-; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:16
-; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1]
+; GFX12-NEXT: global_store_b128 v16, v[12:15], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v16, v[8:11], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v16, v[4:7], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v16, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = sext <8 x i1> %load to <8 x i64>
@@ -5485,82 +5426,73 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NEXT: flat_load_ushort v8, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 0x50
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: s_add_u32 s4, s0, 64
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: s_add_u32 s6, s0, 0x70
+; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: s_add_u32 s8, s0, 0x60
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v15, s9
; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_mov_b32_e32 v14, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 48
+; GFX8-NEXT: v_mov_b32_e32 v11, v1
+; GFX8-NEXT: v_mov_b32_e32 v13, v1
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
-; GFX8-NEXT: v_mov_b32_e32 v5, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, v1
+; GFX8-NEXT: v_mov_b32_e32 v6, v1
; GFX8-NEXT: v_mov_b32_e32 v7, v1
; GFX8-NEXT: v_mov_b32_e32 v9, v1
-; GFX8-NEXT: v_mov_b32_e32 v11, v1
+; GFX8-NEXT: v_mov_b32_e32 v17, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s2, v0
-; GFX8-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX8-NEXT: s_bfe_u32 s4, s2, 0x1000d
-; GFX8-NEXT: s_bfe_u32 s5, s2, 0x10007
-; GFX8-NEXT: s_bfe_u32 s6, s2, 0x10003
-; GFX8-NEXT: s_bfe_u32 s7, s2, 0x10001
-; GFX8-NEXT: s_and_b32 s8, s2, 1
-; GFX8-NEXT: s_bfe_u32 s9, s2, 0x10002
-; GFX8-NEXT: s_bfe_u32 s10, s2, 0x10004
-; GFX8-NEXT: s_bfe_u32 s11, s2, 0x10006
-; GFX8-NEXT: s_bfe_u32 s12, s2, 0x1000c
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x1000a
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 0x50
-; GFX8-NEXT: v_mov_b32_e32 v6, s3
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v13, s3
-; GFX8-NEXT: v_mov_b32_e32 v12, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 64
-; GFX8-NEXT: v_bfe_u32 v2, v4, 11, 1
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
-; GFX8-NEXT: v_mov_b32_e32 v13, s3
-; GFX8-NEXT: v_mov_b32_e32 v12, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 0x70
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 15, v4
-; GFX8-NEXT: v_bfe_u32 v14, v4, 5, 1
-; GFX8-NEXT: v_bfe_u32 v8, v4, 14, 1
-; GFX8-NEXT: v_bfe_u32 v4, v4, 8, 1
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[4:7]
-; GFX8-NEXT: v_mov_b32_e32 v0, s12
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 0x60
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[8:11]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 48
-; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: v_mov_b32_e32 v0, s11
-; GFX8-NEXT: v_mov_b32_e32 v2, s5
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: s_add_u32 s2, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v0, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, v14
-; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v0, s9
+; GFX8-NEXT: v_bfe_u32 v12, v8, 13, 1
+; GFX8-NEXT: v_bfe_u32 v10, v8, 12, 1
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NEXT: v_mov_b32_e32 v15, s9
+; GFX8-NEXT: v_mov_b32_e32 v14, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 32
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: s_add_u32 s10, s0, 16
+; GFX8-NEXT: v_bfe_u32 v12, v8, 7, 1
+; GFX8-NEXT: v_bfe_u32 v10, v8, 6, 1
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NEXT: v_mov_b32_e32 v15, s11
+; GFX8-NEXT: v_mov_b32_e32 v14, s10
+; GFX8-NEXT: v_bfe_u32 v12, v8, 3, 1
+; GFX8-NEXT: v_bfe_u32 v10, v8, 2, 1
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NEXT: v_mov_b32_e32 v15, s3
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff, v8
+; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_bfe_u32 v0, v8, 10, 1
+; GFX8-NEXT: v_bfe_u32 v2, v18, 11, 1
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v15, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_bfe_u32 v5, v8, 9, 1
+; GFX8-NEXT: v_bfe_u32 v3, v18, 8, 1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_mov_b32_e32 v0, s8
-; GFX8-NEXT: v_mov_b32_e32 v2, s7
-; GFX8-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_bfe_u32 v16, v8, 1, 1
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v8
+; GFX8-NEXT: v_bfe_u32 v10, v8, 4, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 15, v18
+; GFX8-NEXT: v_bfe_u32 v6, v18, 14, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: v_bfe_u32 v12, v18, 5, 1
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[6:9]
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[10:13]
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[14:17]
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v16i1_to_v16i64:
@@ -5651,56 +5583,49 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_u16 v0, v1, s[2:3]
+; GFX12-NEXT: global_load_u16 v12, v1, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_and_b32_e32 v4, 0xffff, v0
-; GFX12-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v22, 0xffff, v12
+; GFX12-NEXT: v_and_b32_e32 v28, 1, v12
+; GFX12-NEXT: v_bfe_u32 v0, v12, 10, 1
+; GFX12-NEXT: v_mov_b32_e32 v5, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-NEXT: v_bfe_u32 v2, v22, 11, 1
; GFX12-NEXT: v_mov_b32_e32 v7, v1
+; GFX12-NEXT: v_bfe_u32 v6, v12, 9, 1
+; GFX12-NEXT: v_bfe_u32 v4, v22, 8, 1
+; GFX12-NEXT: v_mov_b32_e32 v9, v1
; GFX12-NEXT: v_mov_b32_e32 v11, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_bfe_u32 v2, v4, 11, 1
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000a
-; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v0, s3
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x1000d
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x1000c
-; GFX12-NEXT: v_mov_b32_e32 v5, v1
-; GFX12-NEXT: v_bfe_u32 v6, v4, 5, 1
+; GFX12-NEXT: v_lshrrev_b32_e32 v10, 15, v22
+; GFX12-NEXT: v_bfe_u32 v8, v22, 14, 1
+; GFX12-NEXT: v_mov_b32_e32 v13, v1
+; GFX12-NEXT: v_mov_b32_e32 v15, v1
+; GFX12-NEXT: v_bfe_u32 v14, v12, 13, 1
+; GFX12-NEXT: v_bfe_u32 v18, v12, 7, 1
+; GFX12-NEXT: v_bfe_u32 v26, v12, 3, 1
+; GFX12-NEXT: v_bfe_u32 v30, v12, 1, 1
+; GFX12-NEXT: v_bfe_u32 v24, v12, 2, 1
+; GFX12-NEXT: v_bfe_u32 v20, v12, 4, 1
+; GFX12-NEXT: v_bfe_u32 v16, v12, 6, 1
+; GFX12-NEXT: v_bfe_u32 v12, v12, 12, 1
+; GFX12-NEXT: v_mov_b32_e32 v17, v1
+; GFX12-NEXT: v_mov_b32_e32 v19, v1
+; GFX12-NEXT: v_mov_b32_e32 v21, v1
+; GFX12-NEXT: v_mov_b32_e32 v23, v1
+; GFX12-NEXT: v_mov_b32_e32 v25, v1
+; GFX12-NEXT: v_mov_b32_e32 v27, v1
+; GFX12-NEXT: v_mov_b32_e32 v29, v1
+; GFX12-NEXT: v_mov_b32_e32 v31, v1
+; GFX12-NEXT: v_bfe_u32 v22, v22, 5, 1
+; GFX12-NEXT: s_clause 0x7
; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
-; GFX12-NEXT: v_mov_b32_e32 v0, s4
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10007
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10006
-; GFX12-NEXT: v_mov_b32_e32 v9, v1
-; GFX12-NEXT: s_bfe_u32 s6, s2, 0x10002
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_mov_b32_e32 v0, s4
-; GFX12-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10004
-; GFX12-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX12-NEXT: s_bfe_u32 s5, s2, 0x10001
-; GFX12-NEXT: v_lshrrev_b32_e32 v10, 15, v4
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_mov_b32_e32 v0, s4
-; GFX12-NEXT: v_mov_b32_e32 v2, v6
-; GFX12-NEXT: s_bfe_u32 s4, s2, 0x10003
-; GFX12-NEXT: s_and_b32 s2, s2, 1
-; GFX12-NEXT: v_bfe_u32 v8, v4, 14, 1
-; GFX12-NEXT: v_bfe_u32 v4, v4, 8, 1
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
-; GFX12-NEXT: v_mov_b32_e32 v0, s6
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-NEXT: v_mov_b32_e32 v6, s3
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-NEXT: v_mov_b32_e32 v2, s5
-; GFX12-NEXT: s_clause 0x2
-; GFX12-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:112
; GFX12-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:64
-; GFX12-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:112
+; GFX12-NEXT: global_store_b128 v1, v[12:15], s[0:1] offset:96
+; GFX12-NEXT: global_store_b128 v1, v[16:19], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v1, v[20:23], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v1, v[24:27], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v1, v[28:31], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i64>
@@ -5790,109 +5715,92 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
-; GFX8-NEXT: v_mov_b32_e32 v19, s1
-; GFX8-NEXT: v_mov_b32_e32 v18, s0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s3, v0
-; GFX8-NEXT: s_lshr_b32 s2, s3, 14
-; GFX8-NEXT: s_lshr_b32 s4, s3, 15
-; GFX8-NEXT: s_lshr_b32 s6, s3, 12
-; GFX8-NEXT: s_lshr_b32 s8, s3, 13
-; GFX8-NEXT: s_lshr_b32 s10, s3, 10
-; GFX8-NEXT: s_lshr_b32 s12, s3, 11
-; GFX8-NEXT: s_lshr_b32 s14, s3, 8
-; GFX8-NEXT: s_lshr_b32 s16, s3, 9
-; GFX8-NEXT: s_lshr_b32 s18, s3, 6
-; GFX8-NEXT: s_lshr_b32 s20, s3, 7
-; GFX8-NEXT: s_lshr_b32 s22, s3, 4
-; GFX8-NEXT: s_lshr_b32 s24, s3, 5
-; GFX8-NEXT: s_lshr_b32 s26, s3, 2
-; GFX8-NEXT: s_lshr_b32 s28, s3, 3
-; GFX8-NEXT: s_lshr_b32 s30, s3, 1
-; GFX8-NEXT: v_mov_b32_e32 v0, s3
-; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x70
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: v_mov_b32_e32 v15, s3
-; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x60
-; GFX8-NEXT: v_mov_b32_e32 v4, s4
-; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[2:5]
-; GFX8-NEXT: v_mov_b32_e32 v15, s3
-; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NEXT: v_mov_b32_e32 v7, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x50
-; GFX8-NEXT: v_mov_b32_e32 v6, s6
-; GFX8-NEXT: v_mov_b32_e32 v7, s7
-; GFX8-NEXT: v_mov_b32_e32 v8, s8
-; GFX8-NEXT: v_mov_b32_e32 v9, s9
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[6:9]
-; GFX8-NEXT: v_mov_b32_e32 v15, s3
-; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v10, s3
+; GFX8-NEXT: v_mov_b32_e32 v9, s2
; GFX8-NEXT: s_add_u32 s2, s0, 64
-; GFX8-NEXT: v_mov_b32_e32 v10, s10
-; GFX8-NEXT: v_mov_b32_e32 v11, s11
-; GFX8-NEXT: v_mov_b32_e32 v12, s12
-; GFX8-NEXT: v_mov_b32_e32 v13, s13
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
-; GFX8-NEXT: v_mov_b32_e32 v15, s3
-; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: v_mov_b32_e32 v12, s3
+; GFX8-NEXT: v_mov_b32_e32 v11, s2
; GFX8-NEXT: s_add_u32 s2, s0, 48
-; GFX8-NEXT: v_mov_b32_e32 v2, s14
-; GFX8-NEXT: v_mov_b32_e32 v3, s15
-; GFX8-NEXT: v_mov_b32_e32 v4, s16
-; GFX8-NEXT: v_mov_b32_e32 v5, s17
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[2:5]
-; GFX8-NEXT: v_mov_b32_e32 v6, s18
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v16, s3
+; GFX8-NEXT: v_mov_b32_e32 v15, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32
-; GFX8-NEXT: v_mov_b32_e32 v7, s19
-; GFX8-NEXT: v_mov_b32_e32 v8, s20
-; GFX8-NEXT: v_mov_b32_e32 v9, s21
+; GFX8-NEXT: v_mov_b32_e32 v14, s1
; GFX8-NEXT: s_addc_u32 s3, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[6:9]
-; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v13, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16
-; GFX8-NEXT: v_mov_b32_e32 v10, s22
-; GFX8-NEXT: v_mov_b32_e32 v11, s23
-; GFX8-NEXT: v_mov_b32_e32 v12, s24
-; GFX8-NEXT: v_mov_b32_e32 v13, s25
-; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: v_mov_b32_e32 v18, s3
; GFX8-NEXT: s_addc_u32 s1, s1, 0
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[10:13]
-; GFX8-NEXT: v_mov_b32_e32 v5, s1
-; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
-; GFX8-NEXT: v_mov_b32_e32 v14, s26
-; GFX8-NEXT: v_mov_b32_e32 v15, s27
-; GFX8-NEXT: v_mov_b32_e32 v16, s28
-; GFX8-NEXT: v_mov_b32_e32 v17, s29
-; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v17, s2
+; GFX8-NEXT: v_mov_b32_e32 v20, s1
+; GFX8-NEXT: v_mov_b32_e32 v19, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 14, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 15, v0
+; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[1:4]
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 10, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 12, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 13, v0
+; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[1:4]
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 8, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 11, v0
+; GFX8-NEXT: v_bfe_i32 v3, v1, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v5, 0, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 9, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[1:4]
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 6, v0
+; GFX8-NEXT: v_bfe_i32 v3, v7, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v6, 0, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 7, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 4, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 5, v0
+; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[1:4]
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 2, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v3, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v7, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v5, v0, 0, 1
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 3, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: v_bfe_i32 v11, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[1:4]
+; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v21, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GFX8-NEXT: v_mov_b32_e32 v2, s30
-; GFX8-NEXT: v_mov_b32_e32 v3, s31
-; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[14:17]
-; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[0:3]
+; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[9:12]
+; GFX8-NEXT: flat_store_dwordx4 v[19:20], v[0:3]
+; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[5:8]
; GFX8-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v16i1_to_v16i64:
@@ -5999,70 +5907,64 @@ define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT: v_mov_b32_e32 v32, 0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: global_load_u16 v0, v32, s[2:3]
+; GFX12-NEXT: global_load_u16 v1, v32, s[2:3]
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_readfirstlane_b32 s3, v0
-; GFX12-NEXT: s_lshr_b32 s4, s3, 15
-; GFX12-NEXT: s_lshr_b32 s2, s3, 14
-; GFX12-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v28, s3 :: v_dual_mov_b32 v3, s5
-; GFX12-NEXT: s_lshr_b32 s6, s3, 12
-; GFX12-NEXT: s_lshr_b32 s8, s3, 13
-; GFX12-NEXT: s_lshr_b32 s10, s3, 10
-; GFX12-NEXT: s_lshr_b32 s12, s3, 11
-; GFX12-NEXT: s_lshr_b32 s14, s3, 8
-; GFX12-NEXT: s_lshr_b32 s16, s3, 9
-; GFX12-NEXT: s_lshr_b32 s18, s3, 6
-; GFX12-NEXT: s_lshr_b32 s20, s3, 7
-; GFX12-NEXT: s_lshr_b32 s22, s3, 4
-; GFX12-NEXT: s_lshr_b32 s24, s3, 5
-; GFX12-NEXT: s_lshr_b32 s26, s3, 2
-; GFX12-NEXT: s_lshr_b32 s28, s3, 3
-; GFX12-NEXT: s_lshr_b32 s30, s3, 1
-; GFX12-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
-; GFX12-NEXT: s_wait_alu 0xfffe
-; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s7
-; GFX12-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s4
-; GFX12-NEXT: v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v4, s6
-; GFX12-NEXT: v_dual_mov_b32 v9, s11 :: v_dual_mov_b32 v6, s8
-; GFX12-NEXT: v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v8, s10
-; GFX12-NEXT: v_dual_mov_b32 v13, s15 :: v_dual_mov_b32 v10, s12
-; GFX12-NEXT: v_mov_b32_e32 v15, s17
-; GFX12-NEXT: v_bfe_i32 v28, v28, 0, 1
-; GFX12-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v17, s19
-; GFX12-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v19, s21
-; GFX12-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
-; GFX12-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v21, s23
-; GFX12-NEXT: v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v23, s25
-; GFX12-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
-; GFX12-NEXT: v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v25, s27
-; GFX12-NEXT: v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v27, s29
-; GFX12-NEXT: v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v31, s31
-; GFX12-NEXT: v_mov_b32_e32 v26, s28
-; GFX12-NEXT: v_mov_b32_e32 v30, s30
-; GFX12-NEXT: s_clause 0x1
-; GFX12-NEXT: global_store_b128 v32, v[0:3], s[0:1] offset:112
-; GFX12-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:96
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 14, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v5, 15, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v7, 12, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v9, 13, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v11, 10, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v13, 11, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v15, 8, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v16, 9, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v12, 6, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v14, 7, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v8, 4, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v2, 1, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v4, 3, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v10, 2, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v17, 5, v1
+; GFX12-NEXT: v_bfe_i32 v30, v5, 0, 1
+; GFX12-NEXT: v_bfe_i32 v28, v3, 0, 1
+; GFX12-NEXT: v_bfe_i32 v26, v9, 0, 1
+; GFX12-NEXT: v_bfe_i32 v24, v7, 0, 1
+; GFX12-NEXT: v_bfe_i32 v22, v13, 0, 1
+; GFX12-NEXT: v_bfe_i32 v20, v11, 0, 1
+; GFX12-NEXT: v_bfe_i32 v18, v16, 0, 1
+; GFX12-NEXT: v_bfe_i32 v16, v15, 0, 1
+; GFX12-NEXT: v_bfe_i32 v14, v14, 0, 1
+; GFX12-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX12-NEXT: v_bfe_i32 v0, v1, 0, 1
+; GFX12-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX12-NEXT: v_bfe_i32 v6, v4, 0, 1
+; GFX12-NEXT: v_bfe_i32 v4, v10, 0, 1
+; GFX12-NEXT: v_bfe_i32 v10, v17, 0, 1
+; GFX12-NEXT: v_bfe_i32 v8, v8, 0, 1
+; GFX12-NEXT: v_ashrrev_i32_e32 v31, 31, v30
; GFX12-NEXT: v_ashrrev_i32_e32 v29, 31, v28
-; GFX12-NEXT: s_clause 0x5
-; GFX12-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:80
-; GFX12-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:64
-; GFX12-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:48
-; GFX12-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:32
-; GFX12-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:16
-; GFX12-NEXT: global_store_b128 v32, v[28:31], s[0:1]
+; GFX12-NEXT: v_ashrrev_i32_e32 v27, 31, v26
+; GFX12-NEXT: v_ashrrev_i32_e32 v25, 31, v24
+; GFX12-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX12-NEXT: v_ashrrev_i32_e32 v21, 31, v20
+; GFX12-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX12-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; GFX12-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX12-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX12-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX12-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX12-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX12-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX12-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX12-NEXT: s_clause 0x7
+; GFX12-NEXT: global_store_b128 v32, v[28:31], s[0:1] offset:112
+; GFX12-NEXT: global_store_b128 v32, v[24:27], s[0:1] offset:96
+; GFX12-NEXT: global_store_b128 v32, v[20:23], s[0:1] offset:80
+; GFX12-NEXT: global_store_b128 v32, v[16:19], s[0:1] offset:64
+; GFX12-NEXT: global_store_b128 v32, v[12:15], s[0:1] offset:48
+; GFX12-NEXT: global_store_b128 v32, v[8:11], s[0:1] offset:32
+; GFX12-NEXT: global_store_b128 v32, v[4:7], s[0:1] offset:16
+; GFX12-NEXT: global_store_b128 v32, v[0:3], s[0:1]
; GFX12-NEXT: s_endpgm
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = sext <16 x i1> %load to <16 x i64>
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index 263dc051737a5..b539f8a9aafb8 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -1900,10 +1900,13 @@ define amdgpu_ps i64 @lshr_mad_i64_sgpr(i64 inreg %arg0) #0 {
; SI-NEXT: v_mov_b32_e32 v0, 0xffff1c18
; SI-NEXT: v_mul_hi_u32 v0, s1, v0
; SI-NEXT: s_mul_i32 s2, s1, 0xffff1c18
-; SI-NEXT: v_readfirstlane_b32 s3, v0
-; SI-NEXT: s_sub_i32 s3, s3, s1
-; SI-NEXT: s_add_u32 s0, s2, s0
-; SI-NEXT: s_addc_u32 s1, s3, s1
+; SI-NEXT: v_mov_b32_e32 v1, s2
+; SI-NEXT: v_mov_b32_e32 v2, s1
+; SI-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; SI-NEXT: v_add_i32_e32 v1, vcc, s0, v1
+; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v2, vcc
+; SI-NEXT: v_readfirstlane_b32 s0, v1
+; SI-NEXT: v_readfirstlane_b32 s1, v0
; SI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_mad_i64_sgpr:
diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
index 83dd44257cbcf..9fc6d33eae578 100644
--- a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
+++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
@@ -182,20 +182,19 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s8, v1
; GCN-NEXT: s_mov_b64 s[4:5], -1
-; GCN-NEXT: s_cmp_lt_i32 s8, 1
+; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; GCN-NEXT: s_mov_b64 s[6:7], -1
-; GCN-NEXT: s_cbranch_scc1 .LBB1_6
+; GCN-NEXT: s_cbranch_vccnz .LBB1_6
; GCN-NEXT: ; %bb.3: ; %LeafBlock1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_cmp_eq_u32 s8, 1
-; GCN-NEXT: s_cbranch_scc0 .LBB1_5
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GCN-NEXT: s_cbranch_vccz .LBB1_5
; GCN-NEXT: ; %bb.4: ; %case1
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
+; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
+; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2
; GCN-NEXT: s_orn2_b64 s[4:5], vcc, exec
; GCN-NEXT: .LBB1_5: ; %Flow3
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
@@ -206,8 +205,8 @@ define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
; GCN-NEXT: s_cbranch_vccz .LBB1_1
; GCN-NEXT: ; %bb.7: ; %LeafBlock
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
-; GCN-NEXT: s_cmp_eq_u32 s8, 0
-; GCN-NEXT: s_cbranch_scc0 .LBB1_1
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GCN-NEXT: s_cbranch_vccz .LBB1_1
; GCN-NEXT: ; %bb.8: ; %case0
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
index 48ac1c60550d7..706db5b1d70a9 100644
--- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
@@ -228,18 +228,19 @@ body: |
; GCN-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 11, 0
; GCN-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 13, 0
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
- ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
- ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
- ; GCN-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[REG_SEQUENCE]].sub0, [[S_LOAD_DWORDX2_IMM1]].sub0, implicit-def $scc
- ; GCN-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADDC_U32 0, [[S_LOAD_DWORDX2_IMM1]].sub1, implicit-def dead $scc, implicit $scc
- ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_ADD_U32_]], %subreg.sub0, killed [[S_ADDC_U32_]], %subreg.sub1
- ; GCN-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[REG_SEQUENCE]].sub0, [[S_LOAD_DWORDX2_IMM2]].sub0, implicit-def $scc
- ; GCN-NEXT: [[S_ADDC_U32_1:%[0-9]+]]:sreg_32_xm0 = S_ADDC_U32 0, [[S_LOAD_DWORDX2_IMM2]].sub1, implicit-def dead $scc, implicit $scc
- ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_ADD_U32_1]], %subreg.sub0, killed [[S_ADDC_U32_1]], %subreg.sub1
- ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1048576, implicit $exec
- ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_MOV_B32_e32_]], %subreg.sub0, killed [[V_MOV_B32_e32_1]], %subreg.sub1
+ ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_LOAD_DWORDX2_IMM1]].sub0, [[REG_SEQUENCE]].sub0, implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM1]].sub1
+ ; GCN-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY3]], implicit-def $vcc, implicit $vcc, implicit $exec
+ ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e32_]], %subreg.sub0, killed [[V_ADDC_U32_e32_]], %subreg.sub1
+ ; GCN-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_LOAD_DWORDX2_IMM2]].sub0, [[REG_SEQUENCE]].sub0, implicit-def $vcc, implicit $exec
+ ; GCN-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM2]].sub1
+ ; GCN-NEXT: [[V_ADDC_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY4]], implicit-def $vcc, implicit $vcc, implicit $exec
+ ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e32_1]], %subreg.sub0, killed [[V_ADDC_U32_e32_1]], %subreg.sub1
+ ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
+ ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
+ ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1
; GCN-NEXT: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U64_e64 killed [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], implicit $exec
; GCN-NEXT: [[V_CMP_LT_U64_e64_1:%[0-9]+]]:sreg_64 = V_CMP_LT_U64_e64 killed [[REG_SEQUENCE2]], [[REG_SEQUENCE3]], implicit $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 killed [[V_CMP_LT_U64_e64_]], killed [[V_CMP_LT_U64_e64_1]], implicit-def dead $scc
@@ -249,14 +250,13 @@ body: |
; GCN-NEXT: bb.1.bb1:
; GCN-NEXT: successors: %bb.2(0x80000000)
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[REG_SEQUENCE]], 2, implicit-def dead $scc
- ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440
- ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
- ; GCN-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_2]], %subreg.sub0, killed [[S_MOV_B32_1]], %subreg.sub1
+ ; GCN-NEXT: [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 [[REG_SEQUENCE]], 2, implicit $exec
+ ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440
+ ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
+ ; GCN-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_3]], %subreg.sub0, killed [[S_MOV_B32_2]], %subreg.sub1
; GCN-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE4]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6
- ; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[S_LSHL_B64_]]
- ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_2]], killed [[COPY3]], killed [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec
+ ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_1]], [[V_LSHL_B64_e64_]], killed [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2.bb2:
; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index 3fbfd756b97e6..7ff2fb8410e5e 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -157,39 +157,19 @@ define amdgpu_kernel void @scalar_to_vector_v4i16() {
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: scalar_to_vector_v4i16:
-; VI: ; %bb.0: ; %bb
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s0, v0
-; VI-NEXT: s_lshl_b32 s1, s0, 8
-; VI-NEXT: s_or_b32 s0, s0, s1
-; VI-NEXT: s_lshl_b32 s1, s0, 16
-; VI-NEXT: s_and_b32 s0, s0, 0xffff
-; VI-NEXT: s_or_b32 s0, s0, s1
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: scalar_to_vector_v4i16:
-; GFX9: ; %bb.0: ; %bb
-; GFX9-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-NEXT: s_mov_b32 s2, -1
-; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_lshl_b32 s1, s0, 8
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: s_or_b32 s0, s1, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX9-NEXT: s_endpgm
+; GFX89-LABEL: scalar_to_vector_v4i16:
+; GFX89: ; %bb.0: ; %bb
+; GFX89-NEXT: s_mov_b32 s3, 0xf000
+; GFX89-NEXT: s_mov_b32 s2, -1
+; GFX89-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: v_lshlrev_b32_e32 v1, 8, v0
+; GFX89-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX89-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX89-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX89-NEXT: v_mov_b32_e32 v1, v0
+; GFX89-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX89-NEXT: s_endpgm
bb:
%tmp = load <2 x i8>, ptr addrspace(1) poison, align 1
%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
@@ -215,49 +195,21 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
-; VI-LABEL: scalar_to_vector_v4f16:
-; VI: ; %bb.0: ; %bb
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s0, v0
-; VI-NEXT: s_lshl_b32 s1, s0, 8
-; VI-NEXT: s_or_b32 s0, s1, s0
-; VI-NEXT: s_and_b32 s1, s0, 0xff00
-; VI-NEXT: s_bfe_u32 s4, s0, 0x80008
-; VI-NEXT: s_or_b32 s1, s4, s1
-; VI-NEXT: s_and_b32 s0, s0, 0xffff
-; VI-NEXT: s_lshl_b32 s4, s1, 16
-; VI-NEXT: s_and_b32 s1, s1, 0xffff
-; VI-NEXT: s_or_b32 s1, s1, s4
-; VI-NEXT: s_or_b32 s0, s0, s4
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; VI-NEXT: s_endpgm
-;
-; GFX9-LABEL: scalar_to_vector_v4f16:
-; GFX9: ; %bb.0: ; %bb
-; GFX9-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-NEXT: s_mov_b32 s2, -1
-; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_lshl_b32 s1, s0, 8
-; GFX9-NEXT: s_or_b32 s0, s1, s0
-; GFX9-NEXT: s_and_b32 s1, s0, 0xff00
-; GFX9-NEXT: s_bfe_u32 s4, s0, 0x80008
-; GFX9-NEXT: s_or_b32 s1, s4, s1
-; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX9-NEXT: s_and_b32 s4, s1, 0xffff
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_or_b32 s4, s4, s1
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: v_mov_b32_e32 v0, s0
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX9-NEXT: s_endpgm
+; GFX89-LABEL: scalar_to_vector_v4f16:
+; GFX89: ; %bb.0: ; %bb
+; GFX89-NEXT: s_mov_b32 s3, 0xf000
+; GFX89-NEXT: s_mov_b32 s2, -1
+; GFX89-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: v_lshlrev_b32_e32 v1, 8, v0
+; GFX89-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX89-NEXT: v_and_b32_e32 v1, 0xff00, v0
+; GFX89-NEXT: v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX89-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX89-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX89-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX89-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX89-NEXT: s_endpgm
bb:
%load = load half, ptr addrspace(1) poison, align 1
%tmp = bitcast half %load to <2 x i8>
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index d06d9f97db71c..67d0320068004 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -116,35 +116,33 @@ define amdgpu_kernel void @sdiv_i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: s_abs_i32 s5, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_sub_i32 s7, 0, s5
-; GFX9-NEXT: s_xor_b32 s4, s6, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: s_abs_i32 s6, s6
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s8
-; GFX9-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX9-NEXT: s_add_i32 s8, s8, s7
-; GFX9-NEXT: s_mul_hi_u32 s7, s6, s8
-; GFX9-NEXT: s_mul_i32 s8, s7, s5
-; GFX9-NEXT: s_sub_i32 s6, s6, s8
-; GFX9-NEXT: s_add_i32 s9, s7, 1
-; GFX9-NEXT: s_sub_i32 s8, s6, s5
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s7, s9, s7
-; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_add_i32 s8, s7, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s8, s7
-; GFX9-NEXT: s_xor_b32 s5, s5, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_sub_u32_e32 v2, 0, v1
+; GFX9-NEXT: v_max_i32_e32 v2, v1, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v4, 0, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v0
+; GFX9-NEXT: v_max_i32_e32 v5, v0, v5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v1, 1, v3
+; GFX9-NEXT: v_sub_u32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, v4, v2
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm
;
@@ -533,77 +531,73 @@ define amdgpu_kernel void @sdiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
;
; GFX9-LABEL: sdiv_v2i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX9-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-NEXT: s_mov_b32 s2, -1
-; GFX9-NEXT: s_mov_b32 s6, s2
-; GFX9-NEXT: s_mov_b32 s7, s3
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: s_mov_b32 s10, s6
+; GFX9-NEXT: s_mov_b32 s11, s7
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, s10
-; GFX9-NEXT: s_mov_b32 s5, s11
-; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; GFX9-NEXT: s_mov_b32 s8, s2
+; GFX9-NEXT: s_mov_b32 s9, s3
+; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GFX9-NEXT: s_mov_b32 s4, s0
+; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v2
-; GFX9-NEXT: s_abs_i32 s1, s0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s1
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_xor_b32 s0, s5, s0
-; GFX9-NEXT: s_ashr_i32 s6, s0, 31
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX9-NEXT: s_sub_i32 s0, 0, s1
-; GFX9-NEXT: s_abs_i32 s5, s5
-; GFX9-NEXT: v_readfirstlane_b32 s4, v3
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s7, v0
-; GFX9-NEXT: s_mul_i32 s0, s0, s7
-; GFX9-NEXT: s_mul_hi_u32 s0, s7, s0
-; GFX9-NEXT: s_add_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s0, s5, s7
-; GFX9-NEXT: s_mul_i32 s7, s0, s1
-; GFX9-NEXT: s_sub_i32 s5, s5, s7
-; GFX9-NEXT: s_add_i32 s10, s0, 1
-; GFX9-NEXT: s_sub_i32 s7, s5, s1
-; GFX9-NEXT: s_cmp_ge_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s0, s10, s0
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_add_i32 s7, s0, 1
-; GFX9-NEXT: s_cmp_ge_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s5, s7, s0
-; GFX9-NEXT: s_abs_i32 s7, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s7
-; GFX9-NEXT: s_xor_b32 s5, s5, s6
-; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_sub_i32 s9, 0, s7
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s5, s5, s6
-; GFX9-NEXT: s_mov_b32 s0, s8
-; GFX9-NEXT: v_readfirstlane_b32 s8, v1
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_xor_b32 s4, s8, s4
-; GFX9-NEXT: s_abs_i32 s8, s8
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mul_i32 s9, s9, s6
-; GFX9-NEXT: s_mul_hi_u32 s9, s6, s9
-; GFX9-NEXT: s_add_i32 s6, s6, s9
-; GFX9-NEXT: s_mul_hi_u32 s6, s8, s6
-; GFX9-NEXT: s_mul_i32 s9, s6, s7
-; GFX9-NEXT: s_sub_i32 s8, s8, s9
-; GFX9-NEXT: s_add_i32 s10, s6, 1
-; GFX9-NEXT: s_sub_i32 s9, s8, s7
-; GFX9-NEXT: s_cmp_ge_u32 s8, s7
-; GFX9-NEXT: s_cselect_b32 s6, s10, s6
-; GFX9-NEXT: s_cselect_b32 s8, s9, s8
-; GFX9-NEXT: s_add_i32 s9, s6, 1
-; GFX9-NEXT: s_cmp_ge_u32 s8, s7
-; GFX9-NEXT: s_cselect_b32 s6, s9, s6
-; GFX9-NEXT: s_xor_b32 s6, s6, s4
-; GFX9-NEXT: s_sub_i32 s4, s6, s4
-; GFX9-NEXT: v_mov_b32_e32 v0, s5
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX9-NEXT: v_sub_u32_e32 v4, 0, v2
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v3
+; GFX9-NEXT: v_max_i32_e32 v4, v2, v4
+; GFX9-NEXT: v_max_i32_e32 v5, v3, v5
+; GFX9-NEXT: v_cvt_f32_u32_e32 v6, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v5
+; GFX9-NEXT: v_sub_u32_e32 v9, 0, v4
+; GFX9-NEXT: v_sub_u32_e32 v10, 0, v5
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GFX9-NEXT: v_sub_u32_e32 v8, 0, v0
+; GFX9-NEXT: v_xor_b32_e32 v2, v0, v2
+; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
+; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_sub_u32_e32 v11, 0, v1
+; GFX9-NEXT: v_max_i32_e32 v0, v0, v8
+; GFX9-NEXT: v_mul_lo_u32 v9, v9, v6
+; GFX9-NEXT: v_mul_lo_u32 v10, v10, v7
+; GFX9-NEXT: v_xor_b32_e32 v3, v1, v3
+; GFX9-NEXT: v_max_i32_e32 v1, v1, v11
+; GFX9-NEXT: v_mul_hi_u32 v9, v6, v9
+; GFX9-NEXT: v_mul_hi_u32 v10, v7, v10
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v2
+; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v3
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v9
+; GFX9-NEXT: v_add_u32_e32 v7, v7, v10
+; GFX9-NEXT: v_mul_hi_u32 v6, v0, v6
+; GFX9-NEXT: v_mul_hi_u32 v7, v1, v7
+; GFX9-NEXT: v_mul_lo_u32 v8, v6, v4
+; GFX9-NEXT: v_mul_lo_u32 v9, v7, v5
+; GFX9-NEXT: v_add_u32_e32 v10, 1, v6
+; GFX9-NEXT: v_add_u32_e32 v11, 1, v7
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v8
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v9
+; GFX9-NEXT: v_sub_u32_e32 v8, v0, v4
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; GFX9-NEXT: v_sub_u32_e32 v9, v1, v5
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[0:1]
+; GFX9-NEXT: v_add_u32_e32 v8, 1, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[0:1]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; GFX9-NEXT: v_add_u32_e32 v9, 1, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
+; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
; EG-LABEL: sdiv_v2i32:
@@ -1045,137 +1039,129 @@ define amdgpu_kernel void @sdiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
;
; GFX9-LABEL: sdiv_v4i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX9-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-NEXT: s_mov_b32 s2, -1
-; GFX9-NEXT: s_mov_b32 s6, s2
-; GFX9-NEXT: s_mov_b32 s7, s3
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s11, 0xf000
+; GFX9-NEXT: s_mov_b32 s10, -1
+; GFX9-NEXT: s_mov_b32 s6, s10
+; GFX9-NEXT: s_mov_b32 s7, s11
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, s10
-; GFX9-NEXT: s_mov_b32 s5, s11
-; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 offset:16
-; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0
+; GFX9-NEXT: s_mov_b32 s4, s2
+; GFX9-NEXT: s_mov_b32 s5, s3
+; GFX9-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; GFX9-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX9-NEXT: s_mov_b32 s8, s0
+; GFX9-NEXT: s_mov_b32 s9, s1
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: s_abs_i32 s1, s0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s1
+; GFX9-NEXT: v_sub_u32_e32 v12, 0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s5, v4
-; GFX9-NEXT: s_xor_b32 s0, s5, s0
-; GFX9-NEXT: s_ashr_i32 s6, s0, 31
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_sub_i32 s0, 0, s1
-; GFX9-NEXT: s_abs_i32 s5, s5
-; GFX9-NEXT: v_readfirstlane_b32 s4, v1
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s7, v0
-; GFX9-NEXT: s_mul_i32 s0, s0, s7
-; GFX9-NEXT: s_mul_hi_u32 s0, s7, s0
-; GFX9-NEXT: s_add_i32 s7, s7, s0
-; GFX9-NEXT: s_mul_hi_u32 s0, s5, s7
-; GFX9-NEXT: s_mul_i32 s7, s0, s1
-; GFX9-NEXT: s_sub_i32 s5, s5, s7
-; GFX9-NEXT: s_add_i32 s10, s0, 1
-; GFX9-NEXT: s_sub_i32 s7, s5, s1
-; GFX9-NEXT: s_cmp_ge_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s0, s10, s0
-; GFX9-NEXT: s_cselect_b32 s5, s7, s5
-; GFX9-NEXT: s_add_i32 s7, s0, 1
-; GFX9-NEXT: s_cmp_ge_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s1, s7, s0
-; GFX9-NEXT: s_abs_i32 s5, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GFX9-NEXT: s_xor_b32 s1, s1, s6
-; GFX9-NEXT: s_sub_i32 s10, 0, s5
-; GFX9-NEXT: s_sub_i32 s6, s1, s6
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: s_mov_b32 s0, s8
-; GFX9-NEXT: v_readfirstlane_b32 s8, v5
-; GFX9-NEXT: s_xor_b32 s4, s8, s4
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_abs_i32 s8, s8
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s7, v2
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
-; GFX9-NEXT: s_mul_i32 s10, s10, s1
-; GFX9-NEXT: s_mul_hi_u32 s10, s1, s10
-; GFX9-NEXT: s_add_i32 s1, s1, s10
-; GFX9-NEXT: s_mul_hi_u32 s1, s8, s1
-; GFX9-NEXT: s_mul_i32 s10, s1, s5
-; GFX9-NEXT: s_sub_i32 s8, s8, s10
-; GFX9-NEXT: s_add_i32 s11, s1, 1
-; GFX9-NEXT: s_sub_i32 s10, s8, s5
-; GFX9-NEXT: s_cmp_ge_u32 s8, s5
-; GFX9-NEXT: s_cselect_b32 s1, s11, s1
-; GFX9-NEXT: s_cselect_b32 s8, s10, s8
-; GFX9-NEXT: s_add_i32 s10, s1, 1
-; GFX9-NEXT: s_cmp_ge_u32 s8, s5
-; GFX9-NEXT: s_cselect_b32 s5, s10, s1
-; GFX9-NEXT: s_abs_i32 s8, s7
-; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GFX9-NEXT: s_xor_b32 s5, s5, s4
-; GFX9-NEXT: s_sub_i32 s11, 0, s8
-; GFX9-NEXT: s_sub_i32 s4, s5, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s10, v6
-; GFX9-NEXT: s_xor_b32 s7, s10, s7
-; GFX9-NEXT: s_abs_i32 s10, s10
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s7, s7, 31
-; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: v_readfirstlane_b32 s9, v3
-; GFX9-NEXT: v_readfirstlane_b32 s5, v0
-; GFX9-NEXT: s_mul_i32 s11, s11, s5
-; GFX9-NEXT: s_mul_hi_u32 s11, s5, s11
-; GFX9-NEXT: s_add_i32 s5, s5, s11
-; GFX9-NEXT: s_mul_hi_u32 s5, s10, s5
-; GFX9-NEXT: s_mul_i32 s11, s5, s8
-; GFX9-NEXT: s_sub_i32 s10, s10, s11
-; GFX9-NEXT: s_add_i32 s12, s5, 1
-; GFX9-NEXT: s_sub_i32 s11, s10, s8
-; GFX9-NEXT: s_cmp_ge_u32 s10, s8
-; GFX9-NEXT: s_cselect_b32 s5, s12, s5
-; GFX9-NEXT: s_cselect_b32 s10, s11, s10
-; GFX9-NEXT: s_add_i32 s11, s5, 1
-; GFX9-NEXT: s_cmp_ge_u32 s10, s8
-; GFX9-NEXT: s_cselect_b32 s5, s11, s5
-; GFX9-NEXT: s_abs_i32 s8, s9
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s8
-; GFX9-NEXT: v_readfirstlane_b32 s10, v7
-; GFX9-NEXT: s_xor_b32 s5, s5, s7
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX9-NEXT: s_xor_b32 s4, s10, s9
-; GFX9-NEXT: s_sub_i32 s9, 0, s8
-; GFX9-NEXT: s_sub_i32 s5, s5, s7
-; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, s6
-; GFX9-NEXT: s_abs_i32 s6, s10
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s7, v2
-; GFX9-NEXT: s_mul_i32 s9, s9, s7
-; GFX9-NEXT: s_mul_hi_u32 s9, s7, s9
-; GFX9-NEXT: s_add_i32 s7, s7, s9
-; GFX9-NEXT: s_mul_hi_u32 s7, s6, s7
-; GFX9-NEXT: s_mul_i32 s9, s7, s8
-; GFX9-NEXT: s_sub_i32 s6, s6, s9
-; GFX9-NEXT: s_add_i32 s10, s7, 1
-; GFX9-NEXT: s_sub_i32 s9, s6, s8
-; GFX9-NEXT: s_cmp_ge_u32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s7, s10, s7
-; GFX9-NEXT: s_cselect_b32 s6, s9, s6
-; GFX9-NEXT: s_add_i32 s9, s7, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s6, s9, s7
-; GFX9-NEXT: s_xor_b32 s6, s6, s4
-; GFX9-NEXT: s_sub_i32 s4, s6, s4
-; GFX9-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
-; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX9-NEXT: v_sub_u32_e32 v10, 0, v4
+; GFX9-NEXT: v_xor_b32_e32 v8, v0, v4
+; GFX9-NEXT: v_max_i32_e32 v4, v4, v10
+; GFX9-NEXT: v_xor_b32_e32 v11, v1, v5
+; GFX9-NEXT: v_sub_u32_e32 v13, 0, v5
+; GFX9-NEXT: v_max_i32_e32 v1, v1, v12
+; GFX9-NEXT: v_cvt_f32_u32_e32 v12, v4
+; GFX9-NEXT: v_xor_b32_e32 v14, v2, v6
+; GFX9-NEXT: v_sub_u32_e32 v16, 0, v6
+; GFX9-NEXT: v_max_i32_e32 v5, v5, v13
+; GFX9-NEXT: v_sub_u32_e32 v19, 0, v7
+; GFX9-NEXT: v_ashrrev_i32_e32 v10, 31, v14
+; GFX9-NEXT: v_max_i32_e32 v6, v6, v16
+; GFX9-NEXT: v_cvt_f32_u32_e32 v14, v5
+; GFX9-NEXT: v_xor_b32_e32 v17, v3, v7
+; GFX9-NEXT: v_sub_u32_e32 v18, 0, v3
+; GFX9-NEXT: v_max_i32_e32 v7, v7, v19
+; GFX9-NEXT: v_cvt_f32_u32_e32 v16, v6
+; GFX9-NEXT: v_max_i32_e32 v3, v3, v18
+; GFX9-NEXT: v_cvt_f32_u32_e32 v18, v7
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v14, v14
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v16, v16
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v18, v18
+; GFX9-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f7ffffe, v14
+; GFX9-NEXT: v_mul_f32_e32 v16, 0x4f7ffffe, v16
+; GFX9-NEXT: v_cvt_u32_f32_e32 v14, v14
+; GFX9-NEXT: v_sub_u32_e32 v13, 0, v4
+; GFX9-NEXT: v_mul_f32_e32 v18, 0x4f7ffffe, v18
+; GFX9-NEXT: v_cvt_u32_f32_e32 v16, v16
+; GFX9-NEXT: v_sub_u32_e32 v15, 0, v2
+; GFX9-NEXT: v_cvt_u32_f32_e32 v18, v18
+; GFX9-NEXT: v_mul_lo_u32 v13, v13, v12
+; GFX9-NEXT: v_sub_u32_e32 v9, 0, v0
+; GFX9-NEXT: v_max_i32_e32 v2, v2, v15
+; GFX9-NEXT: v_sub_u32_e32 v15, 0, v5
+; GFX9-NEXT: v_max_i32_e32 v0, v0, v9
+; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v11
+; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v17
+; GFX9-NEXT: v_sub_u32_e32 v17, 0, v6
+; GFX9-NEXT: v_mul_lo_u32 v15, v15, v14
+; GFX9-NEXT: v_sub_u32_e32 v19, 0, v7
+; GFX9-NEXT: v_mul_lo_u32 v17, v17, v16
+; GFX9-NEXT: v_mul_lo_u32 v19, v19, v18
+; GFX9-NEXT: v_mul_hi_u32 v13, v12, v13
+; GFX9-NEXT: v_mul_hi_u32 v15, v14, v15
+; GFX9-NEXT: v_mul_hi_u32 v17, v16, v17
+; GFX9-NEXT: v_mul_hi_u32 v19, v18, v19
+; GFX9-NEXT: v_add_u32_e32 v12, v12, v13
+; GFX9-NEXT: v_mul_hi_u32 v12, v0, v12
+; GFX9-NEXT: v_add_u32_e32 v13, v14, v15
+; GFX9-NEXT: v_add_u32_e32 v14, v16, v17
+; GFX9-NEXT: v_mul_hi_u32 v13, v1, v13
+; GFX9-NEXT: v_add_u32_e32 v15, v18, v19
+; GFX9-NEXT: v_mul_hi_u32 v14, v2, v14
+; GFX9-NEXT: v_mul_hi_u32 v15, v3, v15
+; GFX9-NEXT: v_mul_lo_u32 v16, v12, v4
+; GFX9-NEXT: v_mul_lo_u32 v18, v13, v5
+; GFX9-NEXT: v_mul_lo_u32 v19, v14, v6
+; GFX9-NEXT: v_add_u32_e32 v17, 1, v12
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v16
+; GFX9-NEXT: v_mul_lo_u32 v16, v15, v7
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v18
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; GFX9-NEXT: v_add_u32_e32 v18, 1, v13
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v19
+; GFX9-NEXT: v_cndmask_b32_e32 v12, v12, v17, vcc
+; GFX9-NEXT: v_sub_u32_e32 v17, v0, v4
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[0:1], v1, v5
+; GFX9-NEXT: v_add_u32_e32 v19, 1, v14
+; GFX9-NEXT: v_sub_u32_e32 v3, v3, v16
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v18, s[0:1]
+; GFX9-NEXT: v_sub_u32_e32 v18, v1, v5
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[2:3], v2, v6
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc
+; GFX9-NEXT: v_add_u32_e32 v16, 1, v15
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v19, s[2:3]
+; GFX9-NEXT: v_sub_u32_e32 v19, v2, v6
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v7
+; GFX9-NEXT: v_add_u32_e32 v17, 1, v12
+; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v18, s[0:1]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; GFX9-NEXT: v_sub_u32_e32 v16, v3, v7
+; GFX9-NEXT: v_add_u32_e32 v18, 1, v13
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v19, s[2:3]
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v12, v17, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5
+; GFX9-NEXT: v_add_u32_e32 v19, 1, v14
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v13, v18, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
+; GFX9-NEXT: v_add_u32_e32 v16, 1, v15
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v14, v19, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v15, v16, vcc
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v8
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v9
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v10
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v11
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v8
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v9
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v10
+; GFX9-NEXT: v_sub_u32_e32 v3, v3, v11
+; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
; GFX9-NEXT: s_endpgm
;
; EG-LABEL: sdiv_v4i32:
@@ -2065,41 +2051,39 @@ define amdgpu_kernel void @v_sdiv_i25(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_mov_b32 s4, s10
; GFX9-NEXT: s_mov_b32 s5, s11
; GFX9-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
+; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: s_bfe_i32 s4, s0, 0x190000
-; GFX9-NEXT: s_abs_i32 s5, s4
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GFX9-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9-NEXT: s_mov_b32 s0, s8
-; GFX9-NEXT: s_sub_i32 s7, 0, s5
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX9-NEXT: s_bfe_i32 s6, s6, 0x190000
-; GFX9-NEXT: s_xor_b32 s4, s6, s4
-; GFX9-NEXT: s_abs_i32 s6, s6
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: s_ashr_i32 s4, s4, 31
-; GFX9-NEXT: v_readfirstlane_b32 s8, v0
-; GFX9-NEXT: s_mul_i32 s7, s7, s8
-; GFX9-NEXT: s_mul_hi_u32 s7, s8, s7
-; GFX9-NEXT: s_add_i32 s8, s8, s7
-; GFX9-NEXT: s_mul_hi_u32 s7, s6, s8
-; GFX9-NEXT: s_mul_i32 s8, s7, s5
-; GFX9-NEXT: s_sub_i32 s6, s6, s8
-; GFX9-NEXT: s_add_i32 s9, s7, 1
-; GFX9-NEXT: s_sub_i32 s8, s6, s5
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s7, s9, s7
-; GFX9-NEXT: s_cselect_b32 s6, s8, s6
-; GFX9-NEXT: s_add_i32 s8, s7, 1
-; GFX9-NEXT: s_cmp_ge_u32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s8, s7
-; GFX9-NEXT: s_xor_b32 s5, s5, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s4
-; GFX9-NEXT: s_bfe_i32 s4, s4, 0x190000
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 25
+; GFX9-NEXT: v_sub_u32_e32 v2, 0, v1
+; GFX9-NEXT: v_max_i32_e32 v2, v1, v2
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v2
+; GFX9-NEXT: v_sub_u32_e32 v4, 0, v2
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 25
+; GFX9-NEXT: v_sub_u32_e32 v5, 0, v0
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX9-NEXT: v_max_i32_e32 v5, v0, v5
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v4, v3
+; GFX9-NEXT: v_mul_hi_u32 v4, v3, v4
+; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3
+; GFX9-NEXT: v_mul_lo_u32 v4, v3, v2
+; GFX9-NEXT: v_add_u32_e32 v1, 1, v3
+; GFX9-NEXT: v_sub_u32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, v4, v2
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 1, v1
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 25
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index a166c4f93462d..367cb5cf3bf04 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -607,22 +607,19 @@ define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s3, s2, s9
-; GCN-NEXT: s_sub_i32 s0, s0, s3
-; GCN-NEXT: s_add_i32 s8, s2, 1
-; GCN-NEXT: s_sub_i32 s3, s0, s9
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-NEXT: s_add_i32 s3, s2, 1
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
@@ -648,22 +645,19 @@ define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-IR-NEXT: s_mul_i32 s3, s2, s9
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s3
-; GCN-IR-NEXT: s_add_i32 s8, s2, 1
-; GCN-IR-NEXT: s_sub_i32 s3, s0, s9
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-IR-NEXT: s_add_i32 s3, s2, 1
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-IR-NEXT: s_xor_b32 s0, s0, s1
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s1
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 32
@@ -699,22 +693,19 @@ define amdgpu_kernel void @s_test_sdiv31_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: s_ashr_i32 s1, s1, 31
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s3, s2, s9
-; GCN-NEXT: s_sub_i32 s0, s0, s3
-; GCN-NEXT: s_add_i32 s8, s2, 1
-; GCN-NEXT: s_sub_i32 s3, s0, s9
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-NEXT: s_add_i32 s3, s2, 1
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
@@ -743,22 +734,19 @@ define amdgpu_kernel void @s_test_sdiv31_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_ashr_i32 s1, s1, 31
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-IR-NEXT: s_mul_i32 s3, s2, s9
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s3
-; GCN-IR-NEXT: s_add_i32 s8, s2, 1
-; GCN-IR-NEXT: s_sub_i32 s3, s0, s9
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-IR-NEXT: s_add_i32 s3, s2, 1
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-IR-NEXT: s_xor_b32 s0, s0, s1
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s1
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 33
@@ -861,22 +849,19 @@ define amdgpu_kernel void @s_test_sdiv25_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: s_ashr_i32 s1, s1, 31
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s3, s2, s9
-; GCN-NEXT: s_sub_i32 s0, s0, s3
-; GCN-NEXT: s_add_i32 s8, s2, 1
-; GCN-NEXT: s_sub_i32 s3, s0, s9
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-NEXT: s_add_i32 s3, s2, 1
-; GCN-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-NEXT: s_xor_b32 s0, s0, s1
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
@@ -905,22 +890,19 @@ define amdgpu_kernel void @s_test_sdiv25_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_ashr_i32 s1, s1, 31
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s0, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-IR-NEXT: s_mul_i32 s3, s2, s9
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s3
-; GCN-IR-NEXT: s_add_i32 s8, s2, 1
-; GCN-IR-NEXT: s_sub_i32 s3, s0, s9
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s2, s8, s2
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s0
-; GCN-IR-NEXT: s_add_i32 s3, s2, 1
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s9
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, s2
-; GCN-IR-NEXT: s_xor_b32 s0, s0, s1
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s1
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v0, s9
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s9, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s1, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 39
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index 68dad8a5347b5..e57962199fd7a 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -1868,116 +1868,62 @@ define amdgpu_kernel void @pulled_out_test(ptr addrspace(1) %sourceA, ptr addrsp
; NOSDWA-NEXT: v_mov_b32_e32 v0, s0
; NOSDWA-NEXT: v_mov_b32_e32 v1, s1
; NOSDWA-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; NOSDWA-NEXT: v_mov_b32_e32 v3, s3
; NOSDWA-NEXT: v_mov_b32_e32 v2, s2
+; NOSDWA-NEXT: v_mov_b32_e32 v3, s3
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
-; NOSDWA-NEXT: v_readfirstlane_b32 s0, v1
-; NOSDWA-NEXT: v_readfirstlane_b32 s1, v0
-; NOSDWA-NEXT: s_lshr_b32 s3, s1, 24
-; NOSDWA-NEXT: s_lshr_b32 s5, s0, 24
-; NOSDWA-NEXT: s_and_b32 s2, s1, 0xffff
-; NOSDWA-NEXT: s_bfe_u32 s1, s1, 0x80010
-; NOSDWA-NEXT: s_and_b32 s4, s0, 0xffff
-; NOSDWA-NEXT: s_bfe_u32 s0, s0, 0x80010
-; NOSDWA-NEXT: s_lshl_b32 s3, s3, 8
-; NOSDWA-NEXT: s_lshl_b32 s5, s5, 8
-; NOSDWA-NEXT: s_or_b32 s1, s1, s3
-; NOSDWA-NEXT: s_or_b32 s0, s0, s5
-; NOSDWA-NEXT: s_lshl_b32 s1, s1, 16
-; NOSDWA-NEXT: s_lshl_b32 s0, s0, 16
-; NOSDWA-NEXT: s_or_b32 s1, s2, s1
-; NOSDWA-NEXT: s_or_b32 s0, s4, s0
-; NOSDWA-NEXT: v_mov_b32_e32 v0, s1
-; NOSDWA-NEXT: v_mov_b32_e32 v1, s0
+; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 24, v0
+; NOSDWA-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; NOSDWA-NEXT: v_and_b32_e32 v4, 0xffff, v0
+; NOSDWA-NEXT: v_bfe_u32 v0, v0, 16, 8
+; NOSDWA-NEXT: v_and_b32_e32 v6, 0xffff, v1
+; NOSDWA-NEXT: v_bfe_u32 v1, v1, 16, 8
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v7, 8, v7
+; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v5
+; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v7
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; NOSDWA-NEXT: v_or_b32_e32 v0, v4, v0
+; NOSDWA-NEXT: v_or_b32_e32 v1, v6, v1
; NOSDWA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
; GFX89-LABEL: pulled_out_test:
; GFX89: ; %bb.0: ; %entry
; GFX89-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX89-NEXT: v_mov_b32_e32 v4, 8
; GFX89-NEXT: s_waitcnt lgkmcnt(0)
; GFX89-NEXT: v_mov_b32_e32 v0, s0
; GFX89-NEXT: v_mov_b32_e32 v1, s1
; GFX89-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
-; GFX89-NEXT: v_mov_b32_e32 v3, s3
; GFX89-NEXT: v_mov_b32_e32 v2, s2
+; GFX89-NEXT: v_mov_b32_e32 v3, s3
; GFX89-NEXT: s_waitcnt vmcnt(0)
-; GFX89-NEXT: v_readfirstlane_b32 s0, v1
-; GFX89-NEXT: v_readfirstlane_b32 s1, v0
-; GFX89-NEXT: s_lshr_b32 s3, s1, 24
-; GFX89-NEXT: s_lshr_b32 s5, s0, 24
-; GFX89-NEXT: s_and_b32 s2, s1, 0xffff
-; GFX89-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX89-NEXT: s_and_b32 s4, s0, 0xffff
-; GFX89-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX89-NEXT: s_lshl_b32 s3, s3, 8
-; GFX89-NEXT: s_lshl_b32 s5, s5, 8
-; GFX89-NEXT: s_or_b32 s1, s1, s3
-; GFX89-NEXT: s_or_b32 s0, s0, s5
-; GFX89-NEXT: s_lshl_b32 s1, s1, 16
-; GFX89-NEXT: s_lshl_b32 s0, s0, 16
-; GFX89-NEXT: s_or_b32 s1, s2, s1
-; GFX89-NEXT: s_or_b32 s0, s4, s0
-; GFX89-NEXT: v_mov_b32_e32 v0, s1
-; GFX89-NEXT: v_mov_b32_e32 v1, s0
+; GFX89-NEXT: v_lshlrev_b32_sdwa v5, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX89-NEXT: v_lshlrev_b32_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX89-NEXT: v_or_b32_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+; GFX89-NEXT: v_or_b32_sdwa v4, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+; GFX89-NEXT: v_or_b32_sdwa v0, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX89-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX89-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX89-NEXT: s_endpgm
;
-; GFX9-LABEL: pulled_out_test:
-; GFX9: ; %bb.0: ; %entry
-; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT: v_mov_b32_e32 v2, 0
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
-; GFX9-NEXT: s_lshr_b32 s5, s1, 24
-; GFX9-NEXT: s_lshr_b32 s7, s0, 24
-; GFX9-NEXT: s_and_b32 s4, s1, 0xffff
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX9-NEXT: s_and_b32 s6, s0, 0xffff
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX9-NEXT: s_lshl_b32 s5, s5, 8
-; GFX9-NEXT: s_lshl_b32 s7, s7, 8
-; GFX9-NEXT: s_or_b32 s1, s1, s5
-; GFX9-NEXT: s_or_b32 s0, s0, s7
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: s_or_b32 s1, s4, s1
-; GFX9-NEXT: s_or_b32 s0, s6, s0
-; GFX9-NEXT: v_mov_b32_e32 v0, s1
-; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
-; GFX9-NEXT: s_endpgm
-;
-; GFX10-LABEL: pulled_out_test:
-; GFX10: ; %bb.0: ; %entry
-; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX10-NEXT: v_mov_b32_e32 v2, 0
-; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: s_lshr_b32 s5, s0, 24
-; GFX10-NEXT: s_lshr_b32 s7, s1, 24
-; GFX10-NEXT: s_and_b32 s4, s0, 0xffff
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX10-NEXT: s_and_b32 s6, s1, 0xffff
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_lshl_b32 s7, s7, 8
-; GFX10-NEXT: s_or_b32 s0, s0, s5
-; GFX10-NEXT: s_or_b32 s1, s1, s7
-; GFX10-NEXT: s_lshl_b32 s0, s0, 16
-; GFX10-NEXT: s_lshl_b32 s1, s1, 16
-; GFX10-NEXT: s_or_b32 s0, s4, s0
-; GFX10-NEXT: s_or_b32 s1, s6, s1
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
-; GFX10-NEXT: s_endpgm
+; GFX9_10-LABEL: pulled_out_test:
+; GFX9_10: ; %bb.0: ; %entry
+; GFX9_10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9_10-NEXT: v_mov_b32_e32 v2, 0
+; GFX9_10-NEXT: v_mov_b32_e32 v3, 8
+; GFX9_10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9_10-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX9_10-NEXT: s_waitcnt vmcnt(0)
+; GFX9_10-NEXT: v_lshlrev_b32_sdwa v4, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9_10-NEXT: v_lshlrev_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9_10-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+; GFX9_10-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+; GFX9_10-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9_10-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9_10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX9_10-NEXT: s_endpgm
entry:
%idxprom = ashr exact i64 15, 32
%arrayidx = getelementptr inbounds <8 x i8>, ptr addrspace(1) %sourceA, i64 %idxprom
@@ -2290,5 +2236,4 @@ declare i32 @llvm.amdgcn.workitem.id.x()
attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
-; GFX9_10: {{.*}}
; SDWA: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index fe47663b11028..840f3554b9457 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -899,42 +899,32 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v2, s2
-; VI-NEXT: v_readfirstlane_b32 s0, v4
-; VI-NEXT: v_readfirstlane_b32 s1, v5
-; VI-NEXT: s_ashr_i32 s3, s0, 16
-; VI-NEXT: s_ashr_i32 s5, s1, 16
-; VI-NEXT: s_cmp_gt_i32 s3, s5
-; VI-NEXT: s_sext_i32_i16 s2, s0
-; VI-NEXT: s_sext_i32_i16 s4, s1
-; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
-; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; VI-NEXT: s_cselect_b32 s0, s3, s5
-; VI-NEXT: s_cselect_b32 s3, s5, s3
-; VI-NEXT: s_lshl_b32 s5, s0, 16
-; VI-NEXT: s_cmp_gt_i32 s2, s4
-; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
-; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; VI-NEXT: s_cselect_b32 s0, s2, s4
-; VI-NEXT: s_cselect_b32 s1, s4, s2
-; VI-NEXT: s_and_b32 s0, s0, 0xffff
-; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v4
-; VI-NEXT: s_lshl_b32 s2, s3, 16
-; VI-NEXT: s_and_b32 s1, s1, 0xffff
-; VI-NEXT: s_or_b32 s0, s0, s5
-; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: s_or_b32 s1, s1, s2
-; VI-NEXT: v_mov_b32_e32 v5, s0
-; VI-NEXT: v_and_b32_e32 v4, 3, v4
-; VI-NEXT: v_mov_b32_e32 v6, s1
+; VI-NEXT: v_mov_b32_e32 v3, s3
+; VI-NEXT: v_bfe_i32 v6, v4, 0, 16
+; VI-NEXT: v_ashrrev_i32_e32 v4, 16, v4
+; VI-NEXT: v_bfe_i32 v7, v5, 0, 16
+; VI-NEXT: v_ashrrev_i32_e32 v5, 16, v5
+; VI-NEXT: v_cmp_gt_i32_e32 vcc, v4, v5
+; VI-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc
+; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], v6, v7
+; VI-NEXT: v_cndmask_b32_e64 v9, v7, v6, s[0:1]
+; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v8
+; VI-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[0:1]
+; VI-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; VI-NEXT: v_or_b32_sdwa v5, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v7, 1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: flat_store_dword v[0:1], v5
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_store_dword v[2:3], v6
+; VI-NEXT: v_or_b32_e32 v0, v8, v7
+; VI-NEXT: v_or_b32_sdwa v4, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_and_b32_e32 v0, 3, v0
+; VI-NEXT: flat_store_dword v[2:3], v4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_store_byte v[0:1], v4
+; VI-NEXT: flat_store_byte v[0:1], v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/sra.ll b/llvm/test/CodeGen/AMDGPU/sra.ll
index 67c51286de216..193fbec18d853 100644
--- a/llvm/test/CodeGen/AMDGPU/sra.ll
+++ b/llvm/test/CodeGen/AMDGPU/sra.ll
@@ -159,17 +159,14 @@ define amdgpu_kernel void @ashr_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s0, v0
-; SI-NEXT: v_readfirstlane_b32 s1, v1
-; SI-NEXT: s_sext_i32_i16 s2, s0
-; SI-NEXT: s_ashr_i32 s0, s0, 16
-; SI-NEXT: s_lshr_b32 s3, s1, 16
-; SI-NEXT: s_ashr_i32 s0, s0, s3
-; SI-NEXT: s_ashr_i32 s1, s2, s1
-; SI-NEXT: s_lshl_b32 s0, s0, 16
-; SI-NEXT: s_and_b32 s1, s1, 0xffff
-; SI-NEXT: s_or_b32 s0, s1, s0
-; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_bfe_i32 v2, v0, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; SI-NEXT: v_ashr_i32_e32 v0, v0, v3
+; SI-NEXT: v_ashr_i32_e32 v1, v2, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -187,18 +184,9 @@ define amdgpu_kernel void @ashr_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s0, v1
-; VI-NEXT: v_readfirstlane_b32 s1, v0
-; VI-NEXT: s_ashr_i32 s2, s1, 16
-; VI-NEXT: s_sext_i32_i16 s1, s1
-; VI-NEXT: s_ashr_i32 s3, s0, 16
-; VI-NEXT: s_sext_i32_i16 s0, s0
-; VI-NEXT: s_ashr_i32 s0, s1, s0
-; VI-NEXT: s_ashr_i32 s1, s2, s3
-; VI-NEXT: s_lshl_b32 s1, s1, 16
-; VI-NEXT: s_and_b32 s0, s0, 0xffff
-; VI-NEXT: s_or_b32 s0, s0, s1
-; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_ashrrev_i32_sdwa v2, sext(v1), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; VI-NEXT: v_ashrrev_i32_sdwa v0, sext(v1), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -255,70 +243,46 @@ define amdgpu_kernel void @ashr_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %i
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_readfirstlane_b32 s0, v3
-; SI-NEXT: v_readfirstlane_b32 s1, v2
-; SI-NEXT: v_readfirstlane_b32 s2, v1
-; SI-NEXT: v_readfirstlane_b32 s3, v0
-; SI-NEXT: s_sext_i32_i16 s8, s3
-; SI-NEXT: s_ashr_i32 s3, s3, 16
-; SI-NEXT: s_sext_i32_i16 s9, s2
-; SI-NEXT: s_ashr_i32 s2, s2, 16
-; SI-NEXT: s_lshr_b32 s10, s1, 16
-; SI-NEXT: s_lshr_b32 s11, s0, 16
-; SI-NEXT: s_ashr_i32 s2, s2, s11
-; SI-NEXT: s_ashr_i32 s0, s9, s0
-; SI-NEXT: s_ashr_i32 s3, s3, s10
-; SI-NEXT: s_ashr_i32 s1, s8, s1
-; SI-NEXT: s_lshl_b32 s2, s2, 16
-; SI-NEXT: s_and_b32 s0, s0, 0xffff
-; SI-NEXT: s_lshl_b32 s3, s3, 16
-; SI-NEXT: s_and_b32 s1, s1, 0xffff
-; SI-NEXT: s_or_b32 s0, s0, s2
-; SI-NEXT: s_or_b32 s1, s1, s3
-; SI-NEXT: v_mov_b32_e32 v0, s1
-; SI-NEXT: v_mov_b32_e32 v1, s0
+; SI-NEXT: v_bfe_i32 v4, v0, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v0, 16, v0
+; SI-NEXT: v_bfe_i32 v5, v1, 0, 16
+; SI-NEXT: v_ashrrev_i32_e32 v1, 16, v1
+; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; SI-NEXT: v_ashr_i32_e32 v1, v1, v7
+; SI-NEXT: v_ashr_i32_e32 v3, v5, v3
+; SI-NEXT: v_ashr_i32_e32 v0, v0, v6
+; SI-NEXT: v_ashr_i32_e32 v2, v4, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: ashr_v4i16:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
-; VI-NEXT: s_mov_b32 s3, 0xf000
-; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: s_mov_b32 s10, s2
-; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s10, s6
+; VI-NEXT: s_mov_b32 s11, s7
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s8, s6
-; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: s_mov_b32 s8, s2
+; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; VI-NEXT: s_mov_b32 s0, s4
-; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_readfirstlane_b32 s4, v2
-; VI-NEXT: v_readfirstlane_b32 s5, v3
-; VI-NEXT: v_readfirstlane_b32 s6, v0
-; VI-NEXT: v_readfirstlane_b32 s7, v1
-; VI-NEXT: s_ashr_i32 s8, s7, 16
-; VI-NEXT: s_sext_i32_i16 s7, s7
-; VI-NEXT: s_ashr_i32 s9, s6, 16
-; VI-NEXT: s_sext_i32_i16 s6, s6
-; VI-NEXT: s_ashr_i32 s10, s5, 16
-; VI-NEXT: s_sext_i32_i16 s5, s5
-; VI-NEXT: s_ashr_i32 s11, s4, 16
-; VI-NEXT: s_sext_i32_i16 s4, s4
-; VI-NEXT: s_ashr_i32 s4, s6, s4
-; VI-NEXT: s_ashr_i32 s6, s9, s11
-; VI-NEXT: s_ashr_i32 s5, s7, s5
-; VI-NEXT: s_ashr_i32 s7, s8, s10
-; VI-NEXT: s_lshl_b32 s7, s7, 16
-; VI-NEXT: s_and_b32 s5, s5, 0xffff
-; VI-NEXT: s_lshl_b32 s6, s6, 16
-; VI-NEXT: s_and_b32 s4, s4, 0xffff
-; VI-NEXT: s_or_b32 s5, s5, s7
-; VI-NEXT: s_or_b32 s4, s4, s6
-; VI-NEXT: v_mov_b32_e32 v0, s4
-; VI-NEXT: v_mov_b32_e32 v1, s5
-; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: v_ashrrev_i32_sdwa v4, sext(v2), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; VI-NEXT: v_ashrrev_i32_sdwa v0, sext(v2), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_ashrrev_i32_sdwa v2, sext(v3), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; VI-NEXT: v_ashrrev_i32_sdwa v1, sext(v3), sext(v1) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm
;
; EG-LABEL: ashr_v4i16:
diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll
index 6423267be4b34..e4b78700ed99b 100644
--- a/llvm/test/CodeGen/AMDGPU/srem.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem.ll
@@ -11,15 +11,15 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_ushort v1, v0, s[2:3]
+; GCN-NEXT: s_movk_i32 s2, 0x4925
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s2, v1
-; GCN-NEXT: s_sext_i32_i16 s2, s2
-; GCN-NEXT: s_mulk_i32 s2, 0x4925
-; GCN-NEXT: s_lshr_b32 s3, s2, 31
-; GCN-NEXT: s_ashr_i32 s2, s2, 17
-; GCN-NEXT: s_add_i32 s2, s2, s3
-; GCN-NEXT: s_mul_i32 s2, s2, 7
-; GCN-NEXT: v_subrev_u32_e32 v1, s2, v1
+; GCN-NEXT: v_bfe_i32 v2, v1, 0, 16
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s2
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 31, v2
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 17, v2
+; GCN-NEXT: v_add_u32_e32 v2, v2, v3
+; GCN-NEXT: v_mul_lo_u32 v2, v2, 7
+; GCN-NEXT: v_sub_u32_e32 v1, v1, v2
; GCN-NEXT: global_store_short v0, v1, s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -34,16 +34,16 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: s_mov_b32 s8, s2
; TAHITI-NEXT: s_mov_b32 s9, s3
; TAHITI-NEXT: buffer_load_sshort v0, off, s[8:11], 0
+; TAHITI-NEXT: s_movk_i32 s2, 0x4925
; TAHITI-NEXT: s_mov_b32 s4, s0
; TAHITI-NEXT: s_mov_b32 s5, s1
; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: s_mulk_i32 s0, 0x4925
-; TAHITI-NEXT: s_lshr_b32 s1, s0, 31
-; TAHITI-NEXT: s_ashr_i32 s0, s0, 17
-; TAHITI-NEXT: s_add_i32 s0, s0, s1
-; TAHITI-NEXT: s_mul_i32 s0, s0, 7
-; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; TAHITI-NEXT: v_mul_lo_u32 v1, v0, s2
+; TAHITI-NEXT: v_lshrrev_b32_e32 v2, 31, v1
+; TAHITI-NEXT: v_ashrrev_i32_e32 v1, 17, v1
+; TAHITI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; TAHITI-NEXT: v_mul_lo_u32 v1, v1, 7
+; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; TAHITI-NEXT: buffer_store_short v0, off, s[4:7], 0
; TAHITI-NEXT: s_endpgm
;
@@ -54,17 +54,17 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_mov_b32_e32 v0, s2
; TONGA-NEXT: v_mov_b32_e32 v1, s3
; TONGA-NEXT: flat_load_ushort v2, v[0:1]
+; TONGA-NEXT: s_movk_i32 s2, 0x4925
+; TONGA-NEXT: s_waitcnt vmcnt(0)
+; TONGA-NEXT: v_bfe_i32 v0, v2, 0, 16
+; TONGA-NEXT: v_mul_lo_u32 v0, v0, s2
+; TONGA-NEXT: v_lshrrev_b32_e32 v1, 31, v0
+; TONGA-NEXT: v_ashrrev_i32_e32 v0, 17, v0
+; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; TONGA-NEXT: v_mul_lo_u32 v3, v0, 7
; TONGA-NEXT: v_mov_b32_e32 v0, s0
; TONGA-NEXT: v_mov_b32_e32 v1, s1
-; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s0, v2
-; TONGA-NEXT: s_sext_i32_i16 s0, s0
-; TONGA-NEXT: s_mulk_i32 s0, 0x4925
-; TONGA-NEXT: s_lshr_b32 s1, s0, 31
-; TONGA-NEXT: s_ashr_i32 s0, s0, 17
-; TONGA-NEXT: s_add_i32 s0, s0, s1
-; TONGA-NEXT: s_mul_i32 s0, s0, 7
-; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, s0, v2
+; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, v3, v2
; TONGA-NEXT: flat_store_short v[0:1], v2
; TONGA-NEXT: s_endpgm
;
@@ -118,32 +118,30 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s2, v1
-; GCN-NEXT: s_abs_i32 s2, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_sub_i32 s5, 0, s2
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: s_abs_i32 s3, s3
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s6, v0
-; GCN-NEXT: s_mul_i32 s5, s5, s6
-; GCN-NEXT: s_mul_hi_u32 s5, s6, s5
-; GCN-NEXT: s_add_i32 s6, s6, s5
-; GCN-NEXT: s_mul_hi_u32 s5, s3, s6
-; GCN-NEXT: s_mul_i32 s5, s5, s2
-; GCN-NEXT: s_sub_i32 s3, s3, s5
-; GCN-NEXT: s_sub_i32 s5, s3, s2
-; GCN-NEXT: s_cmp_ge_u32 s3, s2
-; GCN-NEXT: s_cselect_b32 s3, s5, s3
-; GCN-NEXT: s_sub_i32 s5, s3, s2
-; GCN-NEXT: s_cmp_ge_u32 s3, s2
-; GCN-NEXT: s_cselect_b32 s2, s5, s3
-; GCN-NEXT: s_xor_b32 s2, s2, s4
-; GCN-NEXT: s_sub_i32 s2, s2, s4
-; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_sub_u32_e32 v3, 0, v1
+; GCN-NEXT: v_max_i32_e32 v1, v1, v3
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GCN-NEXT: v_sub_u32_e32 v4, 0, v1
+; GCN-NEXT: v_sub_u32_e32 v5, 0, v0
+; GCN-NEXT: v_max_i32_e32 v5, v0, v5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GCN-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_mul_lo_u32 v4, v4, v3
+; GCN-NEXT: v_mul_hi_u32 v4, v3, v4
+; GCN-NEXT: v_add_u32_e32 v3, v3, v4
+; GCN-NEXT: v_mul_hi_u32 v3, v5, v3
+; GCN-NEXT: v_mul_lo_u32 v3, v3, v1
+; GCN-NEXT: v_sub_u32_e32 v3, v5, v3
+; GCN-NEXT: v_sub_u32_e32 v4, v3, v1
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GCN-NEXT: v_sub_u32_e32 v4, v3, v1
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v0
+; GCN-NEXT: v_sub_u32_e32 v0, v1, v0
; GCN-NEXT: global_store_dword v2, v0, s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -158,35 +156,33 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
; TAHITI-NEXT: s_mov_b32 s8, s2
; TAHITI-NEXT: s_mov_b32 s9, s3
; TAHITI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; TAHITI-NEXT: s_mov_b32 s5, s1
; TAHITI-NEXT: s_mov_b32 s4, s0
+; TAHITI-NEXT: s_mov_b32 s5, s1
; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s2, v1
-; TAHITI-NEXT: s_abs_i32 s2, s2
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v1, s2
-; TAHITI-NEXT: s_sub_i32 s3, 0, s2
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; TAHITI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v1, v1
-; TAHITI-NEXT: v_mul_lo_u32 v2, s3, v1
-; TAHITI-NEXT: v_readfirstlane_b32 s3, v0
-; TAHITI-NEXT: s_abs_i32 s8, s3
-; TAHITI-NEXT: s_ashr_i32 s0, s3, 31
-; TAHITI-NEXT: v_mul_hi_u32 v2, v1, v2
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v1, v2
-; TAHITI-NEXT: v_mul_hi_u32 v0, s8, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s1, v0
-; TAHITI-NEXT: s_mul_i32 s1, s1, s2
-; TAHITI-NEXT: s_sub_i32 s1, s8, s1
-; TAHITI-NEXT: s_sub_i32 s3, s1, s2
-; TAHITI-NEXT: s_cmp_ge_u32 s1, s2
-; TAHITI-NEXT: s_cselect_b32 s1, s3, s1
-; TAHITI-NEXT: s_sub_i32 s3, s1, s2
-; TAHITI-NEXT: s_cmp_ge_u32 s1, s2
-; TAHITI-NEXT: s_cselect_b32 s1, s3, s1
-; TAHITI-NEXT: s_xor_b32 s1, s1, s0
-; TAHITI-NEXT: s_sub_i32 s0, s1, s0
-; TAHITI-NEXT: v_mov_b32_e32 v0, s0
+; TAHITI-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
+; TAHITI-NEXT: v_max_i32_e32 v1, v1, v2
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v2, v1
+; TAHITI-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
+; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; TAHITI-NEXT: v_max_i32_e32 v4, v0, v4
+; TAHITI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; TAHITI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v2, v2
+; TAHITI-NEXT: v_mul_lo_u32 v3, v3, v2
+; TAHITI-NEXT: v_mul_hi_u32 v3, v2, v3
+; TAHITI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; TAHITI-NEXT: v_mul_hi_u32 v2, v4, v2
+; TAHITI-NEXT: v_mul_lo_u32 v2, v2, v1
+; TAHITI-NEXT: v_sub_i32_e32 v2, vcc, v4, v2
+; TAHITI-NEXT: v_sub_i32_e32 v3, vcc, v2, v1
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v1
+; TAHITI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; TAHITI-NEXT: v_sub_i32_e32 v3, vcc, v2, v1
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v1
+; TAHITI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
+; TAHITI-NEXT: v_xor_b32_e32 v1, v1, v0
+; TAHITI-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; TAHITI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; TAHITI-NEXT: s_endpgm
;
@@ -198,35 +194,33 @@ define amdgpu_kernel void @srem_i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
; TONGA-NEXT: v_mov_b32_e32 v1, s3
; TONGA-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s2, v1
-; TONGA-NEXT: s_abs_i32 s2, s2
-; TONGA-NEXT: v_cvt_f32_u32_e32 v1, s2
-; TONGA-NEXT: s_sub_i32 s3, 0, s2
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, 0, v1
+; TONGA-NEXT: v_max_i32_e32 v3, v1, v2
+; TONGA-NEXT: v_cvt_f32_u32_e32 v1, v3
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, 0, v3
+; TONGA-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
; TONGA-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; TONGA-NEXT: v_max_i32_e32 v4, v0, v4
+; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v0
; TONGA-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; TONGA-NEXT: v_cvt_u32_f32_e32 v1, v1
-; TONGA-NEXT: v_mul_lo_u32 v2, s3, v1
-; TONGA-NEXT: v_readfirstlane_b32 s3, v0
-; TONGA-NEXT: s_abs_i32 s4, s3
+; TONGA-NEXT: v_mul_lo_u32 v2, v2, v1
; TONGA-NEXT: v_mul_hi_u32 v2, v1, v2
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v1, v2
-; TONGA-NEXT: v_mul_hi_u32 v2, s4, v0
-; TONGA-NEXT: v_mov_b32_e32 v1, s1
-; TONGA-NEXT: v_mov_b32_e32 v0, s0
-; TONGA-NEXT: s_ashr_i32 s0, s3, 31
-; TONGA-NEXT: v_readfirstlane_b32 s1, v2
-; TONGA-NEXT: s_mul_i32 s1, s1, s2
-; TONGA-NEXT: s_sub_i32 s1, s4, s1
-; TONGA-NEXT: s_sub_i32 s3, s1, s2
-; TONGA-NEXT: s_cmp_ge_u32 s1, s2
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_sub_i32 s3, s1, s2
-; TONGA-NEXT: s_cmp_ge_u32 s1, s2
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_xor_b32 s1, s1, s0
-; TONGA-NEXT: s_sub_i32 s0, s1, s0
-; TONGA-NEXT: v_mov_b32_e32 v2, s0
-; TONGA-NEXT: flat_store_dword v[0:1], v2
+; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v2
+; TONGA-NEXT: v_mul_hi_u32 v2, v4, v1
+; TONGA-NEXT: v_mov_b32_e32 v1, s0
+; TONGA-NEXT: v_mul_lo_u32 v5, v2, v3
+; TONGA-NEXT: v_mov_b32_e32 v2, s1
+; TONGA-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
+; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v4, v3
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v4, v3
+; TONGA-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v4, v3
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v4, v3
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v0
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v3, v0
+; TONGA-NEXT: flat_store_dword v[1:2], v0
; TONGA-NEXT: s_endpgm
;
; EG-LABEL: srem_i32:
@@ -464,58 +458,54 @@ define amdgpu_kernel void @srem_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s2, v2
-; GCN-NEXT: s_abs_i32 s2, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_sub_i32 s6, 0, s2
-; GCN-NEXT: s_ashr_i32 s5, s3, 31
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GCN-NEXT: s_abs_i32 s3, s3
-; GCN-NEXT: v_readfirstlane_b32 s4, v3
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s7, v0
-; GCN-NEXT: s_mul_i32 s6, s6, s7
-; GCN-NEXT: s_mul_hi_u32 s6, s7, s6
-; GCN-NEXT: s_add_i32 s7, s7, s6
-; GCN-NEXT: s_mul_hi_u32 s6, s3, s7
-; GCN-NEXT: s_mul_i32 s6, s6, s2
-; GCN-NEXT: s_sub_i32 s3, s3, s6
-; GCN-NEXT: s_sub_i32 s6, s3, s2
-; GCN-NEXT: s_cmp_ge_u32 s3, s2
-; GCN-NEXT: s_cselect_b32 s3, s6, s3
-; GCN-NEXT: s_sub_i32 s6, s3, s2
-; GCN-NEXT: s_cmp_ge_u32 s3, s2
-; GCN-NEXT: s_cselect_b32 s2, s6, s3
-; GCN-NEXT: s_abs_i32 s3, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GCN-NEXT: s_xor_b32 s2, s2, s5
-; GCN-NEXT: s_sub_i32 s7, 0, s3
-; GCN-NEXT: s_sub_i32 s2, s2, s5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s4, v1
-; GCN-NEXT: s_ashr_i32 s6, s4, 31
-; GCN-NEXT: s_abs_i32 s4, s4
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s5, v0
-; GCN-NEXT: s_mul_i32 s7, s7, s5
-; GCN-NEXT: s_mul_hi_u32 s7, s5, s7
-; GCN-NEXT: s_add_i32 s5, s5, s7
-; GCN-NEXT: s_mul_hi_u32 s5, s4, s5
-; GCN-NEXT: s_mul_i32 s5, s5, s3
-; GCN-NEXT: s_sub_i32 s4, s4, s5
-; GCN-NEXT: s_sub_i32 s5, s4, s3
-; GCN-NEXT: s_cmp_ge_u32 s4, s3
-; GCN-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-NEXT: s_sub_i32 s5, s4, s3
-; GCN-NEXT: s_cmp_ge_u32 s4, s3
-; GCN-NEXT: s_cselect_b32 s3, s5, s4
-; GCN-NEXT: s_xor_b32 s3, s3, s6
-; GCN-NEXT: s_sub_i32 s3, s3, s6
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NEXT: v_sub_u32_e32 v5, 0, v2
+; GCN-NEXT: v_sub_u32_e32 v6, 0, v3
+; GCN-NEXT: v_max_i32_e32 v2, v2, v5
+; GCN-NEXT: v_max_i32_e32 v3, v3, v6
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2
+; GCN-NEXT: v_cvt_f32_u32_e32 v6, v3
+; GCN-NEXT: v_sub_u32_e32 v7, 0, v2
+; GCN-NEXT: v_sub_u32_e32 v8, 0, v3
+; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GCN-NEXT: v_sub_u32_e32 v9, 0, v0
+; GCN-NEXT: v_sub_u32_e32 v10, 0, v1
+; GCN-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; GCN-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GCN-NEXT: v_max_i32_e32 v9, v0, v9
+; GCN-NEXT: v_max_i32_e32 v10, v1, v10
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v8, v6
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; GCN-NEXT: v_mul_hi_u32 v7, v5, v7
+; GCN-NEXT: v_mul_hi_u32 v8, v6, v8
+; GCN-NEXT: v_add_u32_e32 v5, v5, v7
+; GCN-NEXT: v_add_u32_e32 v6, v6, v8
+; GCN-NEXT: v_mul_hi_u32 v5, v9, v5
+; GCN-NEXT: v_mul_hi_u32 v6, v10, v6
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
+; GCN-NEXT: v_mul_lo_u32 v6, v6, v3
+; GCN-NEXT: v_sub_u32_e32 v5, v9, v5
+; GCN-NEXT: v_sub_u32_e32 v6, v10, v6
+; GCN-NEXT: v_sub_u32_e32 v7, v5, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v2
+; GCN-NEXT: v_sub_u32_e32 v8, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; GCN-NEXT: v_sub_u32_e32 v7, v5, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v2
+; GCN-NEXT: v_sub_u32_e32 v8, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
+; GCN-NEXT: v_cndmask_b32_e32 v3, v6, v8, vcc
+; GCN-NEXT: v_xor_b32_e32 v2, v2, v0
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v1
+; GCN-NEXT: v_sub_u32_e32 v0, v2, v0
+; GCN-NEXT: v_sub_u32_e32 v1, v3, v1
; GCN-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -530,61 +520,57 @@ define amdgpu_kernel void @srem_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: s_mov_b32 s8, s6
; TAHITI-NEXT: s_mov_b32 s9, s7
; TAHITI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v2
-; TAHITI-NEXT: s_abs_i32 s0, s0
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v2, s0
-; TAHITI-NEXT: s_sub_i32 s1, 0, s0
-; TAHITI-NEXT: v_readfirstlane_b32 s7, v3
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; TAHITI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v2, v2
-; TAHITI-NEXT: v_mul_lo_u32 v4, s1, v2
-; TAHITI-NEXT: v_readfirstlane_b32 s1, v0
-; TAHITI-NEXT: s_abs_i32 s6, s1
-; TAHITI-NEXT: s_ashr_i32 s8, s1, 31
-; TAHITI-NEXT: v_mul_hi_u32 v4, v2, v4
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v2, v4
-; TAHITI-NEXT: v_mul_hi_u32 v0, s6, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s1, v0
-; TAHITI-NEXT: s_mul_i32 s1, s1, s0
-; TAHITI-NEXT: s_sub_i32 s1, s6, s1
-; TAHITI-NEXT: s_sub_i32 s6, s1, s0
-; TAHITI-NEXT: s_cmp_ge_u32 s1, s0
-; TAHITI-NEXT: s_cselect_b32 s1, s6, s1
-; TAHITI-NEXT: s_sub_i32 s6, s1, s0
-; TAHITI-NEXT: s_cmp_ge_u32 s1, s0
-; TAHITI-NEXT: s_cselect_b32 s6, s6, s1
-; TAHITI-NEXT: s_abs_i32 s7, s7
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v0, s7
-; TAHITI-NEXT: s_sub_i32 s0, 0, s7
-; TAHITI-NEXT: s_mov_b32 s1, s5
-; TAHITI-NEXT: s_xor_b32 s6, s6, s8
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TAHITI-NEXT: s_sub_i32 s6, s6, s8
-; TAHITI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_lo_u32 v2, s0, v0
; TAHITI-NEXT: s_mov_b32 s0, s4
-; TAHITI-NEXT: v_readfirstlane_b32 s4, v1
-; TAHITI-NEXT: s_abs_i32 s5, s4
-; TAHITI-NEXT: v_mul_hi_u32 v2, v0, v2
-; TAHITI-NEXT: s_ashr_i32 s4, s4, 31
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; TAHITI-NEXT: v_mul_hi_u32 v0, s5, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s8, v0
-; TAHITI-NEXT: s_mul_i32 s8, s8, s7
-; TAHITI-NEXT: s_sub_i32 s5, s5, s8
-; TAHITI-NEXT: s_sub_i32 s8, s5, s7
-; TAHITI-NEXT: s_cmp_ge_u32 s5, s7
-; TAHITI-NEXT: s_cselect_b32 s5, s8, s5
-; TAHITI-NEXT: s_sub_i32 s8, s5, s7
-; TAHITI-NEXT: s_cmp_ge_u32 s5, s7
-; TAHITI-NEXT: s_cselect_b32 s5, s8, s5
-; TAHITI-NEXT: s_xor_b32 s5, s5, s4
-; TAHITI-NEXT: s_sub_i32 s4, s5, s4
-; TAHITI-NEXT: v_mov_b32_e32 v0, s6
-; TAHITI-NEXT: v_mov_b32_e32 v1, s4
+; TAHITI-NEXT: s_mov_b32 s1, s5
+; TAHITI-NEXT: s_waitcnt vmcnt(0)
+; TAHITI-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
+; TAHITI-NEXT: v_sub_i32_e32 v6, vcc, 0, v3
+; TAHITI-NEXT: v_max_i32_e32 v2, v2, v5
+; TAHITI-NEXT: v_max_i32_e32 v3, v3, v6
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v5, v2
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v6, v3
+; TAHITI-NEXT: v_sub_i32_e32 v8, vcc, 0, v2
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; TAHITI-NEXT: v_sub_i32_e32 v9, vcc, 0, v3
+; TAHITI-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; TAHITI-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v5, v5
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v6, v6
+; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
+; TAHITI-NEXT: v_mul_lo_u32 v8, v8, v5
+; TAHITI-NEXT: v_mul_lo_u32 v9, v9, v6
+; TAHITI-NEXT: v_sub_i32_e32 v7, vcc, 0, v1
+; TAHITI-NEXT: v_mul_hi_u32 v8, v5, v8
+; TAHITI-NEXT: v_mul_hi_u32 v9, v6, v9
+; TAHITI-NEXT: v_max_i32_e32 v4, v0, v4
+; TAHITI-NEXT: v_max_i32_e32 v7, v1, v7
+; TAHITI-NEXT: v_add_i32_e32 v5, vcc, v5, v8
+; TAHITI-NEXT: v_add_i32_e32 v6, vcc, v6, v9
+; TAHITI-NEXT: v_mul_hi_u32 v5, v4, v5
+; TAHITI-NEXT: v_mul_hi_u32 v6, v7, v6
+; TAHITI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; TAHITI-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; TAHITI-NEXT: v_mul_lo_u32 v5, v5, v2
+; TAHITI-NEXT: v_mul_lo_u32 v6, v6, v3
+; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, v4, v5
+; TAHITI-NEXT: v_sub_i32_e32 v5, vcc, v7, v6
+; TAHITI-NEXT: v_sub_i32_e32 v6, vcc, v4, v2
+; TAHITI-NEXT: v_sub_i32_e32 v7, vcc, v5, v3
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; TAHITI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
+; TAHITI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; TAHITI-NEXT: v_sub_i32_e32 v6, vcc, v4, v2
+; TAHITI-NEXT: v_sub_i32_e32 v7, vcc, v5, v3
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; TAHITI-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
+; TAHITI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; TAHITI-NEXT: v_xor_b32_e32 v2, v2, v0
+; TAHITI-NEXT: v_xor_b32_e32 v3, v3, v1
+; TAHITI-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
+; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v3, v1
; TAHITI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; TAHITI-NEXT: s_endpgm
;
@@ -595,62 +581,58 @@ define amdgpu_kernel void @srem_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: v_mov_b32_e32 v0, s2
; TONGA-NEXT: v_mov_b32_e32 v1, s3
; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; TONGA-NEXT: v_mov_b32_e32 v4, s0
+; TONGA-NEXT: v_mov_b32_e32 v5, s1
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s2, v2
-; TONGA-NEXT: s_abs_i32 s2, s2
-; TONGA-NEXT: v_cvt_f32_u32_e32 v2, s2
-; TONGA-NEXT: s_sub_i32 s3, 0, s2
-; TONGA-NEXT: v_readfirstlane_b32 s5, v3
-; TONGA-NEXT: v_mov_b32_e32 v3, s1
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; TONGA-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; TONGA-NEXT: v_cvt_u32_f32_e32 v2, v2
-; TONGA-NEXT: v_mul_lo_u32 v4, s3, v2
-; TONGA-NEXT: v_readfirstlane_b32 s3, v0
-; TONGA-NEXT: s_abs_i32 s4, s3
-; TONGA-NEXT: s_ashr_i32 s3, s3, 31
-; TONGA-NEXT: v_mul_hi_u32 v4, v2, v4
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v4
-; TONGA-NEXT: v_mul_hi_u32 v0, s4, v0
-; TONGA-NEXT: v_mov_b32_e32 v2, s0
-; TONGA-NEXT: v_readfirstlane_b32 s0, v1
-; TONGA-NEXT: v_readfirstlane_b32 s6, v0
-; TONGA-NEXT: s_mul_i32 s6, s6, s2
-; TONGA-NEXT: s_sub_i32 s4, s4, s6
-; TONGA-NEXT: s_sub_i32 s6, s4, s2
-; TONGA-NEXT: s_cmp_ge_u32 s4, s2
-; TONGA-NEXT: s_cselect_b32 s4, s6, s4
-; TONGA-NEXT: s_sub_i32 s6, s4, s2
-; TONGA-NEXT: s_cmp_ge_u32 s4, s2
-; TONGA-NEXT: s_cselect_b32 s2, s6, s4
-; TONGA-NEXT: s_abs_i32 s4, s5
-; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s4
-; TONGA-NEXT: s_sub_i32 s5, 0, s4
-; TONGA-NEXT: s_abs_i32 s1, s0
-; TONGA-NEXT: s_xor_b32 s2, s2, s3
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT: s_sub_i32 s2, s2, s3
-; TONGA-NEXT: s_ashr_i32 s0, s0, 31
-; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TONGA-NEXT: v_mul_lo_u32 v4, s5, v0
-; TONGA-NEXT: v_mul_hi_u32 v4, v0, v4
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v4
-; TONGA-NEXT: v_mul_hi_u32 v0, s1, v0
-; TONGA-NEXT: v_readfirstlane_b32 s3, v0
-; TONGA-NEXT: s_mul_i32 s3, s3, s4
-; TONGA-NEXT: s_sub_i32 s1, s1, s3
-; TONGA-NEXT: s_sub_i32 s3, s1, s4
-; TONGA-NEXT: s_cmp_ge_u32 s1, s4
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_sub_i32 s3, s1, s4
-; TONGA-NEXT: s_cmp_ge_u32 s1, s4
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_xor_b32 s1, s1, s0
-; TONGA-NEXT: s_sub_i32 s0, s1, s0
-; TONGA-NEXT: v_mov_b32_e32 v0, s2
-; TONGA-NEXT: v_mov_b32_e32 v1, s0
-; TONGA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; TONGA-NEXT: v_sub_u32_e32 v7, vcc, 0, v2
+; TONGA-NEXT: v_sub_u32_e32 v8, vcc, 0, v3
+; TONGA-NEXT: v_max_i32_e32 v2, v2, v7
+; TONGA-NEXT: v_max_i32_e32 v3, v3, v8
+; TONGA-NEXT: v_cvt_f32_u32_e32 v7, v2
+; TONGA-NEXT: v_cvt_f32_u32_e32 v8, v3
+; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v2
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v8, v8
+; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v3
+; TONGA-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
+; TONGA-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; TONGA-NEXT: v_cvt_u32_f32_e32 v7, v7
+; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v8
+; TONGA-NEXT: v_sub_u32_e32 v6, vcc, 0, v0
+; TONGA-NEXT: v_mul_lo_u32 v10, v10, v7
+; TONGA-NEXT: v_mul_lo_u32 v11, v11, v8
+; TONGA-NEXT: v_sub_u32_e32 v9, vcc, 0, v1
+; TONGA-NEXT: v_mul_hi_u32 v10, v7, v10
+; TONGA-NEXT: v_mul_hi_u32 v11, v8, v11
+; TONGA-NEXT: v_max_i32_e32 v6, v0, v6
+; TONGA-NEXT: v_max_i32_e32 v9, v1, v9
+; TONGA-NEXT: v_add_u32_e32 v7, vcc, v7, v10
+; TONGA-NEXT: v_add_u32_e32 v8, vcc, v8, v11
+; TONGA-NEXT: v_mul_hi_u32 v7, v6, v7
+; TONGA-NEXT: v_mul_hi_u32 v8, v9, v8
+; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; TONGA-NEXT: v_ashrrev_i32_e32 v1, 31, v1
+; TONGA-NEXT: v_mul_lo_u32 v7, v7, v2
+; TONGA-NEXT: v_mul_lo_u32 v8, v8, v3
+; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v6, v7
+; TONGA-NEXT: v_sub_u32_e32 v7, vcc, v9, v8
+; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v6, v2
+; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v7, v3
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
+; TONGA-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
+; TONGA-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
+; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v6, v2
+; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v7, v3
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
+; TONGA-NEXT: v_cndmask_b32_e32 v2, v6, v8, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
+; TONGA-NEXT: v_xor_b32_e32 v2, v2, v0
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v1
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v2, v0
+; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
+; TONGA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; TONGA-NEXT: s_endpgm
;
; EG-LABEL: srem_v2i32:
@@ -728,20 +710,16 @@ define amdgpu_kernel void @srem_v2i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: v_readfirstlane_b32 s3, v1
-; GCN-NEXT: s_ashr_i32 s4, s2, 31
-; GCN-NEXT: s_ashr_i32 s5, s3, 31
-; GCN-NEXT: s_lshr_b32 s4, s4, 30
-; GCN-NEXT: s_lshr_b32 s5, s5, 30
-; GCN-NEXT: s_add_i32 s4, s2, s4
-; GCN-NEXT: s_add_i32 s5, s3, s5
-; GCN-NEXT: s_and_b32 s4, s4, -4
-; GCN-NEXT: s_and_b32 s5, s5, -4
-; GCN-NEXT: s_sub_i32 s2, s2, s4
-; GCN-NEXT: s_sub_i32 s3, s3, s5
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GCN-NEXT: v_lshrrev_b32_e32 v3, 30, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v4, 30, v4
+; GCN-NEXT: v_add_u32_e32 v3, v0, v3
+; GCN-NEXT: v_add_u32_e32 v4, v1, v4
+; GCN-NEXT: v_and_b32_e32 v3, -4, v3
+; GCN-NEXT: v_and_b32_e32 v4, -4, v4
+; GCN-NEXT: v_sub_u32_e32 v0, v0, v3
+; GCN-NEXT: v_sub_u32_e32 v1, v1, v4
; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -759,20 +737,16 @@ define amdgpu_kernel void @srem_v2i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; TAHITI-NEXT: s_mov_b32 s4, s0
; TAHITI-NEXT: s_mov_b32 s5, s1
; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s1, v1
-; TAHITI-NEXT: s_ashr_i32 s2, s0, 31
-; TAHITI-NEXT: s_ashr_i32 s3, s1, 31
-; TAHITI-NEXT: s_lshr_b32 s2, s2, 30
-; TAHITI-NEXT: s_lshr_b32 s3, s3, 30
-; TAHITI-NEXT: s_add_i32 s2, s0, s2
-; TAHITI-NEXT: s_add_i32 s3, s1, s3
-; TAHITI-NEXT: s_and_b32 s2, s2, -4
-; TAHITI-NEXT: s_and_b32 s3, s3, -4
-; TAHITI-NEXT: s_sub_i32 s0, s0, s2
-; TAHITI-NEXT: s_sub_i32 s1, s1, s3
-; TAHITI-NEXT: v_mov_b32_e32 v0, s0
-; TAHITI-NEXT: v_mov_b32_e32 v1, s1
+; TAHITI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
+; TAHITI-NEXT: v_ashrrev_i32_e32 v3, 31, v1
+; TAHITI-NEXT: v_lshrrev_b32_e32 v2, 30, v2
+; TAHITI-NEXT: v_lshrrev_b32_e32 v3, 30, v3
+; TAHITI-NEXT: v_add_i32_e32 v2, vcc, v2, v0
+; TAHITI-NEXT: v_add_i32_e32 v3, vcc, v3, v1
+; TAHITI-NEXT: v_and_b32_e32 v2, -4, v2
+; TAHITI-NEXT: v_and_b32_e32 v3, -4, v3
+; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0
+; TAHITI-NEXT: v_subrev_i32_e32 v1, vcc, v3, v1
; TAHITI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; TAHITI-NEXT: s_endpgm
;
@@ -786,20 +760,16 @@ define amdgpu_kernel void @srem_v2i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; TONGA-NEXT: v_mov_b32_e32 v2, s0
; TONGA-NEXT: v_mov_b32_e32 v3, s1
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s0, v0
-; TONGA-NEXT: v_readfirstlane_b32 s1, v1
-; TONGA-NEXT: s_ashr_i32 s2, s0, 31
-; TONGA-NEXT: s_ashr_i32 s3, s1, 31
-; TONGA-NEXT: s_lshr_b32 s2, s2, 30
-; TONGA-NEXT: s_lshr_b32 s3, s3, 30
-; TONGA-NEXT: s_add_i32 s2, s0, s2
-; TONGA-NEXT: s_add_i32 s3, s1, s3
-; TONGA-NEXT: s_and_b32 s2, s2, -4
-; TONGA-NEXT: s_and_b32 s3, s3, -4
-; TONGA-NEXT: s_sub_i32 s0, s0, s2
-; TONGA-NEXT: s_sub_i32 s1, s1, s3
-; TONGA-NEXT: v_mov_b32_e32 v0, s0
-; TONGA-NEXT: v_mov_b32_e32 v1, s1
+; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v0
+; TONGA-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; TONGA-NEXT: v_lshrrev_b32_e32 v4, 30, v4
+; TONGA-NEXT: v_lshrrev_b32_e32 v5, 30, v5
+; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v0
+; TONGA-NEXT: v_add_u32_e32 v5, vcc, v5, v1
+; TONGA-NEXT: v_and_b32_e32 v4, -4, v4
+; TONGA-NEXT: v_and_b32_e32 v5, -4, v5
+; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v4, v0
+; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v5, v1
; TONGA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; TONGA-NEXT: s_endpgm
;
@@ -845,114 +815,106 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: global_load_dwordx4 v[1:4], v0, s[2:3] offset:16
-; GCN-NEXT: global_load_dwordx4 v[5:8], v0, s[2:3]
+; GCN-NEXT: global_load_dwordx4 v[3:6], v0, s[2:3]
+; GCN-NEXT: global_load_dwordx4 v[7:10], v0, s[2:3] offset:16
; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_readfirstlane_b32 s2, v1
-; GCN-NEXT: s_abs_i32 s2, s2
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT: s_sub_i32 s6, 0, s2
+; GCN-NEXT: v_sub_u32_e32 v11, 0, v3
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s4, v5
-; GCN-NEXT: s_ashr_i32 s5, s4, 31
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: s_abs_i32 s4, s4
-; GCN-NEXT: v_readfirstlane_b32 s3, v2
-; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s7, v1
-; GCN-NEXT: s_mul_i32 s6, s6, s7
-; GCN-NEXT: s_mul_hi_u32 s6, s7, s6
-; GCN-NEXT: s_add_i32 s7, s7, s6
-; GCN-NEXT: s_mul_hi_u32 s6, s4, s7
-; GCN-NEXT: s_mul_i32 s6, s6, s2
-; GCN-NEXT: s_sub_i32 s4, s4, s6
-; GCN-NEXT: s_sub_i32 s6, s4, s2
-; GCN-NEXT: s_cmp_ge_u32 s4, s2
-; GCN-NEXT: s_cselect_b32 s4, s6, s4
-; GCN-NEXT: s_sub_i32 s6, s4, s2
-; GCN-NEXT: s_cmp_ge_u32 s4, s2
-; GCN-NEXT: s_cselect_b32 s2, s6, s4
-; GCN-NEXT: s_abs_i32 s3, s3
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT: s_xor_b32 s2, s2, s5
-; GCN-NEXT: s_sub_i32 s8, 0, s3
-; GCN-NEXT: s_sub_i32 s2, s2, s5
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s6, v6
-; GCN-NEXT: s_ashr_i32 s7, s6, 31
-; GCN-NEXT: s_abs_i32 s6, s6
-; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s4, v3
-; GCN-NEXT: v_readfirstlane_b32 s5, v1
-; GCN-NEXT: s_mul_i32 s8, s8, s5
-; GCN-NEXT: s_mul_hi_u32 s8, s5, s8
-; GCN-NEXT: s_add_i32 s5, s5, s8
-; GCN-NEXT: s_mul_hi_u32 s5, s6, s5
-; GCN-NEXT: s_mul_i32 s5, s5, s3
-; GCN-NEXT: s_sub_i32 s5, s6, s5
-; GCN-NEXT: s_sub_i32 s6, s5, s3
-; GCN-NEXT: s_cmp_ge_u32 s5, s3
-; GCN-NEXT: s_cselect_b32 s5, s6, s5
-; GCN-NEXT: s_sub_i32 s6, s5, s3
-; GCN-NEXT: s_cmp_ge_u32 s5, s3
-; GCN-NEXT: s_cselect_b32 s3, s6, s5
-; GCN-NEXT: s_abs_i32 s4, s4
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s4
-; GCN-NEXT: s_xor_b32 s3, s3, s7
-; GCN-NEXT: s_sub_i32 s9, 0, s4
-; GCN-NEXT: s_sub_i32 s3, s3, s7
-; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s6, v7
-; GCN-NEXT: s_ashr_i32 s8, s6, 31
-; GCN-NEXT: s_abs_i32 s6, s6
-; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s5, v4
-; GCN-NEXT: v_readfirstlane_b32 s7, v1
-; GCN-NEXT: s_mul_i32 s9, s9, s7
-; GCN-NEXT: s_mul_hi_u32 s9, s7, s9
-; GCN-NEXT: s_add_i32 s7, s7, s9
-; GCN-NEXT: s_mul_hi_u32 s7, s6, s7
-; GCN-NEXT: s_mul_i32 s7, s7, s4
-; GCN-NEXT: s_sub_i32 s6, s6, s7
-; GCN-NEXT: s_sub_i32 s7, s6, s4
-; GCN-NEXT: s_cmp_ge_u32 s6, s4
-; GCN-NEXT: s_cselect_b32 s6, s7, s6
-; GCN-NEXT: s_sub_i32 s7, s6, s4
-; GCN-NEXT: s_cmp_ge_u32 s6, s4
-; GCN-NEXT: s_cselect_b32 s4, s7, s6
-; GCN-NEXT: s_abs_i32 s5, s5
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5
-; GCN-NEXT: v_readfirstlane_b32 s6, v8
-; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: s_ashr_i32 s2, s6, 31
-; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v2
-; GCN-NEXT: v_mov_b32_e32 v2, s3
-; GCN-NEXT: s_abs_i32 s3, s6
-; GCN-NEXT: s_sub_i32 s6, 0, s5
-; GCN-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: s_xor_b32 s4, s4, s8
-; GCN-NEXT: s_sub_i32 s4, s4, s8
-; GCN-NEXT: v_readfirstlane_b32 s7, v3
-; GCN-NEXT: s_mul_i32 s6, s6, s7
-; GCN-NEXT: s_mul_hi_u32 s6, s7, s6
-; GCN-NEXT: s_add_i32 s7, s7, s6
-; GCN-NEXT: s_mul_hi_u32 s6, s3, s7
-; GCN-NEXT: s_mul_i32 s6, s6, s5
-; GCN-NEXT: s_sub_i32 s3, s3, s6
-; GCN-NEXT: s_sub_i32 s6, s3, s5
-; GCN-NEXT: s_cmp_ge_u32 s3, s5
-; GCN-NEXT: s_cselect_b32 s3, s6, s3
-; GCN-NEXT: s_sub_i32 s6, s3, s5
-; GCN-NEXT: s_cmp_ge_u32 s3, s5
-; GCN-NEXT: s_cselect_b32 s3, s6, s3
-; GCN-NEXT: s_xor_b32 s3, s3, s2
-; GCN-NEXT: s_sub_i32 s2, s3, s2
-; GCN-NEXT: v_mov_b32_e32 v3, s4
-; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_sub_u32_e32 v12, 0, v7
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v3
+; GCN-NEXT: v_max_i32_e32 v3, v3, v11
+; GCN-NEXT: v_sub_u32_e32 v11, 0, v10
+; GCN-NEXT: v_max_i32_e32 v7, v7, v12
+; GCN-NEXT: v_max_i32_e32 v10, v10, v11
+; GCN-NEXT: v_cvt_f32_u32_e32 v11, v7
+; GCN-NEXT: v_sub_u32_e32 v14, 0, v8
+; GCN-NEXT: v_sub_u32_e32 v13, 0, v4
+; GCN-NEXT: v_sub_u32_e32 v17, 0, v9
+; GCN-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; GCN-NEXT: v_max_i32_e32 v8, v8, v14
+; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v4
+; GCN-NEXT: v_sub_u32_e32 v16, 0, v5
+; GCN-NEXT: v_sub_u32_e32 v19, 0, v6
+; GCN-NEXT: v_max_i32_e32 v4, v4, v13
+; GCN-NEXT: v_max_i32_e32 v9, v9, v17
+; GCN-NEXT: v_cvt_f32_u32_e32 v13, v8
+; GCN-NEXT: v_mul_f32_e32 v11, 0x4f7ffffe, v11
+; GCN-NEXT: v_ashrrev_i32_e32 v15, 31, v5
+; GCN-NEXT: v_ashrrev_i32_e32 v18, 31, v6
+; GCN-NEXT: v_max_i32_e32 v5, v5, v16
+; GCN-NEXT: v_max_i32_e32 v6, v6, v19
+; GCN-NEXT: v_cvt_f32_u32_e32 v16, v9
+; GCN-NEXT: v_cvt_f32_u32_e32 v19, v10
+; GCN-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GCN-NEXT: v_sub_u32_e32 v12, 0, v7
+; GCN-NEXT: v_rcp_iflag_f32_e32 v13, v13
+; GCN-NEXT: v_rcp_iflag_f32_e32 v16, v16
+; GCN-NEXT: v_rcp_iflag_f32_e32 v19, v19
+; GCN-NEXT: v_mul_lo_u32 v12, v12, v11
+; GCN-NEXT: v_mul_f32_e32 v13, 0x4f7ffffe, v13
+; GCN-NEXT: v_mul_f32_e32 v16, 0x4f7ffffe, v16
+; GCN-NEXT: v_mul_f32_e32 v19, 0x4f7ffffe, v19
+; GCN-NEXT: v_mul_hi_u32 v12, v11, v12
+; GCN-NEXT: v_cvt_u32_f32_e32 v13, v13
+; GCN-NEXT: v_cvt_u32_f32_e32 v16, v16
+; GCN-NEXT: v_cvt_u32_f32_e32 v19, v19
+; GCN-NEXT: v_sub_u32_e32 v14, 0, v8
+; GCN-NEXT: v_sub_u32_e32 v17, 0, v9
+; GCN-NEXT: v_add_u32_e32 v11, v11, v12
+; GCN-NEXT: v_sub_u32_e32 v12, 0, v10
+; GCN-NEXT: v_mul_lo_u32 v14, v14, v13
+; GCN-NEXT: v_mul_lo_u32 v17, v17, v16
+; GCN-NEXT: v_mul_lo_u32 v12, v12, v19
+; GCN-NEXT: v_mul_hi_u32 v11, v3, v11
+; GCN-NEXT: v_mul_hi_u32 v14, v13, v14
+; GCN-NEXT: v_mul_hi_u32 v17, v16, v17
+; GCN-NEXT: v_mul_hi_u32 v12, v19, v12
+; GCN-NEXT: v_mul_lo_u32 v11, v11, v7
+; GCN-NEXT: v_add_u32_e32 v13, v13, v14
+; GCN-NEXT: v_add_u32_e32 v14, v16, v17
+; GCN-NEXT: v_add_u32_e32 v12, v19, v12
+; GCN-NEXT: v_mul_hi_u32 v13, v4, v13
+; GCN-NEXT: v_mul_hi_u32 v14, v5, v14
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v12
+; GCN-NEXT: v_sub_u32_e32 v3, v3, v11
+; GCN-NEXT: v_mul_lo_u32 v13, v13, v8
+; GCN-NEXT: v_mul_lo_u32 v14, v14, v9
+; GCN-NEXT: v_mul_lo_u32 v12, v12, v10
+; GCN-NEXT: v_sub_u32_e32 v11, v3, v7
+; GCN-NEXT: v_sub_u32_e32 v4, v4, v13
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
+; GCN-NEXT: v_sub_u32_e32 v5, v5, v14
+; GCN-NEXT: v_sub_u32_e32 v6, v6, v12
+; GCN-NEXT: v_sub_u32_e32 v12, v4, v8
+; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v8
+; GCN-NEXT: v_sub_u32_e32 v13, v5, v9
+; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v9
+; GCN-NEXT: v_sub_u32_e32 v14, v6, v10
+; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v10
+; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GCN-NEXT: v_sub_u32_e32 v11, v3, v7
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
+; GCN-NEXT: v_sub_u32_e32 v12, v4, v8
+; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v8
+; GCN-NEXT: v_sub_u32_e32 v13, v5, v9
+; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v9
+; GCN-NEXT: v_sub_u32_e32 v14, v6, v10
+; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v10
+; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v1
+; GCN-NEXT: v_xor_b32_e32 v4, v4, v2
+; GCN-NEXT: v_xor_b32_e32 v5, v5, v15
+; GCN-NEXT: v_xor_b32_e32 v6, v6, v18
+; GCN-NEXT: v_sub_u32_e32 v1, v3, v1
+; GCN-NEXT: v_sub_u32_e32 v2, v4, v2
+; GCN-NEXT: v_sub_u32_e32 v3, v5, v15
+; GCN-NEXT: v_sub_u32_e32 v4, v6, v18
; GCN-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -966,116 +928,108 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: s_waitcnt lgkmcnt(0)
; TAHITI-NEXT: s_mov_b32 s8, s6
; TAHITI-NEXT: s_mov_b32 s9, s7
-; TAHITI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; TAHITI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0
-; TAHITI-NEXT: s_waitcnt vmcnt(1)
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: s_abs_i32 s0, s0
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v0, s0
-; TAHITI-NEXT: s_sub_i32 s1, 0, s0
-; TAHITI-NEXT: v_readfirstlane_b32 s7, v1
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_lo_u32 v8, s1, v0
-; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s1, v4
-; TAHITI-NEXT: s_abs_i32 s6, s1
-; TAHITI-NEXT: s_ashr_i32 s1, s1, 31
-; TAHITI-NEXT: v_mul_hi_u32 v8, v0, v8
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v0, v8
-; TAHITI-NEXT: v_mul_hi_u32 v0, s6, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s8, v0
-; TAHITI-NEXT: s_mul_i32 s8, s8, s0
-; TAHITI-NEXT: s_sub_i32 s6, s6, s8
-; TAHITI-NEXT: s_sub_i32 s8, s6, s0
-; TAHITI-NEXT: s_cmp_ge_u32 s6, s0
-; TAHITI-NEXT: s_cselect_b32 s6, s8, s6
-; TAHITI-NEXT: s_sub_i32 s8, s6, s0
-; TAHITI-NEXT: s_cmp_ge_u32 s6, s0
-; TAHITI-NEXT: s_cselect_b32 s0, s8, s6
-; TAHITI-NEXT: s_abs_i32 s6, s7
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v0, s6
-; TAHITI-NEXT: s_sub_i32 s7, 0, s6
-; TAHITI-NEXT: v_readfirstlane_b32 s8, v5
-; TAHITI-NEXT: s_abs_i32 s9, s8
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TAHITI-NEXT: s_xor_b32 s0, s0, s1
-; TAHITI-NEXT: s_sub_i32 s10, s0, s1
-; TAHITI-NEXT: s_ashr_i32 s8, s8, 31
-; TAHITI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_lo_u32 v1, s7, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s7, v2
-; TAHITI-NEXT: v_mul_hi_u32 v1, v0, v1
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; TAHITI-NEXT: v_mul_hi_u32 v0, s9, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: s_mul_i32 s0, s0, s6
-; TAHITI-NEXT: s_sub_i32 s0, s9, s0
-; TAHITI-NEXT: s_sub_i32 s1, s0, s6
-; TAHITI-NEXT: s_cmp_ge_u32 s0, s6
-; TAHITI-NEXT: s_cselect_b32 s0, s1, s0
-; TAHITI-NEXT: s_sub_i32 s1, s0, s6
-; TAHITI-NEXT: s_cmp_ge_u32 s0, s6
-; TAHITI-NEXT: s_cselect_b32 s0, s1, s0
-; TAHITI-NEXT: s_abs_i32 s1, s7
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v0, s1
-; TAHITI-NEXT: s_sub_i32 s6, 0, s1
-; TAHITI-NEXT: v_readfirstlane_b32 s7, v6
-; TAHITI-NEXT: s_abs_i32 s9, s7
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TAHITI-NEXT: s_xor_b32 s0, s0, s8
-; TAHITI-NEXT: s_sub_i32 s8, s0, s8
-; TAHITI-NEXT: s_ashr_i32 s7, s7, 31
-; TAHITI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_lo_u32 v1, s6, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s6, v3
-; TAHITI-NEXT: v_mul_hi_u32 v1, v0, v1
-; TAHITI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; TAHITI-NEXT: v_mul_hi_u32 v0, s9, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: s_mul_i32 s0, s0, s1
-; TAHITI-NEXT: s_sub_i32 s0, s9, s0
-; TAHITI-NEXT: s_sub_i32 s9, s0, s1
-; TAHITI-NEXT: s_cmp_ge_u32 s0, s1
-; TAHITI-NEXT: s_cselect_b32 s0, s9, s0
-; TAHITI-NEXT: s_sub_i32 s9, s0, s1
-; TAHITI-NEXT: s_cmp_ge_u32 s0, s1
-; TAHITI-NEXT: s_cselect_b32 s9, s9, s0
-; TAHITI-NEXT: s_abs_i32 s6, s6
-; TAHITI-NEXT: v_cvt_f32_u32_e32 v0, s6
-; TAHITI-NEXT: s_sub_i32 s1, 0, s6
+; TAHITI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; TAHITI-NEXT: buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:16
; TAHITI-NEXT: s_mov_b32 s0, s4
-; TAHITI-NEXT: v_readfirstlane_b32 s4, v7
-; TAHITI-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TAHITI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TAHITI-NEXT: v_cvt_u32_f32_e32 v2, v0
-; TAHITI-NEXT: v_mov_b32_e32 v0, s10
-; TAHITI-NEXT: v_mul_lo_u32 v1, s1, v2
; TAHITI-NEXT: s_mov_b32 s1, s5
-; TAHITI-NEXT: s_abs_i32 s5, s4
-; TAHITI-NEXT: s_ashr_i32 s4, s4, 31
-; TAHITI-NEXT: v_mul_hi_u32 v3, v2, v1
-; TAHITI-NEXT: v_mov_b32_e32 v1, s8
-; TAHITI-NEXT: s_xor_b32 s8, s9, s7
-; TAHITI-NEXT: s_sub_i32 s7, s8, s7
-; TAHITI-NEXT: v_add_i32_e32 v2, vcc, v2, v3
-; TAHITI-NEXT: v_mul_hi_u32 v2, s5, v2
-; TAHITI-NEXT: v_readfirstlane_b32 s8, v2
-; TAHITI-NEXT: s_mul_i32 s8, s8, s6
-; TAHITI-NEXT: s_sub_i32 s5, s5, s8
-; TAHITI-NEXT: s_sub_i32 s8, s5, s6
-; TAHITI-NEXT: s_cmp_ge_u32 s5, s6
-; TAHITI-NEXT: s_cselect_b32 s5, s8, s5
-; TAHITI-NEXT: s_sub_i32 s8, s5, s6
-; TAHITI-NEXT: s_cmp_ge_u32 s5, s6
-; TAHITI-NEXT: s_cselect_b32 s5, s8, s5
-; TAHITI-NEXT: s_xor_b32 s5, s5, s4
-; TAHITI-NEXT: s_sub_i32 s4, s5, s4
-; TAHITI-NEXT: v_mov_b32_e32 v2, s7
-; TAHITI-NEXT: v_mov_b32_e32 v3, s4
+; TAHITI-NEXT: s_waitcnt vmcnt(1)
+; TAHITI-NEXT: v_sub_i32_e32 v9, vcc, 0, v0
+; TAHITI-NEXT: s_waitcnt vmcnt(0)
+; TAHITI-NEXT: v_sub_i32_e32 v10, vcc, 0, v5
+; TAHITI-NEXT: v_max_i32_e32 v5, v5, v10
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v10, v5
+; TAHITI-NEXT: v_sub_i32_e32 v13, vcc, 0, v6
+; TAHITI-NEXT: v_sub_i32_e32 v16, vcc, 0, v7
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v10, v10
+; TAHITI-NEXT: v_max_i32_e32 v6, v6, v13
+; TAHITI-NEXT: v_max_i32_e32 v7, v7, v16
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v16, v6
+; TAHITI-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v18, v7
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v10, v10
+; TAHITI-NEXT: v_sub_i32_e32 v13, vcc, 0, v5
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v16, v16
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v18, v18
+; TAHITI-NEXT: v_mul_lo_u32 v13, v13, v10
+; TAHITI-NEXT: v_sub_i32_e32 v17, vcc, 0, v8
+; TAHITI-NEXT: v_mul_f32_e32 v16, 0x4f7ffffe, v16
+; TAHITI-NEXT: v_mul_f32_e32 v18, 0x4f7ffffe, v18
+; TAHITI-NEXT: v_mul_hi_u32 v13, v10, v13
+; TAHITI-NEXT: v_max_i32_e32 v8, v8, v17
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v16, v16
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v18, v18
+; TAHITI-NEXT: v_cvt_f32_u32_e32 v19, v8
+; TAHITI-NEXT: v_sub_i32_e32 v17, vcc, 0, v6
+; TAHITI-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; TAHITI-NEXT: v_sub_i32_e32 v13, vcc, 0, v7
+; TAHITI-NEXT: v_mul_lo_u32 v17, v17, v16
+; TAHITI-NEXT: v_mul_lo_u32 v13, v13, v18
+; TAHITI-NEXT: v_rcp_iflag_f32_e32 v19, v19
+; TAHITI-NEXT: v_sub_i32_e32 v12, vcc, 0, v1
+; TAHITI-NEXT: v_mul_hi_u32 v17, v16, v17
+; TAHITI-NEXT: v_mul_hi_u32 v13, v18, v13
+; TAHITI-NEXT: v_mul_f32_e32 v19, 0x4f7ffffe, v19
+; TAHITI-NEXT: v_cvt_u32_f32_e32 v19, v19
+; TAHITI-NEXT: v_sub_i32_e32 v15, vcc, 0, v2
+; TAHITI-NEXT: v_ashrrev_i32_e32 v4, 31, v0
+; TAHITI-NEXT: v_ashrrev_i32_e32 v11, 31, v1
+; TAHITI-NEXT: v_ashrrev_i32_e32 v14, 31, v2
+; TAHITI-NEXT: v_add_i32_e32 v16, vcc, v16, v17
+; TAHITI-NEXT: v_add_i32_e32 v13, vcc, v18, v13
+; TAHITI-NEXT: v_max_i32_e32 v0, v0, v9
+; TAHITI-NEXT: v_max_i32_e32 v1, v1, v12
+; TAHITI-NEXT: v_max_i32_e32 v2, v2, v15
+; TAHITI-NEXT: v_sub_i32_e32 v17, vcc, 0, v8
+; TAHITI-NEXT: v_mul_hi_u32 v10, v0, v10
+; TAHITI-NEXT: v_mul_hi_u32 v15, v1, v16
+; TAHITI-NEXT: v_mul_hi_u32 v13, v2, v13
+; TAHITI-NEXT: v_mul_lo_u32 v17, v17, v19
+; TAHITI-NEXT: v_mul_lo_u32 v10, v10, v5
+; TAHITI-NEXT: v_mul_lo_u32 v15, v15, v6
+; TAHITI-NEXT: v_mul_lo_u32 v13, v13, v7
+; TAHITI-NEXT: v_mul_hi_u32 v9, v19, v17
+; TAHITI-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
+; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v1, v15
+; TAHITI-NEXT: v_sub_i32_e32 v2, vcc, v2, v13
+; TAHITI-NEXT: v_sub_i32_e32 v18, vcc, 0, v3
+; TAHITI-NEXT: v_add_i32_e32 v9, vcc, v19, v9
+; TAHITI-NEXT: v_sub_i32_e32 v10, vcc, v0, v5
+; TAHITI-NEXT: v_sub_i32_e32 v13, vcc, v1, v6
+; TAHITI-NEXT: v_sub_i32_e32 v15, vcc, v2, v7
+; TAHITI-NEXT: v_max_i32_e32 v12, v3, v18
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
+; TAHITI-NEXT: v_mul_hi_u32 v9, v12, v9
+; TAHITI-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v6
+; TAHITI-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v7
+; TAHITI-NEXT: v_cndmask_b32_e32 v2, v2, v15, vcc
+; TAHITI-NEXT: v_sub_i32_e32 v10, vcc, v0, v5
+; TAHITI-NEXT: v_sub_i32_e32 v13, vcc, v1, v6
+; TAHITI-NEXT: v_sub_i32_e32 v15, vcc, v2, v7
+; TAHITI-NEXT: v_mul_lo_u32 v9, v9, v8
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
+; TAHITI-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v6
+; TAHITI-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v7
+; TAHITI-NEXT: v_cndmask_b32_e32 v2, v2, v15, vcc
+; TAHITI-NEXT: v_xor_b32_e32 v0, v0, v4
+; TAHITI-NEXT: v_xor_b32_e32 v1, v1, v11
+; TAHITI-NEXT: v_xor_b32_e32 v2, v2, v14
+; TAHITI-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
+; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, v12, v9
+; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v1, v11
+; TAHITI-NEXT: v_sub_i32_e32 v2, vcc, v2, v14
+; TAHITI-NEXT: v_sub_i32_e32 v5, vcc, v4, v8
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v8
+; TAHITI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; TAHITI-NEXT: v_sub_i32_e32 v5, vcc, v4, v8
+; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v4, v8
+; TAHITI-NEXT: v_ashrrev_i32_e32 v3, 31, v3
+; TAHITI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; TAHITI-NEXT: v_xor_b32_e32 v4, v4, v3
+; TAHITI-NEXT: v_sub_i32_e32 v3, vcc, v4, v3
; TAHITI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; TAHITI-NEXT: s_endpgm
;
@@ -1083,122 +1037,114 @@ define amdgpu_kernel void @srem_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA: ; %bb.0:
; TONGA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; TONGA-NEXT: s_waitcnt lgkmcnt(0)
-; TONGA-NEXT: s_add_u32 s4, s2, 16
-; TONGA-NEXT: s_addc_u32 s5, s3, 0
-; TONGA-NEXT: v_mov_b32_e32 v0, s4
-; TONGA-NEXT: v_mov_b32_e32 v1, s5
-; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
-; TONGA-NEXT: v_mov_b32_e32 v5, s3
-; TONGA-NEXT: v_mov_b32_e32 v4, s2
-; TONGA-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
+; TONGA-NEXT: v_mov_b32_e32 v0, s2
+; TONGA-NEXT: v_mov_b32_e32 v1, s3
+; TONGA-NEXT: s_add_u32 s2, s2, 16
+; TONGA-NEXT: flat_load_dwordx4 v[2:5], v[0:1]
+; TONGA-NEXT: s_addc_u32 s3, s3, 0
+; TONGA-NEXT: v_mov_b32_e32 v0, s2
+; TONGA-NEXT: v_mov_b32_e32 v1, s3
+; TONGA-NEXT: flat_load_dwordx4 v[6:9], v[0:1]
; TONGA-NEXT: s_waitcnt vmcnt(1)
-; TONGA-NEXT: v_readfirstlane_b32 s2, v0
-; TONGA-NEXT: s_abs_i32 s2, s2
-; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s2
-; TONGA-NEXT: s_sub_i32 s3, 0, s2
-; TONGA-NEXT: v_readfirstlane_b32 s5, v1
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TONGA-NEXT: v_mul_lo_u32 v8, s3, v0
+; TONGA-NEXT: v_sub_u32_e32 v12, vcc, 0, v3
+; TONGA-NEXT: v_ashrrev_i32_e32 v1, 31, v3
+; TONGA-NEXT: v_max_i32_e32 v3, v3, v12
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s3, v4
-; TONGA-NEXT: s_abs_i32 s4, s3
-; TONGA-NEXT: s_ashr_i32 s3, s3, 31
-; TONGA-NEXT: v_mul_hi_u32 v8, v0, v8
+; TONGA-NEXT: v_sub_u32_e32 v13, vcc, 0, v7
+; TONGA-NEXT: v_max_i32_e32 v7, v7, v13
+; TONGA-NEXT: v_cvt_f32_u32_e32 v12, v7
+; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v6
+; TONGA-NEXT: v_sub_u32_e32 v16, vcc, 0, v8
+; TONGA-NEXT: v_sub_u32_e32 v10, vcc, 0, v2
+; TONGA-NEXT: v_sub_u32_e32 v15, vcc, 0, v4
+; TONGA-NEXT: v_sub_u32_e32 v19, vcc, 0, v9
+; TONGA-NEXT: v_max_i32_e32 v6, v6, v11
+; TONGA-NEXT: v_max_i32_e32 v8, v8, v16
+; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v2
+; TONGA-NEXT: v_ashrrev_i32_e32 v14, 31, v4
+; TONGA-NEXT: v_sub_u32_e32 v18, vcc, 0, v5
+; TONGA-NEXT: v_max_i32_e32 v2, v2, v10
+; TONGA-NEXT: v_max_i32_e32 v10, v4, v15
+; TONGA-NEXT: v_max_i32_e32 v9, v9, v19
+; TONGA-NEXT: v_cvt_f32_u32_e32 v4, v6
+; TONGA-NEXT: v_cvt_f32_u32_e32 v15, v8
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; TONGA-NEXT: v_max_i32_e32 v11, v5, v18
+; TONGA-NEXT: v_cvt_f32_u32_e32 v18, v9
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v4, v4
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v15, v15
+; TONGA-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; TONGA-NEXT: v_rcp_iflag_f32_e32 v18, v18
+; TONGA-NEXT: v_cvt_u32_f32_e32 v12, v12
+; TONGA-NEXT: v_sub_u32_e32 v13, vcc, 0, v7
+; TONGA-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
+; TONGA-NEXT: v_mul_f32_e32 v15, 0x4f7ffffe, v15
+; TONGA-NEXT: v_cvt_u32_f32_e32 v4, v4
+; TONGA-NEXT: v_mul_f32_e32 v18, 0x4f7ffffe, v18
+; TONGA-NEXT: v_cvt_u32_f32_e32 v15, v15
+; TONGA-NEXT: v_mul_lo_u32 v13, v13, v12
+; TONGA-NEXT: v_cvt_u32_f32_e32 v18, v18
+; TONGA-NEXT: v_ashrrev_i32_e32 v17, 31, v5
+; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v6
+; TONGA-NEXT: v_sub_u32_e32 v16, vcc, 0, v8
+; TONGA-NEXT: v_sub_u32_e32 v19, vcc, 0, v9
+; TONGA-NEXT: v_mul_lo_u32 v5, v5, v4
+; TONGA-NEXT: v_mul_lo_u32 v16, v16, v15
+; TONGA-NEXT: v_mul_hi_u32 v13, v12, v13
+; TONGA-NEXT: v_mul_lo_u32 v19, v19, v18
+; TONGA-NEXT: v_mul_hi_u32 v5, v4, v5
+; TONGA-NEXT: v_add_u32_e32 v12, vcc, v12, v13
+; TONGA-NEXT: v_mul_hi_u32 v13, v15, v16
+; TONGA-NEXT: v_mul_hi_u32 v16, v18, v19
+; TONGA-NEXT: v_add_u32_e32 v20, vcc, v4, v5
+; TONGA-NEXT: v_add_u32_e32 v13, vcc, v15, v13
+; TONGA-NEXT: v_add_u32_e32 v15, vcc, v18, v16
+; TONGA-NEXT: v_mul_hi_u32 v16, v2, v20
+; TONGA-NEXT: v_mul_hi_u32 v12, v3, v12
+; TONGA-NEXT: v_mul_hi_u32 v13, v10, v13
+; TONGA-NEXT: v_mul_hi_u32 v15, v11, v15
+; TONGA-NEXT: v_mul_lo_u32 v16, v16, v6
+; TONGA-NEXT: v_mul_lo_u32 v12, v12, v7
+; TONGA-NEXT: v_mul_lo_u32 v13, v13, v8
+; TONGA-NEXT: v_mul_lo_u32 v15, v15, v9
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v16
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v12
+; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v10, v13
+; TONGA-NEXT: v_sub_u32_e32 v11, vcc, v11, v15
+; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v2, v6
+; TONGA-NEXT: v_sub_u32_e32 v13, vcc, v3, v7
+; TONGA-NEXT: v_sub_u32_e32 v15, vcc, v10, v8
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
+; TONGA-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v10, v8
+; TONGA-NEXT: v_cndmask_b32_e32 v10, v10, v15, vcc
+; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v2, v6
+; TONGA-NEXT: v_sub_u32_e32 v13, vcc, v3, v7
+; TONGA-NEXT: v_sub_u32_e32 v15, vcc, v10, v8
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6
+; TONGA-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v10, v8
+; TONGA-NEXT: v_cndmask_b32_e32 v6, v10, v15, vcc
+; TONGA-NEXT: v_xor_b32_e32 v2, v2, v0
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v1
+; TONGA-NEXT: v_xor_b32_e32 v6, v6, v14
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v2, v0
+; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v3, v1
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v6, v14
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v11, v9
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v11, v9
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; TONGA-NEXT: v_sub_u32_e32 v6, vcc, v3, v9
+; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v9
+; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
+; TONGA-NEXT: v_xor_b32_e32 v3, v3, v17
; TONGA-NEXT: v_mov_b32_e32 v4, s0
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v8
-; TONGA-NEXT: v_mul_hi_u32 v0, s4, v0
-; TONGA-NEXT: v_readfirstlane_b32 s6, v0
-; TONGA-NEXT: s_mul_i32 s6, s6, s2
-; TONGA-NEXT: s_sub_i32 s4, s4, s6
-; TONGA-NEXT: s_sub_i32 s6, s4, s2
-; TONGA-NEXT: s_cmp_ge_u32 s4, s2
-; TONGA-NEXT: s_cselect_b32 s4, s6, s4
-; TONGA-NEXT: s_sub_i32 s6, s4, s2
-; TONGA-NEXT: s_cmp_ge_u32 s4, s2
-; TONGA-NEXT: s_cselect_b32 s2, s6, s4
-; TONGA-NEXT: s_abs_i32 s4, s5
-; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s4
-; TONGA-NEXT: s_sub_i32 s5, 0, s4
-; TONGA-NEXT: v_readfirstlane_b32 s6, v5
-; TONGA-NEXT: s_abs_i32 s7, s6
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT: s_xor_b32 s2, s2, s3
-; TONGA-NEXT: s_sub_i32 s2, s2, s3
-; TONGA-NEXT: s_ashr_i32 s6, s6, 31
-; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0
; TONGA-NEXT: v_mov_b32_e32 v5, s1
-; TONGA-NEXT: v_mul_lo_u32 v1, s5, v0
-; TONGA-NEXT: v_readfirstlane_b32 s5, v2
-; TONGA-NEXT: v_mul_hi_u32 v1, v0, v1
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; TONGA-NEXT: v_mul_hi_u32 v0, s7, v0
-; TONGA-NEXT: v_readfirstlane_b32 s3, v0
-; TONGA-NEXT: s_mul_i32 s3, s3, s4
-; TONGA-NEXT: s_sub_i32 s3, s7, s3
-; TONGA-NEXT: s_sub_i32 s7, s3, s4
-; TONGA-NEXT: s_cmp_ge_u32 s3, s4
-; TONGA-NEXT: s_cselect_b32 s3, s7, s3
-; TONGA-NEXT: s_sub_i32 s7, s3, s4
-; TONGA-NEXT: s_cmp_ge_u32 s3, s4
-; TONGA-NEXT: s_cselect_b32 s3, s7, s3
-; TONGA-NEXT: s_abs_i32 s4, s5
-; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s4
-; TONGA-NEXT: s_sub_i32 s5, 0, s4
-; TONGA-NEXT: v_readfirstlane_b32 s7, v6
-; TONGA-NEXT: s_abs_i32 s8, s7
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT: s_xor_b32 s3, s3, s6
-; TONGA-NEXT: s_sub_i32 s3, s3, s6
-; TONGA-NEXT: s_ashr_i32 s7, s7, 31
-; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0
-; TONGA-NEXT: v_mul_lo_u32 v1, s5, v0
-; TONGA-NEXT: v_readfirstlane_b32 s5, v3
-; TONGA-NEXT: v_mul_hi_u32 v1, v0, v1
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; TONGA-NEXT: v_mul_hi_u32 v0, s8, v0
-; TONGA-NEXT: v_readfirstlane_b32 s6, v0
-; TONGA-NEXT: s_mul_i32 s6, s6, s4
-; TONGA-NEXT: s_sub_i32 s6, s8, s6
-; TONGA-NEXT: s_sub_i32 s8, s6, s4
-; TONGA-NEXT: s_cmp_ge_u32 s6, s4
-; TONGA-NEXT: s_cselect_b32 s6, s8, s6
-; TONGA-NEXT: s_sub_i32 s8, s6, s4
-; TONGA-NEXT: s_cmp_ge_u32 s6, s4
-; TONGA-NEXT: s_cselect_b32 s4, s8, s6
-; TONGA-NEXT: s_abs_i32 s5, s5
-; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s5
-; TONGA-NEXT: s_sub_i32 s0, 0, s5
-; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; TONGA-NEXT: v_cvt_u32_f32_e32 v2, v0
-; TONGA-NEXT: v_mov_b32_e32 v0, s2
-; TONGA-NEXT: s_xor_b32 s2, s4, s7
-; TONGA-NEXT: s_sub_i32 s2, s2, s7
-; TONGA-NEXT: v_mul_lo_u32 v1, s0, v2
-; TONGA-NEXT: v_readfirstlane_b32 s0, v7
-; TONGA-NEXT: s_abs_i32 s1, s0
-; TONGA-NEXT: s_ashr_i32 s0, s0, 31
-; TONGA-NEXT: v_mul_hi_u32 v3, v2, v1
-; TONGA-NEXT: v_mov_b32_e32 v1, s3
-; TONGA-NEXT: v_add_u32_e32 v2, vcc, v2, v3
-; TONGA-NEXT: v_mul_hi_u32 v2, s1, v2
-; TONGA-NEXT: v_readfirstlane_b32 s3, v2
-; TONGA-NEXT: s_mul_i32 s3, s3, s5
-; TONGA-NEXT: s_sub_i32 s1, s1, s3
-; TONGA-NEXT: s_sub_i32 s3, s1, s5
-; TONGA-NEXT: s_cmp_ge_u32 s1, s5
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_sub_i32 s3, s1, s5
-; TONGA-NEXT: s_cmp_ge_u32 s1, s5
-; TONGA-NEXT: s_cselect_b32 s1, s3, s1
-; TONGA-NEXT: s_xor_b32 s1, s1, s0
-; TONGA-NEXT: s_sub_i32 s0, s1, s0
-; TONGA-NEXT: v_mov_b32_e32 v2, s2
-; TONGA-NEXT: v_mov_b32_e32 v3, s0
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v17
; TONGA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; TONGA-NEXT: s_endpgm
;
@@ -1322,34 +1268,26 @@ define amdgpu_kernel void @srem_v4i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: v_readfirstlane_b32 s3, v1
-; GCN-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-NEXT: v_readfirstlane_b32 s5, v3
-; GCN-NEXT: s_ashr_i32 s6, s2, 31
-; GCN-NEXT: s_ashr_i32 s7, s3, 31
-; GCN-NEXT: s_ashr_i32 s8, s4, 31
-; GCN-NEXT: s_ashr_i32 s9, s5, 31
-; GCN-NEXT: s_lshr_b32 s6, s6, 30
-; GCN-NEXT: s_lshr_b32 s7, s7, 30
-; GCN-NEXT: s_lshr_b32 s8, s8, 30
-; GCN-NEXT: s_lshr_b32 s9, s9, 30
-; GCN-NEXT: s_add_i32 s6, s2, s6
-; GCN-NEXT: s_add_i32 s7, s3, s7
-; GCN-NEXT: s_add_i32 s8, s4, s8
-; GCN-NEXT: s_add_i32 s9, s5, s9
-; GCN-NEXT: s_and_b32 s6, s6, -4
-; GCN-NEXT: s_and_b32 s7, s7, -4
-; GCN-NEXT: s_and_b32 s8, s8, -4
-; GCN-NEXT: s_and_b32 s9, s9, -4
-; GCN-NEXT: s_sub_i32 s2, s2, s6
-; GCN-NEXT: s_sub_i32 s3, s3, s7
-; GCN-NEXT: s_sub_i32 s4, s4, s8
-; GCN-NEXT: s_sub_i32 s5, s5, s9
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: v_mov_b32_e32 v1, s3
-; GCN-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1
+; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v2
+; GCN-NEXT: v_ashrrev_i32_e32 v8, 31, v3
+; GCN-NEXT: v_lshrrev_b32_e32 v5, 30, v5
+; GCN-NEXT: v_lshrrev_b32_e32 v6, 30, v6
+; GCN-NEXT: v_lshrrev_b32_e32 v7, 30, v7
+; GCN-NEXT: v_lshrrev_b32_e32 v8, 30, v8
+; GCN-NEXT: v_add_u32_e32 v5, v0, v5
+; GCN-NEXT: v_add_u32_e32 v6, v1, v6
+; GCN-NEXT: v_add_u32_e32 v7, v2, v7
+; GCN-NEXT: v_add_u32_e32 v8, v3, v8
+; GCN-NEXT: v_and_b32_e32 v5, -4, v5
+; GCN-NEXT: v_and_b32_e32 v6, -4, v6
+; GCN-NEXT: v_and_b32_e32 v7, -4, v7
+; GCN-NEXT: v_and_b32_e32 v8, -4, v8
+; GCN-NEXT: v_sub_u32_e32 v0, v0, v5
+; GCN-NEXT: v_sub_u32_e32 v1, v1, v6
+; GCN-NEXT: v_sub_u32_e32 v2, v2, v7
+; GCN-NEXT: v_sub_u32_e32 v3, v3, v8
; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GCN-NEXT: s_endpgm
;
@@ -1367,34 +1305,26 @@ define amdgpu_kernel void @srem_v4i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; TAHITI-NEXT: s_mov_b32 s0, s4
; TAHITI-NEXT: s_mov_b32 s1, s5
; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s4, v0
-; TAHITI-NEXT: v_readfirstlane_b32 s5, v1
-; TAHITI-NEXT: v_readfirstlane_b32 s6, v2
-; TAHITI-NEXT: v_readfirstlane_b32 s7, v3
-; TAHITI-NEXT: s_ashr_i32 s8, s4, 31
-; TAHITI-NEXT: s_ashr_i32 s9, s5, 31
-; TAHITI-NEXT: s_ashr_i32 s10, s6, 31
-; TAHITI-NEXT: s_ashr_i32 s11, s7, 31
-; TAHITI-NEXT: s_lshr_b32 s8, s8, 30
-; TAHITI-NEXT: s_lshr_b32 s9, s9, 30
-; TAHITI-NEXT: s_lshr_b32 s10, s10, 30
-; TAHITI-NEXT: s_lshr_b32 s11, s11, 30
-; TAHITI-NEXT: s_add_i32 s8, s4, s8
-; TAHITI-NEXT: s_add_i32 s9, s5, s9
-; TAHITI-NEXT: s_add_i32 s10, s6, s10
-; TAHITI-NEXT: s_add_i32 s11, s7, s11
-; TAHITI-NEXT: s_and_b32 s8, s8, -4
-; TAHITI-NEXT: s_and_b32 s9, s9, -4
-; TAHITI-NEXT: s_and_b32 s10, s10, -4
-; TAHITI-NEXT: s_and_b32 s11, s11, -4
-; TAHITI-NEXT: s_sub_i32 s4, s4, s8
-; TAHITI-NEXT: s_sub_i32 s5, s5, s9
-; TAHITI-NEXT: s_sub_i32 s6, s6, s10
-; TAHITI-NEXT: s_sub_i32 s7, s7, s11
-; TAHITI-NEXT: v_mov_b32_e32 v0, s4
-; TAHITI-NEXT: v_mov_b32_e32 v1, s5
-; TAHITI-NEXT: v_mov_b32_e32 v2, s6
-; TAHITI-NEXT: v_mov_b32_e32 v3, s7
+; TAHITI-NEXT: v_ashrrev_i32_e32 v4, 31, v0
+; TAHITI-NEXT: v_ashrrev_i32_e32 v5, 31, v1
+; TAHITI-NEXT: v_ashrrev_i32_e32 v6, 31, v2
+; TAHITI-NEXT: v_ashrrev_i32_e32 v7, 31, v3
+; TAHITI-NEXT: v_lshrrev_b32_e32 v4, 30, v4
+; TAHITI-NEXT: v_lshrrev_b32_e32 v5, 30, v5
+; TAHITI-NEXT: v_lshrrev_b32_e32 v6, 30, v6
+; TAHITI-NEXT: v_lshrrev_b32_e32 v7, 30, v7
+; TAHITI-NEXT: v_add_i32_e32 v4, vcc, v4, v0
+; TAHITI-NEXT: v_add_i32_e32 v5, vcc, v5, v1
+; TAHITI-NEXT: v_add_i32_e32 v6, vcc, v6, v2
+; TAHITI-NEXT: v_add_i32_e32 v7, vcc, v7, v3
+; TAHITI-NEXT: v_and_b32_e32 v4, -4, v4
+; TAHITI-NEXT: v_and_b32_e32 v5, -4, v5
+; TAHITI-NEXT: v_and_b32_e32 v6, -4, v6
+; TAHITI-NEXT: v_and_b32_e32 v7, -4, v7
+; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, v4, v0
+; TAHITI-NEXT: v_subrev_i32_e32 v1, vcc, v5, v1
+; TAHITI-NEXT: v_subrev_i32_e32 v2, vcc, v6, v2
+; TAHITI-NEXT: v_subrev_i32_e32 v3, vcc, v7, v3
; TAHITI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; TAHITI-NEXT: s_endpgm
;
@@ -1408,34 +1338,26 @@ define amdgpu_kernel void @srem_v4i32_4(ptr addrspace(1) %out, ptr addrspace(1)
; TONGA-NEXT: v_mov_b32_e32 v4, s0
; TONGA-NEXT: v_mov_b32_e32 v5, s1
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_readfirstlane_b32 s0, v0
-; TONGA-NEXT: v_readfirstlane_b32 s1, v1
-; TONGA-NEXT: v_readfirstlane_b32 s2, v2
-; TONGA-NEXT: v_readfirstlane_b32 s3, v3
-; TONGA-NEXT: s_ashr_i32 s4, s0, 31
-; TONGA-NEXT: s_ashr_i32 s5, s1, 31
-; TONGA-NEXT: s_ashr_i32 s6, s2, 31
-; TONGA-NEXT: s_ashr_i32 s7, s3, 31
-; TONGA-NEXT: s_lshr_b32 s4, s4, 30
-; TONGA-NEXT: s_lshr_b32 s5, s5, 30
-; TONGA-NEXT: s_lshr_b32 s6, s6, 30
-; TONGA-NEXT: s_lshr_b32 s7, s7, 30
-; TONGA-NEXT: s_add_i32 s4, s0, s4
-; TONGA-NEXT: s_add_i32 s5, s1, s5
-; TONGA-NEXT: s_add_i32 s6, s2, s6
-; TONGA-NEXT: s_add_i32 s7, s3, s7
-; TONGA-NEXT: s_and_b32 s4, s4, -4
-; TONGA-NEXT: s_and_b32 s5, s5, -4
-; TONGA-NEXT: s_and_b32 s6, s6, -4
-; TONGA-NEXT: s_and_b32 s7, s7, -4
-; TONGA-NEXT: s_sub_i32 s0, s0, s4
-; TONGA-NEXT: s_sub_i32 s1, s1, s5
-; TONGA-NEXT: s_sub_i32 s2, s2, s6
-; TONGA-NEXT: s_sub_i32 s3, s3, s7
-; TONGA-NEXT: v_mov_b32_e32 v0, s0
-; TONGA-NEXT: v_mov_b32_e32 v1, s1
-; TONGA-NEXT: v_mov_b32_e32 v2, s2
-; TONGA-NEXT: v_mov_b32_e32 v3, s3
+; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v0
+; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v1
+; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v2
+; TONGA-NEXT: v_ashrrev_i32_e32 v9, 31, v3
+; TONGA-NEXT: v_lshrrev_b32_e32 v6, 30, v6
+; TONGA-NEXT: v_lshrrev_b32_e32 v7, 30, v7
+; TONGA-NEXT: v_lshrrev_b32_e32 v8, 30, v8
+; TONGA-NEXT: v_lshrrev_b32_e32 v9, 30, v9
+; TONGA-NEXT: v_add_u32_e32 v6, vcc, v6, v0
+; TONGA-NEXT: v_add_u32_e32 v7, vcc, v7, v1
+; TONGA-NEXT: v_add_u32_e32 v8, vcc, v8, v2
+; TONGA-NEXT: v_add_u32_e32 v9, vcc, v9, v3
+; TONGA-NEXT: v_and_b32_e32 v6, -4, v6
+; TONGA-NEXT: v_and_b32_e32 v7, -4, v7
+; TONGA-NEXT: v_and_b32_e32 v8, -4, v8
+; TONGA-NEXT: v_and_b32_e32 v9, -4, v9
+; TONGA-NEXT: v_subrev_u32_e32 v0, vcc, v6, v0
+; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v7, v1
+; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, v8, v2
+; TONGA-NEXT: v_subrev_u32_e32 v3, vcc, v9, v3
; TONGA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; TONGA-NEXT: s_endpgm
;
@@ -1492,185 +1414,157 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GCN-LABEL: srem_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[10:11]
+; GCN-NEXT: global_load_dwordx4 v[0:3], v4, s[10:11]
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s7, v1
-; GCN-NEXT: v_readfirstlane_b32 s6, v0
-; GCN-NEXT: v_readfirstlane_b32 s5, v3
-; GCN-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5]
-; GCN-NEXT: s_mov_b32 s0, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_cbranch_scc0 .LBB8_4
+; GCN-NEXT: v_or_b32_e32 v5, v1, v3
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GCN-NEXT: s_cbranch_vccz .LBB8_4
; GCN-NEXT: ; %bb.1:
-; GCN-NEXT: s_ashr_i32 s0, s5, 31
-; GCN-NEXT: s_add_u32 s2, s4, s0
-; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: s_addc_u32 s3, s5, s0
-; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT: s_sub_u32 s0, 0, s12
-; GCN-NEXT: s_subb_u32 s1, 0, s13
-; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v1
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_mul_i32 s5, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s15, s0, s3
-; GCN-NEXT: s_mul_i32 s14, s1, s3
-; GCN-NEXT: s_add_i32 s5, s15, s5
-; GCN-NEXT: s_add_i32 s5, s5, s14
-; GCN-NEXT: s_mul_i32 s16, s0, s3
-; GCN-NEXT: s_mul_hi_u32 s14, s3, s5
-; GCN-NEXT: s_mul_i32 s15, s3, s5
-; GCN-NEXT: s_mul_hi_u32 s3, s3, s16
-; GCN-NEXT: s_add_u32 s3, s3, s15
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: s_mul_hi_u32 s17, s2, s16
-; GCN-NEXT: s_mul_i32 s16, s2, s16
-; GCN-NEXT: s_add_u32 s3, s3, s16
-; GCN-NEXT: s_mul_hi_u32 s15, s2, s5
-; GCN-NEXT: s_addc_u32 s3, s14, s17
-; GCN-NEXT: s_addc_u32 s14, s15, 0
-; GCN-NEXT: s_mul_i32 s5, s2, s5
-; GCN-NEXT: s_add_u32 s3, s3, s5
-; GCN-NEXT: s_addc_u32 s5, 0, s14
-; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s5
-; GCN-NEXT: v_readfirstlane_b32 s5, v0
-; GCN-NEXT: s_mul_i32 s3, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s14, s0, s5
-; GCN-NEXT: s_add_i32 s3, s14, s3
-; GCN-NEXT: s_mul_i32 s1, s1, s5
-; GCN-NEXT: s_add_i32 s3, s3, s1
-; GCN-NEXT: s_mul_i32 s0, s0, s5
-; GCN-NEXT: s_mul_hi_u32 s14, s2, s0
-; GCN-NEXT: s_mul_i32 s15, s2, s0
-; GCN-NEXT: s_mul_i32 s17, s5, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s5, s0
-; GCN-NEXT: s_mul_hi_u32 s16, s5, s3
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: s_addc_u32 s5, 0, s16
-; GCN-NEXT: s_add_u32 s0, s0, s15
-; GCN-NEXT: s_mul_hi_u32 s1, s2, s3
-; GCN-NEXT: s_addc_u32 s0, s5, s14
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mul_i32 s3, s2, s3
-; GCN-NEXT: s_add_u32 s0, s0, s3
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s1
-; GCN-NEXT: s_ashr_i32 s14, s7, 31
-; GCN-NEXT: s_add_u32 s0, s6, s14
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_addc_u32 s1, s7, s14
-; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15]
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_mul_i32 s1, s16, s2
-; GCN-NEXT: s_mul_hi_u32 s5, s16, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s16, s2
-; GCN-NEXT: s_add_u32 s1, s5, s1
-; GCN-NEXT: s_addc_u32 s0, 0, s0
-; GCN-NEXT: s_mul_hi_u32 s7, s17, s3
-; GCN-NEXT: s_mul_i32 s3, s17, s3
-; GCN-NEXT: s_add_u32 s1, s1, s3
-; GCN-NEXT: s_mul_hi_u32 s5, s17, s2
-; GCN-NEXT: s_addc_u32 s0, s0, s7
-; GCN-NEXT: s_addc_u32 s1, s5, 0
-; GCN-NEXT: s_mul_i32 s2, s17, s2
-; GCN-NEXT: s_add_u32 s0, s0, s2
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: s_mul_i32 s1, s12, s1
-; GCN-NEXT: s_mul_hi_u32 s2, s12, s0
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s2, s13, s0
-; GCN-NEXT: s_mul_i32 s0, s12, s0
-; GCN-NEXT: s_add_i32 s5, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: s_sub_i32 s1, s17, s5
-; GCN-NEXT: v_sub_co_u32_e32 v0, vcc, s16, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_subb_u32 s7, s1, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s12, v0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s15, s7, 0
-; GCN-NEXT: s_cmp_ge_u32 s15, s13
-; GCN-NEXT: s_cselect_b32 s16, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v1
-; GCN-NEXT: s_cmp_eq_u32 s15, s13
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3]
-; GCN-NEXT: v_mov_b32_e32 v3, s16
-; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3]
-; GCN-NEXT: s_subb_u32 s2, s7, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v1
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s2, s2, 0
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NEXT: v_mov_b32_e32 v3, s2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: s_subb_u32 s0, s17, s5
-; GCN-NEXT: s_cmp_ge_u32 s0, s13
-; GCN-NEXT: s_cselect_b32 s1, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
-; GCN-NEXT: s_cmp_eq_u32 s0, s13
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, s1
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v3
+; GCN-NEXT: v_add_co_u32_e32 v4, vcc, v2, v5
+; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
+; GCN-NEXT: v_xor_b32_e32 v4, v4, v5
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v5
+; GCN-NEXT: v_cvt_f32_u32_e32 v5, v4
+; GCN-NEXT: v_cvt_f32_u32_e32 v6, v3
+; GCN-NEXT: v_sub_co_u32_e32 v7, vcc, 0, v4
+; GCN-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v3, vcc
+; GCN-NEXT: v_madmk_f32 v5, v6, 0x4f800000, v5
+; GCN-NEXT: v_rcp_f32_e32 v5, v5
+; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
+; GCN-NEXT: v_trunc_f32_e32 v6, v6
+; GCN-NEXT: v_madmk_f32 v5, v6, 0xcf800000, v5
+; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v7, v6
+; GCN-NEXT: v_mul_hi_u32 v9, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v8, v5
+; GCN-NEXT: v_mul_lo_u32 v12, v7, v5
+; GCN-NEXT: v_add_u32_e32 v9, v9, v10
+; GCN-NEXT: v_add_u32_e32 v9, v9, v11
+; GCN-NEXT: v_mul_lo_u32 v10, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v12
+; GCN-NEXT: v_mul_hi_u32 v13, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v14, v6, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
+; GCN-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc
+; GCN-NEXT: v_mul_lo_u32 v13, v6, v12
+; GCN-NEXT: v_mul_hi_u32 v12, v6, v12
+; GCN-NEXT: v_add_co_u32_e32 v10, vcc, v10, v13
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v14, vcc
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9
+; GCN-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
+; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
+; GCN-NEXT: v_mul_hi_u32 v10, v7, v5
+; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
+; GCN-NEXT: v_mul_lo_u32 v7, v7, v5
+; GCN-NEXT: v_add_u32_e32 v9, v10, v9
+; GCN-NEXT: v_add_u32_e32 v8, v9, v8
+; GCN-NEXT: v_mul_lo_u32 v11, v5, v8
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v7
+; GCN-NEXT: v_mul_hi_u32 v13, v5, v8
+; GCN-NEXT: v_mul_hi_u32 v10, v6, v7
+; GCN-NEXT: v_mul_lo_u32 v7, v6, v7
+; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GCN-NEXT: v_mul_lo_u32 v8, v6, v8
+; GCN-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7
+; GCN-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
+; GCN-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
+; GCN-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
+; GCN-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
+; GCN-NEXT: v_add_co_u32_e32 v8, vcc, v0, v7
+; GCN-NEXT: v_xor_b32_e32 v8, v8, v7
+; GCN-NEXT: v_mul_lo_u32 v9, v8, v6
+; GCN-NEXT: v_mul_hi_u32 v10, v8, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GCN-NEXT: v_mul_lo_u32 v11, v1, v5
+; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
+; GCN-NEXT: v_mul_hi_u32 v12, v1, v6
+; GCN-NEXT: v_mul_lo_u32 v6, v1, v6
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v9, v11
+; GCN-NEXT: v_addc_co_u32_e32 v5, vcc, v10, v5, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v12, vcc
+; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
+; GCN-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v9, vcc
+; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
+; GCN-NEXT: v_mul_hi_u32 v9, v4, v5
+; GCN-NEXT: v_mul_lo_u32 v10, v3, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
+; GCN-NEXT: v_add_u32_e32 v6, v9, v6
+; GCN-NEXT: v_add_u32_e32 v6, v6, v10
+; GCN-NEXT: v_sub_u32_e32 v9, v1, v6
+; GCN-NEXT: v_sub_co_u32_e32 v5, vcc, v8, v5
+; GCN-NEXT: v_subb_co_u32_e64 v8, s[0:1], v9, v3, vcc
+; GCN-NEXT: v_sub_co_u32_e64 v9, s[0:1], v5, v4
+; GCN-NEXT: v_subbrev_co_u32_e64 v10, s[2:3], 0, v8, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v10, v3
+; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v9, v4
+; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v10, v3
+; GCN-NEXT: v_subb_co_u32_e64 v8, s[0:1], v8, v3, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[2:3]
+; GCN-NEXT: v_sub_co_u32_e64 v12, s[0:1], v9, v4
+; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v4
+; GCN-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v8, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
+; GCN-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v12, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s14, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s14, v2
-; GCN-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NEXT: v_subrev_co_u32_e32 v0, vcc, s14, v0
-; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v8, v10, v8, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
+; GCN-NEXT: v_xor_b32_e32 v3, v3, v7
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
+; GCN-NEXT: v_sub_co_u32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v7, vcc
; GCN-NEXT: s_cbranch_execnz .LBB8_3
; GCN-NEXT: .LBB8_2:
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
-; GCN-NEXT: s_sub_i32 s0, 0, s4
-; GCN-NEXT: s_mov_b32 s1, 0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s0, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s0, s2, s0
-; GCN-NEXT: s_add_i32 s2, s2, s0
-; GCN-NEXT: s_mul_hi_u32 s0, s6, s2
-; GCN-NEXT: s_mul_i32 s0, s0, s4
-; GCN-NEXT: s_sub_i32 s0, s6, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s4
-; GCN-NEXT: s_cmp_ge_u32 s0, s4
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s4
-; GCN-NEXT: s_cmp_ge_u32 s0, s4
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v2
+; GCN-NEXT: v_sub_u32_e32 v3, 0, v2
+; GCN-NEXT: v_mov_b32_e32 v4, 0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_lo_u32 v3, v3, v1
+; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
+; GCN-NEXT: v_add_u32_e32 v1, v1, v3
+; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
+; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
+; GCN-NEXT: v_sub_u32_e32 v0, v0, v1
+; GCN-NEXT: v_sub_u32_e32 v1, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_sub_u32_e32 v1, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc
; GCN-NEXT: .LBB8_3:
-; GCN-NEXT: v_mov_b32_e32 v2, 0
-; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: global_store_dwordx2 v0, v[3:4], s[8:9]
; GCN-NEXT: s_endpgm
; GCN-NEXT: .LBB8_4:
-; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GCN-NEXT: ; implicit-def: $vgpr3_vgpr4
; GCN-NEXT: s_branch .LBB8_2
;
; TAHITI-LABEL: srem_i64:
@@ -2689,350 +2583,297 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx4 v[0:3], v8, s[10:11] offset:16
; GCN-NEXT: global_load_dwordx4 v[4:7], v8, s[10:11]
-; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_readfirstlane_b32 s11, v1
-; GCN-NEXT: v_readfirstlane_b32 s10, v0
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_readfirstlane_b32 s13, v5
-; GCN-NEXT: v_readfirstlane_b32 s12, v4
-; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[10:11]
-; GCN-NEXT: s_mov_b32 s0, 0
-; GCN-NEXT: v_readfirstlane_b32 s5, v3
-; GCN-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-NEXT: v_readfirstlane_b32 s7, v7
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: v_readfirstlane_b32 s6, v6
-; GCN-NEXT: s_cbranch_scc0 .LBB10_7
+; GCN-NEXT: v_or_b32_e32 v9, v5, v1
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; GCN-NEXT: s_cbranch_vccz .LBB10_7
; GCN-NEXT: ; %bb.1:
-; GCN-NEXT: s_ashr_i32 s0, s11, 31
-; GCN-NEXT: s_add_u32 s2, s10, s0
-; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: s_addc_u32 s3, s11, s0
-; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[0:1]
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17
-; GCN-NEXT: s_sub_u32 s0, 0, s16
-; GCN-NEXT: s_subb_u32 s1, 0, s17
-; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
-; GCN-NEXT: v_rcp_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v1
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_mul_i32 s11, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s19, s0, s3
-; GCN-NEXT: s_mul_i32 s18, s1, s3
-; GCN-NEXT: s_add_i32 s11, s19, s11
-; GCN-NEXT: s_add_i32 s11, s11, s18
-; GCN-NEXT: s_mul_i32 s20, s0, s3
-; GCN-NEXT: s_mul_hi_u32 s18, s3, s11
-; GCN-NEXT: s_mul_i32 s19, s3, s11
-; GCN-NEXT: s_mul_hi_u32 s3, s3, s20
-; GCN-NEXT: s_add_u32 s3, s3, s19
-; GCN-NEXT: s_addc_u32 s18, 0, s18
-; GCN-NEXT: s_mul_hi_u32 s21, s2, s20
-; GCN-NEXT: s_mul_i32 s20, s2, s20
-; GCN-NEXT: s_add_u32 s3, s3, s20
-; GCN-NEXT: s_mul_hi_u32 s19, s2, s11
-; GCN-NEXT: s_addc_u32 s3, s18, s21
-; GCN-NEXT: s_addc_u32 s18, s19, 0
-; GCN-NEXT: s_mul_i32 s11, s2, s11
-; GCN-NEXT: s_add_u32 s3, s3, s11
-; GCN-NEXT: s_addc_u32 s11, 0, s18
-; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s11
-; GCN-NEXT: v_readfirstlane_b32 s11, v0
-; GCN-NEXT: s_mul_i32 s3, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s18, s0, s11
-; GCN-NEXT: s_add_i32 s3, s18, s3
-; GCN-NEXT: s_mul_i32 s1, s1, s11
-; GCN-NEXT: s_add_i32 s3, s3, s1
-; GCN-NEXT: s_mul_i32 s0, s0, s11
-; GCN-NEXT: s_mul_hi_u32 s18, s2, s0
-; GCN-NEXT: s_mul_i32 s19, s2, s0
-; GCN-NEXT: s_mul_i32 s21, s11, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s11, s0
-; GCN-NEXT: s_mul_hi_u32 s20, s11, s3
-; GCN-NEXT: s_add_u32 s0, s0, s21
-; GCN-NEXT: s_addc_u32 s11, 0, s20
-; GCN-NEXT: s_add_u32 s0, s0, s19
-; GCN-NEXT: s_mul_hi_u32 s1, s2, s3
-; GCN-NEXT: s_addc_u32 s0, s11, s18
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mul_i32 s3, s2, s3
-; GCN-NEXT: s_add_u32 s0, s0, s3
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s1
-; GCN-NEXT: s_ashr_i32 s18, s13, 31
-; GCN-NEXT: s_add_u32 s0, s12, s18
-; GCN-NEXT: s_mov_b32 s19, s18
-; GCN-NEXT: s_addc_u32 s1, s13, s18
-; GCN-NEXT: s_xor_b64 s[20:21], s[0:1], s[18:19]
-; GCN-NEXT: v_readfirstlane_b32 s3, v0
-; GCN-NEXT: s_mul_i32 s1, s20, s2
-; GCN-NEXT: s_mul_hi_u32 s11, s20, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s20, s2
-; GCN-NEXT: s_add_u32 s1, s11, s1
-; GCN-NEXT: s_addc_u32 s0, 0, s0
-; GCN-NEXT: s_mul_hi_u32 s13, s21, s3
-; GCN-NEXT: s_mul_i32 s3, s21, s3
-; GCN-NEXT: s_add_u32 s1, s1, s3
-; GCN-NEXT: s_mul_hi_u32 s11, s21, s2
-; GCN-NEXT: s_addc_u32 s0, s0, s13
-; GCN-NEXT: s_addc_u32 s1, s11, 0
-; GCN-NEXT: s_mul_i32 s2, s21, s2
-; GCN-NEXT: s_add_u32 s0, s0, s2
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: s_mul_i32 s1, s16, s1
-; GCN-NEXT: s_mul_hi_u32 s2, s16, s0
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s2, s17, s0
-; GCN-NEXT: s_mul_i32 s0, s16, s0
-; GCN-NEXT: s_add_i32 s11, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: s_sub_i32 s1, s21, s11
-; GCN-NEXT: v_sub_co_u32_e32 v0, vcc, s20, v0
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_subb_u32 s13, s1, s17
-; GCN-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s16, v0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s19, s13, 0
-; GCN-NEXT: s_cmp_ge_u32 s19, s17
-; GCN-NEXT: s_cselect_b32 s20, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v1
-; GCN-NEXT: s_cmp_eq_u32 s19, s17
-; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3]
-; GCN-NEXT: v_mov_b32_e32 v3, s20
-; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3]
-; GCN-NEXT: s_subb_u32 s2, s13, s17
-; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s16, v1
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s2, s2, 0
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
-; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v2, s19
-; GCN-NEXT: v_mov_b32_e32 v3, s2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GCN-NEXT: s_subb_u32 s0, s21, s11
-; GCN-NEXT: s_cmp_ge_u32 s0, s17
-; GCN-NEXT: s_cselect_b32 s1, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0
-; GCN-NEXT: s_cmp_eq_u32 s0, s17
-; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT: v_mov_b32_e32 v4, s1
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
-; GCN-NEXT: v_mov_b32_e32 v4, s0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GCN-NEXT: v_xor_b32_e32 v0, s18, v0
-; GCN-NEXT: v_xor_b32_e32 v1, s18, v2
-; GCN-NEXT: v_mov_b32_e32 v2, s18
-; GCN-NEXT: v_subrev_co_u32_e32 v0, vcc, s18, v0
-; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v9, 31, v1
+; GCN-NEXT: v_add_co_u32_e32 v8, vcc, v0, v9
+; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v9, vcc
+; GCN-NEXT: v_xor_b32_e32 v8, v8, v9
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v9
+; GCN-NEXT: v_cvt_f32_u32_e32 v9, v8
+; GCN-NEXT: v_cvt_f32_u32_e32 v10, v1
+; GCN-NEXT: v_sub_co_u32_e32 v11, vcc, 0, v8
+; GCN-NEXT: v_subb_co_u32_e32 v12, vcc, 0, v1, vcc
+; GCN-NEXT: v_madmk_f32 v9, v10, 0x4f800000, v9
+; GCN-NEXT: v_rcp_f32_e32 v9, v9
+; GCN-NEXT: v_mul_f32_e32 v9, 0x5f7ffffc, v9
+; GCN-NEXT: v_mul_f32_e32 v10, 0x2f800000, v9
+; GCN-NEXT: v_trunc_f32_e32 v10, v10
+; GCN-NEXT: v_madmk_f32 v9, v10, 0xcf800000, v9
+; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GCN-NEXT: v_mul_lo_u32 v14, v11, v10
+; GCN-NEXT: v_mul_hi_u32 v13, v11, v9
+; GCN-NEXT: v_mul_lo_u32 v15, v12, v9
+; GCN-NEXT: v_mul_lo_u32 v16, v11, v9
+; GCN-NEXT: v_add_u32_e32 v13, v13, v14
+; GCN-NEXT: v_add_u32_e32 v13, v13, v15
+; GCN-NEXT: v_mul_lo_u32 v14, v9, v13
+; GCN-NEXT: v_mul_hi_u32 v15, v9, v16
+; GCN-NEXT: v_mul_hi_u32 v17, v9, v13
+; GCN-NEXT: v_mul_hi_u32 v18, v10, v13
+; GCN-NEXT: v_mul_lo_u32 v13, v10, v13
+; GCN-NEXT: v_add_co_u32_e32 v14, vcc, v15, v14
+; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v17, vcc
+; GCN-NEXT: v_mul_lo_u32 v17, v10, v16
+; GCN-NEXT: v_mul_hi_u32 v16, v10, v16
+; GCN-NEXT: v_add_co_u32_e32 v14, vcc, v14, v17
+; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, v15, v16, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v18, vcc
+; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v14, v13
+; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v15, vcc
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v9, v13
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v14, vcc
+; GCN-NEXT: v_mul_lo_u32 v13, v11, v10
+; GCN-NEXT: v_mul_hi_u32 v14, v11, v9
+; GCN-NEXT: v_mul_lo_u32 v12, v12, v9
+; GCN-NEXT: v_mul_lo_u32 v11, v11, v9
+; GCN-NEXT: v_add_u32_e32 v13, v14, v13
+; GCN-NEXT: v_add_u32_e32 v12, v13, v12
+; GCN-NEXT: v_mul_lo_u32 v15, v9, v12
+; GCN-NEXT: v_mul_hi_u32 v16, v9, v11
+; GCN-NEXT: v_mul_hi_u32 v17, v9, v12
+; GCN-NEXT: v_mul_hi_u32 v14, v10, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v10, v11
+; GCN-NEXT: v_mul_hi_u32 v13, v10, v12
+; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v16, v15
+; GCN-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v17, vcc
+; GCN-NEXT: v_mul_lo_u32 v12, v10, v12
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v15, v11
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v11, v12
+; GCN-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v9, v11
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v11, 31, v5
+; GCN-NEXT: v_add_co_u32_e32 v12, vcc, v4, v11
+; GCN-NEXT: v_xor_b32_e32 v12, v12, v11
+; GCN-NEXT: v_mul_lo_u32 v13, v12, v10
+; GCN-NEXT: v_mul_hi_u32 v14, v12, v9
+; GCN-NEXT: v_mul_hi_u32 v15, v12, v10
+; GCN-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v11, vcc
+; GCN-NEXT: v_xor_b32_e32 v5, v5, v11
+; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v14, v13
+; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v15, vcc
+; GCN-NEXT: v_mul_lo_u32 v15, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
+; GCN-NEXT: v_mul_hi_u32 v16, v5, v10
+; GCN-NEXT: v_mul_lo_u32 v10, v5, v10
+; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v15
+; GCN-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v16, vcc
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v13, vcc
+; GCN-NEXT: v_mul_lo_u32 v10, v8, v10
+; GCN-NEXT: v_mul_hi_u32 v13, v8, v9
+; GCN-NEXT: v_mul_lo_u32 v14, v1, v9
+; GCN-NEXT: v_mul_lo_u32 v9, v8, v9
+; GCN-NEXT: v_add_u32_e32 v10, v13, v10
+; GCN-NEXT: v_add_u32_e32 v10, v10, v14
+; GCN-NEXT: v_sub_u32_e32 v13, v5, v10
+; GCN-NEXT: v_sub_co_u32_e32 v9, vcc, v12, v9
+; GCN-NEXT: v_subb_co_u32_e64 v12, s[0:1], v13, v1, vcc
+; GCN-NEXT: v_sub_co_u32_e64 v13, s[0:1], v9, v8
+; GCN-NEXT: v_subbrev_co_u32_e64 v14, s[2:3], 0, v12, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v14, v1
+; GCN-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v13, v8
+; GCN-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v10, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v14, v1
+; GCN-NEXT: v_subb_co_u32_e64 v12, s[0:1], v12, v1, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[2:3]
+; GCN-NEXT: v_sub_co_u32_e64 v16, s[0:1], v13, v8
+; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v8
+; GCN-NEXT: v_subbrev_co_u32_e64 v12, s[0:1], 0, v12, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v15
+; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v12, v14, v12, s[0:1]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v12, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v5, v9, v13, vcc
+; GCN-NEXT: v_xor_b32_e32 v5, v5, v11
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v11
+; GCN-NEXT: v_sub_co_u32_e32 v8, vcc, v5, v11
+; GCN-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v11, vcc
; GCN-NEXT: s_cbranch_execnz .LBB10_3
; GCN-NEXT: .LBB10_2:
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10
-; GCN-NEXT: s_sub_i32 s0, 0, s10
-; GCN-NEXT: s_mov_b32 s1, 0
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s0, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s0, s2, s0
-; GCN-NEXT: s_add_i32 s2, s2, s0
-; GCN-NEXT: s_mul_hi_u32 s0, s12, s2
-; GCN-NEXT: s_mul_i32 s0, s0, s10
-; GCN-NEXT: s_sub_i32 s0, s12, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s10
-; GCN-NEXT: s_cmp_ge_u32 s0, s10
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s10
-; GCN-NEXT: s_cmp_ge_u32 s0, s10
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
+; GCN-NEXT: v_sub_u32_e32 v5, 0, v0
+; GCN-NEXT: v_mov_b32_e32 v9, 0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v1
+; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
+; GCN-NEXT: v_add_u32_e32 v1, v1, v5
+; GCN-NEXT: v_mul_hi_u32 v1, v4, v1
+; GCN-NEXT: v_mul_lo_u32 v1, v1, v0
+; GCN-NEXT: v_sub_u32_e32 v1, v4, v1
+; GCN-NEXT: v_sub_u32_e32 v4, v1, v0
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GCN-NEXT: v_sub_u32_e32 v4, v1, v0
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0
+; GCN-NEXT: v_cndmask_b32_e32 v8, v1, v4, vcc
; GCN-NEXT: .LBB10_3:
-; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5]
-; GCN-NEXT: s_mov_b32 s0, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_cbranch_scc0 .LBB10_8
+; GCN-NEXT: v_or_b32_e32 v1, v7, v3
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GCN-NEXT: s_cbranch_vccz .LBB10_8
; GCN-NEXT: ; %bb.4:
-; GCN-NEXT: s_ashr_i32 s0, s5, 31
-; GCN-NEXT: s_add_u32 s2, s4, s0
-; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: s_addc_u32 s3, s5, s0
-; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1]
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s13
-; GCN-NEXT: s_sub_u32 s0, 0, s12
-; GCN-NEXT: s_subb_u32 s1, 0, s13
-; GCN-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2
-; GCN-NEXT: v_rcp_f32_e32 v2, v2
-; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
-; GCN-NEXT: v_trunc_f32_e32 v3, v3
-; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v3
+; GCN-NEXT: v_add_co_u32_e32 v1, vcc, v2, v0
+; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v0, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v0
+; GCN-NEXT: v_xor_b32_e32 v0, v3, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, v0
+; GCN-NEXT: v_sub_co_u32_e32 v5, vcc, 0, v1
+; GCN-NEXT: v_subb_co_u32_e32 v10, vcc, 0, v0, vcc
+; GCN-NEXT: v_madmk_f32 v3, v4, 0x4f800000, v3
+; GCN-NEXT: v_rcp_f32_e32 v3, v3
+; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
+; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
+; GCN-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-NEXT: v_madmk_f32 v3, v4, 0xcf800000, v3
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_readfirstlane_b32 s2, v3
-; GCN-NEXT: v_readfirstlane_b32 s3, v2
-; GCN-NEXT: s_mul_i32 s5, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s15, s0, s3
-; GCN-NEXT: s_mul_i32 s14, s1, s3
-; GCN-NEXT: s_add_i32 s5, s15, s5
-; GCN-NEXT: s_add_i32 s5, s5, s14
-; GCN-NEXT: s_mul_i32 s16, s0, s3
-; GCN-NEXT: s_mul_hi_u32 s14, s3, s5
-; GCN-NEXT: s_mul_i32 s15, s3, s5
-; GCN-NEXT: s_mul_hi_u32 s3, s3, s16
-; GCN-NEXT: s_add_u32 s3, s3, s15
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: s_mul_hi_u32 s17, s2, s16
-; GCN-NEXT: s_mul_i32 s16, s2, s16
-; GCN-NEXT: s_add_u32 s3, s3, s16
-; GCN-NEXT: s_mul_hi_u32 s15, s2, s5
-; GCN-NEXT: s_addc_u32 s3, s14, s17
-; GCN-NEXT: s_addc_u32 s14, s15, 0
-; GCN-NEXT: s_mul_i32 s5, s2, s5
-; GCN-NEXT: s_add_u32 s3, s3, s5
-; GCN-NEXT: s_addc_u32 s5, 0, s14
-; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s3, v2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s5
-; GCN-NEXT: v_readfirstlane_b32 s5, v2
-; GCN-NEXT: s_mul_i32 s3, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s14, s0, s5
-; GCN-NEXT: s_add_i32 s3, s14, s3
-; GCN-NEXT: s_mul_i32 s1, s1, s5
-; GCN-NEXT: s_add_i32 s3, s3, s1
-; GCN-NEXT: s_mul_i32 s0, s0, s5
-; GCN-NEXT: s_mul_hi_u32 s14, s2, s0
-; GCN-NEXT: s_mul_i32 s15, s2, s0
-; GCN-NEXT: s_mul_i32 s17, s5, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s5, s0
-; GCN-NEXT: s_mul_hi_u32 s16, s5, s3
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: s_addc_u32 s5, 0, s16
-; GCN-NEXT: s_add_u32 s0, s0, s15
-; GCN-NEXT: s_mul_hi_u32 s1, s2, s3
-; GCN-NEXT: s_addc_u32 s0, s5, s14
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mul_i32 s3, s2, s3
-; GCN-NEXT: s_add_u32 s0, s0, s3
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s1
-; GCN-NEXT: s_ashr_i32 s14, s7, 31
-; GCN-NEXT: s_add_u32 s0, s6, s14
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_addc_u32 s1, s7, s14
-; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15]
-; GCN-NEXT: v_readfirstlane_b32 s3, v2
-; GCN-NEXT: s_mul_i32 s1, s16, s2
-; GCN-NEXT: s_mul_hi_u32 s5, s16, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s16, s2
-; GCN-NEXT: s_add_u32 s1, s5, s1
-; GCN-NEXT: s_addc_u32 s0, 0, s0
-; GCN-NEXT: s_mul_hi_u32 s7, s17, s3
-; GCN-NEXT: s_mul_i32 s3, s17, s3
-; GCN-NEXT: s_add_u32 s1, s1, s3
-; GCN-NEXT: s_mul_hi_u32 s5, s17, s2
-; GCN-NEXT: s_addc_u32 s0, s0, s7
-; GCN-NEXT: s_addc_u32 s1, s5, 0
-; GCN-NEXT: s_mul_i32 s2, s17, s2
-; GCN-NEXT: s_add_u32 s0, s0, s2
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: s_mul_i32 s1, s12, s1
-; GCN-NEXT: s_mul_hi_u32 s2, s12, s0
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s2, s13, s0
-; GCN-NEXT: s_mul_i32 s0, s12, s0
-; GCN-NEXT: s_add_i32 s5, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NEXT: s_sub_i32 s1, s17, s5
-; GCN-NEXT: v_sub_co_u32_e32 v2, vcc, s16, v2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_subb_u32 s7, s1, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v2
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s15, s7, 0
-; GCN-NEXT: s_cmp_ge_u32 s15, s13
-; GCN-NEXT: s_cselect_b32 s16, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v3
-; GCN-NEXT: s_cmp_eq_u32 s15, s13
-; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[2:3]
-; GCN-NEXT: v_mov_b32_e32 v5, s16
-; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[2:3]
-; GCN-NEXT: s_subb_u32 s2, s7, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v3
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s2, s2, 0
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
-; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v4, s15
-; GCN-NEXT: v_mov_b32_e32 v5, s2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT: s_subb_u32 s0, s17, s5
-; GCN-NEXT: s_cmp_ge_u32 s0, s13
-; GCN-NEXT: s_cselect_b32 s1, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v2
-; GCN-NEXT: s_cmp_eq_u32 s0, s13
-; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT: v_mov_b32_e32 v6, s1
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GCN-NEXT: v_mov_b32_e32 v6, s0
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; GCN-NEXT: v_xor_b32_e32 v2, s14, v2
-; GCN-NEXT: v_xor_b32_e32 v3, s14, v4
-; GCN-NEXT: v_mov_b32_e32 v4, s14
-; GCN-NEXT: v_subrev_co_u32_e32 v2, vcc, s14, v2
-; GCN-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
+; GCN-NEXT: v_mul_lo_u32 v12, v5, v4
+; GCN-NEXT: v_mul_hi_u32 v11, v5, v3
+; GCN-NEXT: v_mul_lo_u32 v13, v10, v3
+; GCN-NEXT: v_mul_lo_u32 v14, v5, v3
+; GCN-NEXT: v_add_u32_e32 v11, v11, v12
+; GCN-NEXT: v_add_u32_e32 v11, v11, v13
+; GCN-NEXT: v_mul_lo_u32 v12, v3, v11
+; GCN-NEXT: v_mul_hi_u32 v13, v3, v14
+; GCN-NEXT: v_mul_hi_u32 v15, v3, v11
+; GCN-NEXT: v_mul_hi_u32 v16, v4, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v4, v11
+; GCN-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
+; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v15, vcc
+; GCN-NEXT: v_mul_lo_u32 v15, v4, v14
+; GCN-NEXT: v_mul_hi_u32 v14, v4, v14
+; GCN-NEXT: v_add_co_u32_e32 v12, vcc, v12, v15
+; GCN-NEXT: v_addc_co_u32_e32 v12, vcc, v13, v14, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v16, vcc
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v11
+; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v12, vcc
+; GCN-NEXT: v_mul_lo_u32 v11, v5, v4
+; GCN-NEXT: v_mul_hi_u32 v12, v5, v3
+; GCN-NEXT: v_mul_lo_u32 v10, v10, v3
+; GCN-NEXT: v_mul_lo_u32 v5, v5, v3
+; GCN-NEXT: v_add_u32_e32 v11, v12, v11
+; GCN-NEXT: v_add_u32_e32 v10, v11, v10
+; GCN-NEXT: v_mul_lo_u32 v13, v3, v10
+; GCN-NEXT: v_mul_hi_u32 v14, v3, v5
+; GCN-NEXT: v_mul_hi_u32 v15, v3, v10
+; GCN-NEXT: v_mul_hi_u32 v12, v4, v5
+; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
+; GCN-NEXT: v_mul_hi_u32 v11, v4, v10
+; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v14, v13
+; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v15, vcc
+; GCN-NEXT: v_mul_lo_u32 v10, v4, v10
+; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v13, v5
+; GCN-NEXT: v_addc_co_u32_e32 v5, vcc, v14, v12, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
+; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
+; GCN-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
+; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v10, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v7
+; GCN-NEXT: v_add_co_u32_e32 v10, vcc, v6, v5
+; GCN-NEXT: v_xor_b32_e32 v10, v10, v5
+; GCN-NEXT: v_mul_lo_u32 v11, v10, v4
+; GCN-NEXT: v_mul_hi_u32 v12, v10, v3
+; GCN-NEXT: v_mul_hi_u32 v13, v10, v4
+; GCN-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v5, vcc
+; GCN-NEXT: v_xor_b32_e32 v7, v7, v5
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
+; GCN-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GCN-NEXT: v_mul_lo_u32 v13, v7, v3
+; GCN-NEXT: v_mul_hi_u32 v3, v7, v3
+; GCN-NEXT: v_mul_hi_u32 v14, v7, v4
+; GCN-NEXT: v_mul_lo_u32 v4, v7, v4
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13
+; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v12, v3, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v14, vcc
+; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v11, vcc
+; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT: v_mul_hi_u32 v11, v1, v3
+; GCN-NEXT: v_mul_lo_u32 v12, v0, v3
+; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT: v_add_u32_e32 v4, v11, v4
+; GCN-NEXT: v_add_u32_e32 v4, v4, v12
+; GCN-NEXT: v_sub_u32_e32 v11, v7, v4
+; GCN-NEXT: v_sub_co_u32_e32 v3, vcc, v10, v3
+; GCN-NEXT: v_subb_co_u32_e64 v10, s[0:1], v11, v0, vcc
+; GCN-NEXT: v_sub_co_u32_e64 v11, s[0:1], v3, v1
+; GCN-NEXT: v_subbrev_co_u32_e64 v12, s[2:3], 0, v10, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v12, v0
+; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v11, v1
+; GCN-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v12, v0
+; GCN-NEXT: v_subb_co_u32_e64 v10, s[0:1], v10, v0, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
+; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[2:3]
+; GCN-NEXT: v_sub_co_u32_e64 v14, s[0:1], v11, v1
+; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
+; GCN-NEXT: v_subbrev_co_u32_e64 v10, s[0:1], 0, v10, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v0
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v13
+; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v14, s[0:1]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GCN-NEXT: v_cndmask_b32_e64 v10, v12, v10, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v11, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v10, vcc
+; GCN-NEXT: v_xor_b32_e32 v1, v1, v5
+; GCN-NEXT: v_xor_b32_e32 v0, v0, v5
+; GCN-NEXT: v_sub_co_u32_e32 v10, vcc, v1, v5
+; GCN-NEXT: v_subb_co_u32_e32 v11, vcc, v0, v5, vcc
; GCN-NEXT: s_cbranch_execnz .LBB10_6
; GCN-NEXT: .LBB10_5:
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4
-; GCN-NEXT: s_sub_i32 s0, 0, s4
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_mul_lo_u32 v3, s0, v2
-; GCN-NEXT: v_mul_hi_u32 v3, v2, v3
-; GCN-NEXT: v_add_u32_e32 v2, v2, v3
-; GCN-NEXT: v_mul_hi_u32 v2, s6, v2
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s4
-; GCN-NEXT: v_sub_u32_e32 v2, s6, v2
-; GCN-NEXT: v_subrev_u32_e32 v3, s4, v2
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GCN-NEXT: v_subrev_u32_e32 v3, s4, v2
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
-; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, v2
+; GCN-NEXT: v_sub_u32_e32 v1, 0, v2
+; GCN-NEXT: v_mov_b32_e32 v11, 0
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_mul_lo_u32 v1, v1, v0
+; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
+; GCN-NEXT: v_add_u32_e32 v0, v0, v1
+; GCN-NEXT: v_mul_hi_u32 v0, v6, v0
+; GCN-NEXT: v_mul_lo_u32 v0, v0, v2
+; GCN-NEXT: v_sub_u32_e32 v0, v6, v0
+; GCN-NEXT: v_sub_u32_e32 v1, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_sub_u32_e32 v1, v0, v2
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
+; GCN-NEXT: v_cndmask_b32_e32 v10, v0, v1, vcc
; GCN-NEXT: .LBB10_6:
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: global_store_dwordx4 v0, v[8:11], s[8:9]
; GCN-NEXT: s_endpgm
; GCN-NEXT: .LBB10_7:
-; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9
; GCN-NEXT: s_branch .LBB10_2
; GCN-NEXT: .LBB10_8:
; GCN-NEXT: s_branch .LBB10_5
@@ -3184,7 +3025,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_mul_hi_u32 v1, v4, v1
; TAHITI-NEXT: v_mul_lo_u32 v1, v1, v0
; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v4, v1
-; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, v1, v0
+; TAHITI-NEXT: v_subrev_i32_e32 v4, vcc, v0, v1
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0
; TAHITI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; TAHITI-NEXT: v_sub_i32_e32 v4, vcc, v1, v0
@@ -4867,177 +4708,148 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: global_load_dwordx4 v[14:17], v8, s[10:11]
; GCN-NEXT: global_load_dwordx4 v[0:3], v8, s[10:11] offset:48
; GCN-NEXT: global_load_dwordx4 v[4:7], v8, s[10:11] offset:16
-; GCN-NEXT: s_waitcnt vmcnt(3)
-; GCN-NEXT: v_readfirstlane_b32 s5, v11
-; GCN-NEXT: v_readfirstlane_b32 s4, v10
; GCN-NEXT: s_waitcnt vmcnt(2)
-; GCN-NEXT: v_readfirstlane_b32 s7, v15
-; GCN-NEXT: v_readfirstlane_b32 s6, v14
-; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5]
-; GCN-NEXT: s_mov_b32 s0, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_cbranch_scc0 .LBB12_13
+; GCN-NEXT: v_or_b32_e32 v9, v15, v11
+; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; GCN-NEXT: s_cbranch_vccz .LBB12_13
; GCN-NEXT: ; %bb.1:
-; GCN-NEXT: s_ashr_i32 s0, s5, 31
-; GCN-NEXT: s_add_u32 s2, s4, s0
-; GCN-NEXT: s_mov_b32 s1, s0
-; GCN-NEXT: s_addc_u32 s3, s5, s0
-; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1]
-; GCN-NEXT: v_cvt_f32_u32_e32 v8, s12
-; GCN-NEXT: v_cvt_f32_u32_e32 v9, s13
-; GCN-NEXT: s_sub_u32 s0, 0, s12
-; GCN-NEXT: s_subb_u32 s1, 0, s13
-; GCN-NEXT: v_madmk_f32 v8, v9, 0x4f800000, v8
-; GCN-NEXT: v_rcp_f32_e32 v8, v8
-; GCN-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; GCN-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8
-; GCN-NEXT: v_trunc_f32_e32 v9, v9
-; GCN-NEXT: v_madmk_f32 v8, v9, 0xcf800000, v8
-; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9
-; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GCN-NEXT: v_readfirstlane_b32 s2, v9
-; GCN-NEXT: v_readfirstlane_b32 s3, v8
-; GCN-NEXT: s_mul_i32 s5, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s15, s0, s3
-; GCN-NEXT: s_mul_i32 s14, s1, s3
-; GCN-NEXT: s_add_i32 s5, s15, s5
-; GCN-NEXT: s_add_i32 s5, s5, s14
-; GCN-NEXT: s_mul_i32 s16, s0, s3
-; GCN-NEXT: s_mul_hi_u32 s14, s3, s5
-; GCN-NEXT: s_mul_i32 s15, s3, s5
-; GCN-NEXT: s_mul_hi_u32 s3, s3, s16
-; GCN-NEXT: s_add_u32 s3, s3, s15
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: s_mul_hi_u32 s17, s2, s16
-; GCN-NEXT: s_mul_i32 s16, s2, s16
-; GCN-NEXT: s_add_u32 s3, s3, s16
-; GCN-NEXT: s_mul_hi_u32 s15, s2, s5
-; GCN-NEXT: s_addc_u32 s3, s14, s17
-; GCN-NEXT: s_addc_u32 s14, s15, 0
-; GCN-NEXT: s_mul_i32 s5, s2, s5
-; GCN-NEXT: s_add_u32 s3, s3, s5
-; GCN-NEXT: s_addc_u32 s5, 0, s14
-; GCN-NEXT: v_add_co_u32_e32 v8, vcc, s3, v8
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s5
-; GCN-NEXT: v_readfirstlane_b32 s5, v8
-; GCN-NEXT: s_mul_i32 s3, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s14, s0, s5
-; GCN-NEXT: s_add_i32 s3, s14, s3
-; GCN-NEXT: s_mul_i32 s1, s1, s5
-; GCN-NEXT: s_add_i32 s3, s3, s1
-; GCN-NEXT: s_mul_i32 s0, s0, s5
-; GCN-NEXT: s_mul_hi_u32 s14, s2, s0
-; GCN-NEXT: s_mul_i32 s15, s2, s0
-; GCN-NEXT: s_mul_i32 s17, s5, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s5, s0
-; GCN-NEXT: s_mul_hi_u32 s16, s5, s3
-; GCN-NEXT: s_add_u32 s0, s0, s17
-; GCN-NEXT: s_addc_u32 s5, 0, s16
-; GCN-NEXT: s_add_u32 s0, s0, s15
-; GCN-NEXT: s_mul_hi_u32 s1, s2, s3
-; GCN-NEXT: s_addc_u32 s0, s5, s14
-; GCN-NEXT: s_addc_u32 s1, s1, 0
-; GCN-NEXT: s_mul_i32 s3, s2, s3
-; GCN-NEXT: s_add_u32 s0, s0, s3
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: v_add_co_u32_e32 v8, vcc, s0, v8
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_addc_u32 s2, s2, s1
-; GCN-NEXT: s_ashr_i32 s14, s7, 31
-; GCN-NEXT: s_add_u32 s0, s6, s14
-; GCN-NEXT: s_mov_b32 s15, s14
-; GCN-NEXT: s_addc_u32 s1, s7, s14
-; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15]
-; GCN-NEXT: v_readfirstlane_b32 s3, v8
-; GCN-NEXT: s_mul_i32 s1, s16, s2
-; GCN-NEXT: s_mul_hi_u32 s5, s16, s3
-; GCN-NEXT: s_mul_hi_u32 s0, s16, s2
-; GCN-NEXT: s_add_u32 s1, s5, s1
-; GCN-NEXT: s_addc_u32 s0, 0, s0
-; GCN-NEXT: s_mul_hi_u32 s7, s17, s3
-; GCN-NEXT: s_mul_i32 s3, s17, s3
-; GCN-NEXT: s_add_u32 s1, s1, s3
-; GCN-NEXT: s_mul_hi_u32 s5, s17, s2
-; GCN-NEXT: s_addc_u32 s0, s0, s7
-; GCN-NEXT: s_addc_u32 s1, s5, 0
-; GCN-NEXT: s_mul_i32 s2, s17, s2
-; GCN-NEXT: s_add_u32 s0, s0, s2
-; GCN-NEXT: s_addc_u32 s1, 0, s1
-; GCN-NEXT: s_mul_i32 s1, s12, s1
-; GCN-NEXT: s_mul_hi_u32 s2, s12, s0
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s2, s13, s0
-; GCN-NEXT: s_mul_i32 s0, s12, s0
-; GCN-NEXT: s_add_i32 s5, s1, s2
-; GCN-NEXT: v_mov_b32_e32 v8, s0
-; GCN-NEXT: s_sub_i32 s1, s17, s5
-; GCN-NEXT: v_sub_co_u32_e32 v8, vcc, s16, v8
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: s_subb_u32 s7, s1, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v9, s[0:1], s12, v8
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s15, s7, 0
-; GCN-NEXT: s_cmp_ge_u32 s15, s13
-; GCN-NEXT: s_cselect_b32 s16, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v9
-; GCN-NEXT: s_cmp_eq_u32 s15, s13
-; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3]
-; GCN-NEXT: v_mov_b32_e32 v11, s16
-; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[2:3]
-; GCN-NEXT: s_subb_u32 s2, s7, s13
-; GCN-NEXT: v_subrev_co_u32_e64 v11, s[0:1], s12, v9
-; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GCN-NEXT: s_subb_u32 s2, s2, 0
-; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
-; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1]
-; GCN-NEXT: v_mov_b32_e32 v10, s15
-; GCN-NEXT: v_mov_b32_e32 v11, s2
-; GCN-NEXT: s_cmp_lg_u64 vcc, 0
-; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1]
-; GCN-NEXT: s_subb_u32 s0, s17, s5
-; GCN-NEXT: s_cmp_ge_u32 s0, s13
-; GCN-NEXT: s_cselect_b32 s1, -1, 0
-; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v8
-; GCN-NEXT: s_cmp_eq_u32 s0, s13
-; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
-; GCN-NEXT: v_mov_b32_e32 v14, s1
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
-; GCN-NEXT: v_mov_b32_e32 v14, s0
-; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc
-; GCN-NEXT: v_xor_b32_e32 v8, s14, v8
-; GCN-NEXT: v_xor_b32_e32 v9, s14, v10
-; GCN-NEXT: v_mov_b32_e32 v10, s14
-; GCN-NEXT: v_subrev_co_u32_e32 v8, vcc, s14, v8
-; GCN-NEXT: v_subb_co_u32_e32 v9, vcc, v9, v10, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v8, 31, v11
+; GCN-NEXT: v_add_co_u32_e32 v9, vcc, v10, v8
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, v11, v8, vcc
+; GCN-NEXT: v_xor_b32_e32 v9, v9, v8
+; GCN-NEXT: v_xor_b32_e32 v8, v11, v8
+; GCN-NEXT: v_cvt_f32_u32_e32 v11, v9
+; GCN-NEXT: v_cvt_f32_u32_e32 v18, v8
+; GCN-NEXT: v_sub_co_u32_e32 v19, vcc, 0, v9
+; GCN-NEXT: v_subb_co_u32_e32 v20, vcc, 0, v8, vcc
+; GCN-NEXT: v_madmk_f32 v11, v18, 0x4f800000, v11
+; GCN-NEXT: v_rcp_f32_e32 v11, v11
+; GCN-NEXT: v_mul_f32_e32 v11, 0x5f7ffffc, v11
+; GCN-NEXT: v_mul_f32_e32 v18, 0x2f800000, v11
+; GCN-NEXT: v_trunc_f32_e32 v18, v18
+; GCN-NEXT: v_madmk_f32 v11, v18, 0xcf800000, v11
+; GCN-NEXT: v_cvt_u32_f32_e32 v18, v18
+; GCN-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GCN-NEXT: v_mul_lo_u32 v22, v19, v18
+; GCN-NEXT: v_mul_hi_u32 v21, v19, v11
+; GCN-NEXT: v_mul_lo_u32 v23, v20, v11
+; GCN-NEXT: v_mul_lo_u32 v24, v19, v11
+; GCN-NEXT: v_add_u32_e32 v21, v21, v22
+; GCN-NEXT: v_add_u32_e32 v21, v21, v23
+; GCN-NEXT: v_mul_lo_u32 v22, v11, v21
+; GCN-NEXT: v_mul_hi_u32 v23, v11, v24
+; GCN-NEXT: v_mul_hi_u32 v25, v11, v21
+; GCN-NEXT: v_mul_hi_u32 v26, v18, v21
+; GCN-NEXT: v_mul_lo_u32 v21, v18, v21
+; GCN-NEXT: v_add_co_u32_e32 v22, vcc, v23, v22
+; GCN-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v25, vcc
+; GCN-NEXT: v_mul_lo_u32 v25, v18, v24
+; GCN-NEXT: v_mul_hi_u32 v24, v18, v24
+; GCN-NEXT: v_add_co_u32_e32 v22, vcc, v22, v25
+; GCN-NEXT: v_addc_co_u32_e32 v22, vcc, v23, v24, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v23, vcc, 0, v26, vcc
+; GCN-NEXT: v_add_co_u32_e32 v21, vcc, v22, v21
+; GCN-NEXT: v_addc_co_u32_e32 v22, vcc, 0, v23, vcc
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v11, v21
+; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, v18, v22, vcc
+; GCN-NEXT: v_mul_lo_u32 v21, v19, v18
+; GCN-NEXT: v_mul_hi_u32 v22, v19, v11
+; GCN-NEXT: v_mul_lo_u32 v20, v20, v11
+; GCN-NEXT: v_mul_lo_u32 v19, v19, v11
+; GCN-NEXT: v_add_u32_e32 v21, v22, v21
+; GCN-NEXT: v_add_u32_e32 v20, v21, v20
+; GCN-NEXT: v_mul_lo_u32 v23, v11, v20
+; GCN-NEXT: v_mul_hi_u32 v24, v11, v19
+; GCN-NEXT: v_mul_hi_u32 v25, v11, v20
+; GCN-NEXT: v_mul_hi_u32 v22, v18, v19
+; GCN-NEXT: v_mul_lo_u32 v19, v18, v19
+; GCN-NEXT: v_mul_hi_u32 v21, v18, v20
+; GCN-NEXT: v_add_co_u32_e32 v23, vcc, v24, v23
+; GCN-NEXT: v_addc_co_u32_e32 v24, vcc, 0, v25, vcc
+; GCN-NEXT: v_mul_lo_u32 v20, v18, v20
+; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v23, v19
+; GCN-NEXT: v_addc_co_u32_e32 v19, vcc, v24, v22, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v21, vcc
+; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v19, v20
+; GCN-NEXT: v_addc_co_u32_e32 v20, vcc, 0, v21, vcc
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v11, v19
+; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, v18, v20, vcc
+; GCN-NEXT: v_ashrrev_i32_e32 v19, 31, v15
+; GCN-NEXT: v_add_co_u32_e32 v20, vcc, v14, v19
+; GCN-NEXT: v_xor_b32_e32 v20, v20, v19
+; GCN-NEXT: v_mul_lo_u32 v21, v20, v18
+; GCN-NEXT: v_mul_hi_u32 v22, v20, v11
+; GCN-NEXT: v_mul_hi_u32 v23, v20, v18
+; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, v15, v19, vcc
+; GCN-NEXT: v_xor_b32_e32 v15, v15, v19
+; GCN-NEXT: v_add_co_u32_e32 v21, vcc, v22, v21
+; GCN-NEXT: v_addc_co_u32_e32 v22, vcc, 0, v23, vcc
+; GCN-NEXT: v_mul_lo_u32 v23, v15, v11
+; GCN-NEXT: v_mul_hi_u32 v11, v15, v11
+; GCN-NEXT: v_mul_hi_u32 v24, v15, v18
+; GCN-NEXT: v_mul_lo_u32 v18, v15, v18
+; GCN-NEXT: v_add_co_u32_e32 v21, vcc, v21, v23
+; GCN-NEXT: v_addc_co_u32_e32 v11, vcc, v22, v11, vcc
+; GCN-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v24, vcc
+; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v11, v18
+; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v21, vcc
+; GCN-NEXT: v_mul_lo_u32 v18, v9, v18
+; GCN-NEXT: v_mul_hi_u32 v21, v9, v11
+; GCN-NEXT: v_mul_lo_u32 v22, v8, v11
+; GCN-NEXT: v_mul_lo_u32 v11, v9, v11
+; GCN-NEXT: v_add_u32_e32 v18, v21, v18
+; GCN-NEXT: v_add_u32_e32 v18, v18, v22
+; GCN-NEXT: v_sub_u32_e32 v21, v15, v18
+; GCN-NEXT: v_sub_co_u32_e32 v11, vcc, v20, v11
+; GCN-NEXT: v_subb_co_u32_e64 v20, s[0:1], v21, v8, vcc
+; GCN-NEXT: v_sub_co_u32_e64 v21, s[0:1], v11, v9
+; GCN-NEXT: v_subbrev_co_u32_e64 v22, s[2:3], 0, v20, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v22, v8
+; GCN-NEXT: v_cndmask_b32_e64 v23, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v21, v9
+; GCN-NEXT: v_subb_co_u32_e32 v15, vcc, v15, v18, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v24, 0, -1, s[2:3]
+; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v22, v8
+; GCN-NEXT: v_subb_co_u32_e64 v20, s[0:1], v20, v8, s[0:1]
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v15, v8
+; GCN-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[2:3]
+; GCN-NEXT: v_sub_co_u32_e64 v24, s[0:1], v21, v9
+; GCN-NEXT: v_cndmask_b32_e64 v18, 0, -1, vcc
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v11, v9
+; GCN-NEXT: v_subbrev_co_u32_e64 v20, s[0:1], 0, v20, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v15, v8
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v23
+; GCN-NEXT: v_cndmask_b32_e32 v8, v18, v9, vcc
+; GCN-NEXT: v_cndmask_b32_e64 v21, v21, v24, s[0:1]
+; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
+; GCN-NEXT: v_cndmask_b32_e64 v20, v22, v20, s[0:1]
+; GCN-NEXT: v_cndmask_b32_e32 v9, v11, v21, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v8, v15, v20, vcc
+; GCN-NEXT: v_xor_b32_e32 v9, v9, v19
+; GCN-NEXT: v_xor_b32_e32 v11, v8, v19
+; GCN-NEXT: v_sub_co_u32_e32 v8, vcc, v9, v19
+; GCN-NEXT: v_subb_co_u32_e32 v9, vcc, v11, v19, vcc
; GCN-NEXT: s_cbranch_execnz .LBB12_3
; GCN-NEXT: .LBB12_2:
-; GCN-NEXT: v_cvt_f32_u32_e32 v8, s4
-; GCN-NEXT: s_sub_i32 s0, 0, s4
-; GCN-NEXT: s_mov_b32 s1, 0
+; GCN-NEXT: v_cvt_f32_u32_e32 v8, v10
+; GCN-NEXT: v_sub_u32_e32 v9, 0, v10
; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v8
; GCN-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GCN-NEXT: v_readfirstlane_b32 s2, v8
-; GCN-NEXT: s_mul_i32 s0, s0, s2
-; GCN-NEXT: s_mul_hi_u32 s0, s2, s0
-; GCN-NEXT: s_add_i32 s2, s2, s0
-; GCN-NEXT: s_mul_hi_u32 s0, s6, s2
-; GCN-NEXT: s_mul_i32 s0, s0, s4
-; GCN-NEXT: s_sub_i32 s0, s6, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s4
-; GCN-NEXT: s_cmp_ge_u32 s0, s4
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: s_sub_i32 s2, s0, s4
-; GCN-NEXT: s_cmp_ge_u32 s0, s4
-; GCN-NEXT: s_cselect_b32 s0, s2, s0
-; GCN-NEXT: v_mov_b32_e32 v9, s1
-; GCN-NEXT: v_mov_b32_e32 v8, s0
+; GCN-NEXT: v_mul_lo_u32 v9, v9, v8
+; GCN-NEXT: v_mul_hi_u32 v9, v8, v9
+; GCN-NEXT: v_add_u32_e32 v8, v8, v9
+; GCN-NEXT: v_mul_hi_u32 v8, v14, v8
+; GCN-NEXT: v_mul_lo_u32 v8, v8, v10
+; GCN-NEXT: v_sub_u32_e32 v8, v14, v8
+; GCN-NEXT: v_sub_u32_e32 v9, v8, v10
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v10
+; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GCN-NEXT: v_sub_u32_e32 v9, v8, v10
+; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v10
+; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
+; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: .LBB12_3:
; GCN-NEXT: v_or_b32_e32 v11, v17, v13
; GCN-NEXT: v_mov_b32_e32 v10, 0
@@ -5632,7 +5444,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: v_mul_hi_u32 v8, v14, v8
; TAHITI-NEXT: v_mul_lo_u32 v8, v8, v10
; TAHITI-NEXT: v_sub_i32_e32 v8, vcc, v14, v8
-; TAHITI-NEXT: v_sub_i32_e32 v9, vcc, v8, v10
+; TAHITI-NEXT: v_subrev_i32_e32 v9, vcc, v10, v8
; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v8, v10
; TAHITI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; TAHITI-NEXT: v_sub_i32_e32 v9, vcc, v8, v10
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index c9e5ff444f715..20738b8701f28 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -442,71 +442,65 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
define amdgpu_kernel void @s_test_srem23_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem23_64:
; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s9, s[4:5], 0xe
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_load_dword s5, s[4:5], 0xe
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_ashr_i64 s[8:9], s[4:5], 41
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 41
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GCN-NEXT: s_ashr_i64 s[4:5], s[8:9], 41
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 41
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GCN-NEXT: s_xor_b32 s3, s2, s4
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_xor_b32 s1, s0, s8
-; GCN-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-NEXT: s_or_b32 s1, s1, 1
+; GCN-NEXT: s_ashr_i32 s3, s3, 30
+; GCN-NEXT: s_or_b32 s3, s3, 1
+; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
-; GCN-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GCN-NEXT: s_cselect_b32 s1, s1, 0
-; GCN-NEXT: v_readfirstlane_b32 s2, v2
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s1, s1, s8
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: s_bfe_i32 s0, s0, 0x170000
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
+; GCN-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem23_64:
; GCN-IR: ; %bb.0:
+; GCN-IR-NEXT: s_load_dword s9, s[4:5], 0xe
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_load_dword s5, s[4:5], 0xe
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_mov_b32 s4, s0
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 41
-; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 41
-; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[8:9], 41
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 41
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GCN-IR-NEXT: s_xor_b32 s3, s2, s4
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT: s_xor_b32 s1, s0, s8
-; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-IR-NEXT: s_or_b32 s1, s1, 1
+; GCN-IR-NEXT: s_ashr_i32 s3, s3, 30
+; GCN-IR-NEXT: s_or_b32 s3, s3, 1
+; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
-; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v2
-; GCN-IR-NEXT: s_add_i32 s1, s2, s1
-; GCN-IR-NEXT: s_mul_i32 s1, s1, s8
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s1
-; GCN-IR-NEXT: s_bfe_i32 s0, s0, 0x170000
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
+; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GCN-IR-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s3, v2
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 41
@@ -519,71 +513,65 @@ define amdgpu_kernel void @s_test_srem23_64(ptr addrspace(1) %out, i64 %x, i64 %
define amdgpu_kernel void @s_test_srem24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem24_64:
; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s9, s[4:5], 0xe
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_load_dword s5, s[4:5], 0xe
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_ashr_i64 s[8:9], s[4:5], 40
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
-; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GCN-NEXT: s_ashr_i64 s[4:5], s[8:9], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GCN-NEXT: s_xor_b32 s3, s2, s4
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT: s_xor_b32 s1, s0, s8
-; GCN-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-NEXT: s_or_b32 s1, s1, 1
+; GCN-NEXT: s_ashr_i32 s3, s3, 30
+; GCN-NEXT: s_or_b32 s3, s3, 1
+; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
-; GCN-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GCN-NEXT: s_cselect_b32 s1, s1, 0
-; GCN-NEXT: v_readfirstlane_b32 s2, v2
-; GCN-NEXT: s_add_i32 s1, s2, s1
-; GCN-NEXT: s_mul_i32 s1, s1, s8
-; GCN-NEXT: s_sub_i32 s0, s0, s1
-; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
+; GCN-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GCN-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s3, v2
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem24_64:
; GCN-IR: ; %bb.0:
+; GCN-IR-NEXT: s_load_dword s9, s[4:5], 0xe
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_load_dword s5, s[4:5], 0xe
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_mov_b32 s4, s0
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 40
-; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
-; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 40
-; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s0
+; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[8:9], 40
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s2
+; GCN-IR-NEXT: s_xor_b32 s3, s2, s4
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT: s_xor_b32 s1, s0, s8
-; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
-; GCN-IR-NEXT: s_or_b32 s1, s1, 1
+; GCN-IR-NEXT: s_ashr_i32 s3, s3, 30
+; GCN-IR-NEXT: s_or_b32 s3, s3, 1
+; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0|
-; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], exec
-; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v2
-; GCN-IR-NEXT: s_add_i32 s1, s2, s1
-; GCN-IR-NEXT: s_mul_i32 s1, s1, s8
-; GCN-IR-NEXT: s_sub_i32 s0, s0, s1
-; GCN-IR-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
+; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], exec
+; GCN-IR-NEXT: s_cselect_b32 s3, s3, 0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s3, v2
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 40
@@ -651,83 +639,73 @@ define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-LABEL: s_test_srem25_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s1, s[4:5], 0xe
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 39
-; GCN-NEXT: s_abs_i32 s8, s0
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GCN-NEXT: s_abs_i32 s6, s0
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sub_i32 s2, 0, s8
+; GCN-NEXT: s_sub_i32 s2, 0, s6
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 39
+; GCN-NEXT: s_abs_i32 s5, s4
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: s_ashr_i32 s4, s4, 31
+; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_mul_lo_u32 v1, s2, v0
-; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39
-; GCN-NEXT: s_abs_i32 s3, s2
-; GCN-NEXT: s_ashr_i32 s0, s2, 31
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-NEXT: s_mul_i32 s1, s1, s8
-; GCN-NEXT: s_sub_i32 s1, s3, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: s_sub_i32 s0, s1, s0
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: v_mul_hi_u32 v0, s5, v0
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem25_64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s1, s[4:5], 0xe
-; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 39
-; GCN-IR-NEXT: s_abs_i32 s8, s0
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GCN-IR-NEXT: s_abs_i32 s6, s0
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_sub_i32 s2, 0, s8
+; GCN-IR-NEXT: s_sub_i32 s2, 0, s6
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[2:3], 39
+; GCN-IR-NEXT: s_abs_i32 s5, s4
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-IR-NEXT: s_ashr_i32 s4, s4, 31
+; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39
-; GCN-IR-NEXT: s_abs_i32 s3, s2
-; GCN-IR-NEXT: s_ashr_i32 s0, s2, 31
+; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-IR-NEXT: s_mul_i32 s1, s1, s8
-; GCN-IR-NEXT: s_sub_i32 s1, s3, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_xor_b32 s1, s1, s0
-; GCN-IR-NEXT: s_sub_i32 s0, s1, s0
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
-; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s5, v0
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 39
%2 = ashr i64 %y, 39
@@ -740,83 +718,73 @@ define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-LABEL: s_test_srem31_64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s1, s[4:5], 0xe
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 33
-; GCN-NEXT: s_abs_i32 s8, s0
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GCN-NEXT: s_abs_i32 s6, s0
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_sub_i32 s2, 0, s8
+; GCN-NEXT: s_sub_i32 s2, 0, s6
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 33
+; GCN-NEXT: s_abs_i32 s5, s4
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: s_ashr_i32 s4, s4, 31
+; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_mul_lo_u32 v1, s2, v0
-; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33
-; GCN-NEXT: s_abs_i32 s3, s2
-; GCN-NEXT: s_ashr_i32 s0, s2, 31
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-NEXT: s_mul_i32 s1, s1, s8
-; GCN-NEXT: s_sub_i32 s1, s3, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: s_sub_i32 s0, s1, s0
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: v_mul_hi_u32 v0, s5, v0
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem31_64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s1, s[4:5], 0xe
-; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 33
-; GCN-IR-NEXT: s_abs_i32 s8, s0
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
+; GCN-IR-NEXT: s_abs_i32 s6, s0
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_sub_i32 s2, 0, s8
+; GCN-IR-NEXT: s_sub_i32 s2, 0, s6
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[2:3], 33
+; GCN-IR-NEXT: s_abs_i32 s5, s4
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-IR-NEXT: s_ashr_i32 s4, s4, 31
+; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33
-; GCN-IR-NEXT: s_abs_i32 s3, s2
-; GCN-IR-NEXT: s_ashr_i32 s0, s2, 31
+; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-IR-NEXT: s_mul_i32 s1, s1, s8
-; GCN-IR-NEXT: s_sub_i32 s1, s3, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_xor_b32 s1, s1, s0
-; GCN-IR-NEXT: s_sub_i32 s0, s1, s0
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
-; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s5, v0
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s4, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 33
%2 = ashr i64 %y, 33
@@ -844,25 +812,22 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_abs_i32 s2, s3
-; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_ashr_i32 s0, s3, 31
-; GCN-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-NEXT: s_mul_i32 s1, s1, s8
-; GCN-NEXT: s_sub_i32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s8
-; GCN-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_xor_b32 s1, s1, s0
-; GCN-NEXT: s_sub_i32 s0, s1, s0
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s8, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s8, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
+; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
@@ -883,25 +848,22 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_abs_i32 s2, s3
-; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: s_mov_b32 s4, s0
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-IR-NEXT: s_mov_b32 s4, s0
; GCN-IR-NEXT: s_ashr_i32 s0, s3, 31
-; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0
-; GCN-IR-NEXT: s_mul_i32 s1, s1, s8
-; GCN-IR-NEXT: s_sub_i32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s8
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_xor_b32 s1, s1, s0
-; GCN-IR-NEXT: s_sub_i32 s0, s1, s0
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s8
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s8, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s8, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 32
@@ -1129,18 +1091,19 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-NEXT: s_mul_i32 s11, s8, s11
; GCN-IR-NEXT: s_mul_i32 s9, s9, s10
; GCN-IR-NEXT: s_mul_i32 s8, s8, s10
-; GCN-IR-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-IR-NEXT: s_add_i32 s11, s12, s11
-; GCN-IR-NEXT: s_add_i32 s11, s11, s9
-; GCN-IR-NEXT: s_sub_u32 s6, s6, s8
-; GCN-IR-NEXT: s_subb_u32 s7, s7, s11
-; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
-; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
-; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s11, v0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s9, v0
+; GCN-IR-NEXT: v_mov_b32_e32 v1, s8
+; GCN-IR-NEXT: v_mov_b32_e32 v2, s7
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s6, v1
+; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
+; GCN-IR-NEXT: v_xor_b32_e32 v1, s4, v1
+; GCN-IR-NEXT: v_xor_b32_e32 v2, s5, v0
+; GCN-IR-NEXT: v_mov_b32_e32 v3, s5
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s4, v1
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
+; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v3, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = ashr i64 %x, 31
@@ -1915,65 +1878,55 @@ define amdgpu_kernel void @s_test_srem24_k_num_i64(ptr addrspace(1) %out, i64 %x
; GCN-LABEL: s_test_srem24_k_num_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
-; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
-; GCN-NEXT: s_mov_b32 s3, 0x41c00000
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_ashr_i32 s0, s2, 30
+; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 40
+; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-NEXT: s_mov_b32 s5, 0x41c00000
+; GCN-NEXT: s_ashr_i32 s6, s4, 30
+; GCN-NEXT: s_or_b32 s8, s6, 1
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: s_or_b32 s8, s0, 1
+; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mad_f32 v2, -v1, v0, s3
+; GCN-NEXT: v_mad_f32 v2, -v1, v0, s5
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
-; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-NEXT: s_cselect_b32 s0, s8, 0
-; GCN-NEXT: v_readfirstlane_b32 s1, v1
-; GCN-NEXT: s_add_i32 s0, s1, s0
-; GCN-NEXT: s_mul_i32 s0, s0, s2
-; GCN-NEXT: s_sub_i32 s0, 24, s0
-; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v0|
+; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GCN-NEXT: s_cselect_b32 s5, s8, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s5, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem24_k_num_i64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
-; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2
-; GCN-IR-NEXT: s_mov_b32 s3, 0x41c00000
-; GCN-IR-NEXT: s_mov_b32 s4, s0
-; GCN-IR-NEXT: s_ashr_i32 s0, s2, 30
+; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[2:3], 40
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4
+; GCN-IR-NEXT: s_mov_b32 s5, 0x41c00000
+; GCN-IR-NEXT: s_ashr_i32 s6, s4, 30
+; GCN-IR-NEXT: s_or_b32 s8, s6, 1
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: s_or_b32 s8, s0, 1
+; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s3
+; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s5
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
-; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-IR-NEXT: s_cselect_b32 s0, s8, 0
-; GCN-IR-NEXT: v_readfirstlane_b32 s1, v1
-; GCN-IR-NEXT: s_add_i32 s0, s1, s0
-; GCN-IR-NEXT: s_mul_i32 s0, s0, s2
-; GCN-IR-NEXT: s_sub_i32 s0, 24, s0
-; GCN-IR-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
-; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v0|
+; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], exec
+; GCN-IR-NEXT: s_cselect_b32 s5, s8, 0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s5, v1
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%x.shr = ashr i64 %x, 40
%result = srem i64 24, %x.shr
@@ -1985,62 +1938,58 @@ define amdgpu_kernel void @s_test_srem24_k_den_i64(ptr addrspace(1) %out, i64 %x
; GCN-LABEL: s_test_srem24_k_den_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
-; GCN-NEXT: s_mov_b32 s4, s0
-; GCN-NEXT: s_ashr_i32 s0, s2, 30
-; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: s_mov_b32 s3, 0x46b6fe00
+; GCN-NEXT: s_ashr_i32 s4, s2, 30
+; GCN-NEXT: s_or_b32 s8, s4, 1
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-NEXT: v_mad_f32 v0, -v1, s8, v0
+; GCN-NEXT: v_mad_f32 v0, -v1, s3, v0
; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GCN-NEXT: s_or_b32 s3, s0, 1
-; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s8
-; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-NEXT: s_cselect_b32 s0, s3, 0
-; GCN-NEXT: v_readfirstlane_b32 s1, v1
-; GCN-NEXT: s_add_i32 s0, s1, s0
-; GCN-NEXT: s_mulk_i32 s0, 0x5b7f
-; GCN-NEXT: s_sub_i32 s0, s2, s0
-; GCN-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s3
+; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GCN-NEXT: s_cselect_b32 s3, s8, 0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, s3, v1
+; GCN-NEXT: s_movk_i32 s3, 0x5b7f
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s3
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem24_k_den_i64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2
-; GCN-IR-NEXT: s_mov_b32 s4, s0
-; GCN-IR-NEXT: s_ashr_i32 s0, s2, 30
-; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: s_mov_b32 s3, 0x46b6fe00
+; GCN-IR-NEXT: s_ashr_i32 s4, s2, 30
+; GCN-IR-NEXT: s_or_b32 s8, s4, 1
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
-; GCN-IR-NEXT: v_mad_f32 v0, -v1, s8, v0
+; GCN-IR-NEXT: v_mad_f32 v0, -v1, s3, v0
; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GCN-IR-NEXT: s_or_b32 s3, s0, 1
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s8
-; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; GCN-IR-NEXT: s_cselect_b32 s0, s3, 0
-; GCN-IR-NEXT: v_readfirstlane_b32 s1, v1
-; GCN-IR-NEXT: s_add_i32 s0, s1, s0
-; GCN-IR-NEXT: s_mulk_i32 s0, 0x5b7f
-; GCN-IR-NEXT: s_sub_i32 s0, s2, s0
-; GCN-IR-NEXT: s_bfe_i32 s0, s0, 0x180000
-; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s3
+; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
+; GCN-IR-NEXT: s_cselect_b32 s3, s8, 0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s3, v1
+; GCN-IR-NEXT: s_movk_i32 s3, 0x5b7f
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s3
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%x.shr = ashr i64 %x, 40
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 6045d423c6bad..e9da27a6f96b6 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -117,29 +117,25 @@ define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_readfirstlane_b32 s2, v1
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v0
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GFX1030-NEXT: s_sub_i32 s4, 0, s2
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX1030-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1030-NEXT: v_readfirstlane_b32 s3, v1
-; GFX1030-NEXT: s_mul_i32 s4, s4, s3
-; GFX1030-NEXT: s_mul_hi_u32 s4, s3, s4
-; GFX1030-NEXT: s_add_i32 s3, s3, s4
-; GFX1030-NEXT: s_mul_hi_u32 s3, s5, s3
-; GFX1030-NEXT: s_mul_i32 s4, s3, s2
-; GFX1030-NEXT: s_sub_i32 s4, s5, s4
-; GFX1030-NEXT: s_add_i32 s5, s3, 1
-; GFX1030-NEXT: s_sub_i32 s6, s4, s2
-; GFX1030-NEXT: s_cmp_ge_u32 s4, s2
-; GFX1030-NEXT: s_cselect_b32 s3, s5, s3
-; GFX1030-NEXT: s_cselect_b32 s4, s6, s4
-; GFX1030-NEXT: s_add_i32 s5, s3, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s4, s2
-; GFX1030-NEXT: s_cselect_b32 s2, s5, s3
-; GFX1030-NEXT: v_mov_b32_e32 v0, s2
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GFX1030-NEXT: v_sub_nc_u32_e32 v4, 0, v1
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX1030-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX1030-NEXT: v_mul_lo_u32 v4, v4, v3
+; GFX1030-NEXT: v_mul_hi_u32 v4, v3, v4
+; GFX1030-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX1030-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX1030-NEXT: v_mul_lo_u32 v4, v3, v1
+; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v4
+; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3
+; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v0, v1
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
+; GFX1030-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo
; GFX1030-NEXT: global_store_dword v2, v0, s[0:1]
; GFX1030-NEXT: s_endpgm
;
@@ -200,19 +196,16 @@ define amdgpu_kernel void @s_udiv_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; SI-NEXT: v_mul_hi_u32 v1, v0, v1
; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; SI-NEXT: v_mul_hi_u32 v0, s2, v0
-; SI-NEXT: v_readfirstlane_b32 s0, v0
-; SI-NEXT: s_mul_i32 s0, s0, s3
-; SI-NEXT: s_sub_i32 s0, s2, s0
-; SI-NEXT: s_sub_i32 s1, s0, s3
-; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; SI-NEXT: s_cmp_ge_u32 s0, s3
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT: s_cselect_b32 s0, s1, s0
-; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; SI-NEXT: s_cmp_ge_u32 s0, s3
-; SI-NEXT: s_cselect_b64 vcc, -1, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT: v_mul_lo_u32 v1, v0, s3
+; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; SI-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; SI-NEXT: v_subrev_i32_e32 v3, vcc, s3, v1
+; SI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; SI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
@@ -233,19 +226,16 @@ define amdgpu_kernel void @s_udiv_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; VI-NEXT: v_mul_hi_u32 v1, v0, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; VI-NEXT: v_mul_hi_u32 v0, s2, v0
-; VI-NEXT: v_readfirstlane_b32 s0, v0
-; VI-NEXT: s_mul_i32 s0, s0, s3
-; VI-NEXT: s_sub_i32 s0, s2, s0
-; VI-NEXT: s_sub_i32 s1, s0, s3
-; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; VI-NEXT: s_cmp_ge_u32 s0, s3
-; VI-NEXT: s_cselect_b64 vcc, -1, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; VI-NEXT: s_cselect_b32 s0, s1, s0
-; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; VI-NEXT: s_cmp_ge_u32 s0, s3
-; VI-NEXT: s_cselect_b64 vcc, -1, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; VI-NEXT: v_mul_lo_u32 v1, v0, s3
+; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; VI-NEXT: v_sub_u32_e32 v1, vcc, s2, v1
+; VI-NEXT: v_subrev_u32_e32 v3, vcc, s3, v1
+; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -262,19 +252,16 @@ define amdgpu_kernel void @s_udiv_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: s_mul_i32 s4, s4, s3
-; GCN-NEXT: s_sub_i32 s2, s2, s4
-; GCN-NEXT: s_sub_i32 s4, s2, s3
-; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s2, s3
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: s_cselect_b32 s2, s4, s2
-; GCN-NEXT: v_add_u32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s2, s3
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s3
+; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_u32_e32 v1, vcc, s2, v1
+; GCN-NEXT: v_subrev_u32_e32 v3, vcc, s3, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dword v[0:1], v2
@@ -285,28 +272,26 @@ define amdgpu_kernel void @s_udiv_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030-NEXT: v_cvt_f32_u32_e32 v0, s3
-; GFX1030-NEXT: s_sub_i32 s5, 0, s3
+; GFX1030-NEXT: s_sub_i32 s4, 0, s3
; GFX1030-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v0
-; GFX1030-NEXT: v_mov_b32_e32 v0, 0
-; GFX1030-NEXT: s_mul_i32 s5, s5, s4
-; GFX1030-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX1030-NEXT: s_add_i32 s4, s4, s5
-; GFX1030-NEXT: s_mul_hi_u32 s4, s2, s4
-; GFX1030-NEXT: s_mul_i32 s5, s4, s3
-; GFX1030-NEXT: s_sub_i32 s2, s2, s5
-; GFX1030-NEXT: s_add_i32 s5, s4, 1
-; GFX1030-NEXT: s_sub_i32 s6, s2, s3
-; GFX1030-NEXT: s_cmp_ge_u32 s2, s3
-; GFX1030-NEXT: s_cselect_b32 s4, s5, s4
-; GFX1030-NEXT: s_cselect_b32 s2, s6, s2
-; GFX1030-NEXT: s_add_i32 s5, s4, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s2, s3
-; GFX1030-NEXT: s_cselect_b32 s2, s5, s4
-; GFX1030-NEXT: v_mov_b32_e32 v1, s2
-; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX1030-NEXT: v_mul_lo_u32 v1, s4, v0
+; GFX1030-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1030-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1030-NEXT: v_mul_hi_u32 v0, s2, v0
+; GFX1030-NEXT: v_mul_lo_u32 v1, v0, s3
+; GFX1030-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030-NEXT: v_sub_nc_u32_e32 v1, s2, v1
+; GFX1030-NEXT: v_subrev_nc_u32_e32 v3, s3, v1
+; GFX1030-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1030-NEXT: v_mov_b32_e32 v3, 0
+; GFX1030-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1030-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v1
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1030-NEXT: global_store_dword v3, v0, s[0:1]
; GFX1030-NEXT: s_endpgm
;
; EG-LABEL: s_udiv_i32:
@@ -507,58 +492,50 @@ define amdgpu_kernel void @udiv_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %i
;
; GFX1030-LABEL: udiv_v2i32:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
+; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
; GFX1030-NEXT: v_mov_b32_e32 v4, 0
; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[2:3]
+; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[6:7]
; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1030-NEXT: v_readfirstlane_b32 s3, v3
-; GFX1030-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, s2
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v3, s3
-; GFX1030-NEXT: s_sub_i32 s5, 0, s2
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v3
-; GFX1030-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
-; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v3
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1030-NEXT: v_readfirstlane_b32 s8, v0
-; GFX1030-NEXT: s_mul_i32 s5, s5, s4
-; GFX1030-NEXT: s_mul_hi_u32 s5, s4, s5
-; GFX1030-NEXT: s_add_i32 s4, s4, s5
-; GFX1030-NEXT: s_mul_hi_u32 s4, s6, s4
-; GFX1030-NEXT: s_mul_i32 s5, s4, s2
-; GFX1030-NEXT: s_sub_i32 s5, s6, s5
-; GFX1030-NEXT: s_add_i32 s6, s4, 1
-; GFX1030-NEXT: s_sub_i32 s7, s5, s2
-; GFX1030-NEXT: s_cmp_ge_u32 s5, s2
-; GFX1030-NEXT: s_cselect_b32 s4, s6, s4
-; GFX1030-NEXT: s_cselect_b32 s5, s7, s5
-; GFX1030-NEXT: s_add_i32 s6, s4, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s5, s2
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v1
-; GFX1030-NEXT: s_cselect_b32 s2, s6, s4
-; GFX1030-NEXT: s_sub_i32 s4, 0, s3
-; GFX1030-NEXT: v_mov_b32_e32 v0, s2
-; GFX1030-NEXT: s_mul_i32 s4, s4, s8
-; GFX1030-NEXT: s_mul_hi_u32 s4, s8, s4
-; GFX1030-NEXT: s_add_i32 s8, s8, s4
-; GFX1030-NEXT: s_mul_hi_u32 s4, s5, s8
-; GFX1030-NEXT: s_mul_i32 s6, s4, s3
-; GFX1030-NEXT: s_sub_i32 s5, s5, s6
-; GFX1030-NEXT: s_add_i32 s6, s4, 1
-; GFX1030-NEXT: s_sub_i32 s7, s5, s3
-; GFX1030-NEXT: s_cmp_ge_u32 s5, s3
-; GFX1030-NEXT: s_cselect_b32 s4, s6, s4
-; GFX1030-NEXT: s_cselect_b32 s5, s7, s5
-; GFX1030-NEXT: s_add_i32 s6, s4, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s5, s3
-; GFX1030-NEXT: s_cselect_b32 s3, s6, s4
-; GFX1030-NEXT: v_mov_b32_e32 v1, s3
-; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v5, v2
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v6, v3
+; GFX1030-NEXT: v_sub_nc_u32_e32 v7, 0, v2
+; GFX1030-NEXT: v_sub_nc_u32_e32 v8, 0, v3
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX1030-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5
+; GFX1030-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v5, v5
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX1030-NEXT: v_mul_lo_u32 v7, v7, v5
+; GFX1030-NEXT: v_mul_lo_u32 v8, v8, v6
+; GFX1030-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX1030-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX1030-NEXT: v_add_nc_u32_e32 v5, v5, v7
+; GFX1030-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX1030-NEXT: v_mul_hi_u32 v5, v0, v5
+; GFX1030-NEXT: v_mul_hi_u32 v6, v1, v6
+; GFX1030-NEXT: v_mul_lo_u32 v7, v5, v2
+; GFX1030-NEXT: v_mul_lo_u32 v8, v6, v3
+; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v7
+; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5
+; GFX1030-NEXT: v_sub_nc_u32_e32 v1, v1, v8
+; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6
+; GFX1030-NEXT: v_sub_nc_u32_e32 v9, v0, v2
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc_lo
+; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v8, s0
+; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v5
+; GFX1030-NEXT: v_cndmask_b32_e64 v1, v1, v7, s0
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2
+; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v6
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc_lo
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc_lo
+; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5]
; GFX1030-NEXT: s_endpgm
;
; EG-LABEL: udiv_v2i32:
@@ -904,107 +881,91 @@ define amdgpu_kernel void @udiv_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %i
;
; GFX1030-LABEL: udiv_v4i32:
; GFX1030: ; %bb.0:
-; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
+; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x0
; GFX1030-NEXT: v_mov_b32_e32 v8, 0
; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030-NEXT: s_clause 0x1
-; GFX1030-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] offset:16
-; GFX1030-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3]
+; GFX1030-NEXT: global_load_dwordx4 v[0:3], v8, s[6:7] offset:16
+; GFX1030-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7]
; GFX1030-NEXT: s_waitcnt vmcnt(1)
-; GFX1030-NEXT: v_readfirstlane_b32 s2, v0
-; GFX1030-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v9, v0
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v10, v1
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v12, v3
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v11, v2
+; GFX1030-NEXT: v_sub_nc_u32_e32 v13, 0, v0
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v9, v9
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v10, v10
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v12, v12
+; GFX1030-NEXT: v_rcp_iflag_f32_e32 v11, v11
+; GFX1030-NEXT: v_sub_nc_u32_e32 v14, 0, v1
+; GFX1030-NEXT: v_sub_nc_u32_e32 v16, 0, v3
+; GFX1030-NEXT: v_sub_nc_u32_e32 v15, 0, v2
+; GFX1030-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX1030-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10
+; GFX1030-NEXT: v_mul_f32_e32 v12, 0x4f7ffffe, v12
+; GFX1030-NEXT: v_mul_f32_e32 v11, 0x4f7ffffe, v11
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v9, v9
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v12, v12
+; GFX1030-NEXT: v_cvt_u32_f32_e32 v11, v11
+; GFX1030-NEXT: v_mul_lo_u32 v13, v13, v9
+; GFX1030-NEXT: v_mul_lo_u32 v14, v14, v10
+; GFX1030-NEXT: v_mul_lo_u32 v16, v16, v12
+; GFX1030-NEXT: v_mul_lo_u32 v15, v15, v11
+; GFX1030-NEXT: v_mul_hi_u32 v13, v9, v13
+; GFX1030-NEXT: v_mul_hi_u32 v14, v10, v14
+; GFX1030-NEXT: v_mul_hi_u32 v16, v12, v16
+; GFX1030-NEXT: v_mul_hi_u32 v15, v11, v15
+; GFX1030-NEXT: v_add_nc_u32_e32 v9, v9, v13
+; GFX1030-NEXT: v_add_nc_u32_e32 v10, v10, v14
+; GFX1030-NEXT: v_add_nc_u32_e32 v12, v12, v16
+; GFX1030-NEXT: v_add_nc_u32_e32 v11, v11, v15
; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_readfirstlane_b32 s7, v4
-; GFX1030-NEXT: v_readfirstlane_b32 s5, v2
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v0, s2
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s3
-; GFX1030-NEXT: s_sub_i32 s6, 0, s2
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX1030-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v0
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v0, s5
-; GFX1030-NEXT: v_readfirstlane_b32 s9, v1
-; GFX1030-NEXT: s_mul_i32 s6, s6, s4
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX1030-NEXT: s_mul_hi_u32 s6, s4, s6
-; GFX1030-NEXT: s_add_i32 s4, s4, s6
-; GFX1030-NEXT: s_mul_hi_u32 s4, s7, s4
-; GFX1030-NEXT: s_mul_i32 s6, s4, s2
-; GFX1030-NEXT: s_sub_i32 s6, s7, s6
-; GFX1030-NEXT: s_add_i32 s7, s4, 1
-; GFX1030-NEXT: s_sub_i32 s8, s6, s2
-; GFX1030-NEXT: s_cmp_ge_u32 s6, s2
-; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX1030-NEXT: s_cselect_b32 s4, s7, s4
-; GFX1030-NEXT: s_cselect_b32 s6, s8, s6
-; GFX1030-NEXT: s_add_i32 s7, s4, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s6, s2
-; GFX1030-NEXT: v_readfirstlane_b32 s2, v3
-; GFX1030-NEXT: s_cselect_b32 s4, s7, s4
-; GFX1030-NEXT: s_sub_i32 s6, 0, s3
-; GFX1030-NEXT: v_readfirstlane_b32 s7, v5
-; GFX1030-NEXT: s_mul_i32 s6, s6, s9
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030-NEXT: s_mul_hi_u32 s6, s9, s6
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GFX1030-NEXT: s_add_i32 s9, s9, s6
-; GFX1030-NEXT: s_mul_hi_u32 s6, s7, s9
-; GFX1030-NEXT: v_readfirstlane_b32 s10, v0
-; GFX1030-NEXT: s_mul_i32 s8, s6, s3
-; GFX1030-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; GFX1030-NEXT: s_sub_i32 s7, s7, s8
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_sub_i32 s9, s7, s3
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s3
-; GFX1030-NEXT: s_cselect_b32 s6, s8, s6
-; GFX1030-NEXT: s_cselect_b32 s7, s9, s7
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s3
-; GFX1030-NEXT: v_readfirstlane_b32 s7, v6
-; GFX1030-NEXT: s_cselect_b32 s3, s8, s6
-; GFX1030-NEXT: s_sub_i32 s6, 0, s5
-; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v1
-; GFX1030-NEXT: s_mul_i32 s6, s6, s10
-; GFX1030-NEXT: v_mov_b32_e32 v1, s3
-; GFX1030-NEXT: s_mul_hi_u32 s6, s10, s6
-; GFX1030-NEXT: s_add_i32 s10, s10, s6
-; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1030-NEXT: s_mul_hi_u32 s6, s7, s10
-; GFX1030-NEXT: s_mul_i32 s8, s6, s5
-; GFX1030-NEXT: s_sub_i32 s7, s7, s8
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_sub_i32 s9, s7, s5
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s5
-; GFX1030-NEXT: v_readfirstlane_b32 s10, v0
-; GFX1030-NEXT: s_cselect_b32 s6, s8, s6
-; GFX1030-NEXT: s_cselect_b32 s7, s9, s7
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s5
-; GFX1030-NEXT: v_readfirstlane_b32 s7, v7
-; GFX1030-NEXT: s_cselect_b32 s5, s8, s6
-; GFX1030-NEXT: s_sub_i32 s6, 0, s2
-; GFX1030-NEXT: v_mov_b32_e32 v0, s4
-; GFX1030-NEXT: s_mul_i32 s6, s6, s10
-; GFX1030-NEXT: v_mov_b32_e32 v2, s5
-; GFX1030-NEXT: s_mul_hi_u32 s6, s10, s6
-; GFX1030-NEXT: s_add_i32 s10, s10, s6
-; GFX1030-NEXT: s_mul_hi_u32 s6, s7, s10
-; GFX1030-NEXT: s_mul_i32 s8, s6, s2
-; GFX1030-NEXT: s_sub_i32 s7, s7, s8
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_sub_i32 s9, s7, s2
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s2
-; GFX1030-NEXT: s_cselect_b32 s6, s8, s6
-; GFX1030-NEXT: s_cselect_b32 s7, s9, s7
-; GFX1030-NEXT: s_add_i32 s8, s6, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s7, s2
-; GFX1030-NEXT: s_cselect_b32 s2, s8, s6
-; GFX1030-NEXT: v_mov_b32_e32 v3, s2
-; GFX1030-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
+; GFX1030-NEXT: v_mul_hi_u32 v9, v4, v9
+; GFX1030-NEXT: v_mul_hi_u32 v10, v5, v10
+; GFX1030-NEXT: v_mul_hi_u32 v12, v7, v12
+; GFX1030-NEXT: v_mul_hi_u32 v11, v6, v11
+; GFX1030-NEXT: v_mul_lo_u32 v13, v9, v0
+; GFX1030-NEXT: v_mul_lo_u32 v14, v10, v1
+; GFX1030-NEXT: v_mul_lo_u32 v16, v12, v3
+; GFX1030-NEXT: v_mul_lo_u32 v15, v11, v2
+; GFX1030-NEXT: v_add_nc_u32_e32 v17, 1, v9
+; GFX1030-NEXT: v_add_nc_u32_e32 v18, 1, v10
+; GFX1030-NEXT: v_add_nc_u32_e32 v19, 1, v11
+; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v13
+; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v5, v14
+; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v7, v16
+; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12
+; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v6, v15
+; GFX1030-NEXT: v_sub_nc_u32_e32 v14, v4, v0
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0
+; GFX1030-NEXT: v_sub_nc_u32_e32 v15, v5, v1
+; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v5, v1
+; GFX1030-NEXT: v_cmp_ge_u32_e64 s2, v7, v3
+; GFX1030-NEXT: v_sub_nc_u32_e32 v16, v6, v2
+; GFX1030-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
+; GFX1030-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
+; GFX1030-NEXT: v_cndmask_b32_e64 v10, v10, v18, s0
+; GFX1030-NEXT: v_cmp_ge_u32_e64 s1, v6, v2
+; GFX1030-NEXT: v_cndmask_b32_e64 v12, v12, v13, s2
+; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v9
+; GFX1030-NEXT: v_cndmask_b32_e64 v5, v5, v15, s0
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0
+; GFX1030-NEXT: v_cndmask_b32_e64 v11, v11, v19, s1
+; GFX1030-NEXT: v_sub_nc_u32_e32 v17, v7, v3
+; GFX1030-NEXT: v_add_nc_u32_e32 v14, 1, v10
+; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v16, s1
+; GFX1030-NEXT: v_cndmask_b32_e32 v0, v9, v13, vcc_lo
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v1
+; GFX1030-NEXT: v_add_nc_u32_e32 v15, 1, v11
+; GFX1030-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
+; GFX1030-NEXT: v_add_nc_u32_e32 v16, 1, v12
+; GFX1030-NEXT: v_cndmask_b32_e32 v1, v10, v14, vcc_lo
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v6, v2
+; GFX1030-NEXT: v_cndmask_b32_e32 v2, v11, v15, vcc_lo
+; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v7, v3
+; GFX1030-NEXT: v_cndmask_b32_e32 v3, v12, v16, vcc_lo
+; GFX1030-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5]
; GFX1030-NEXT: s_endpgm
;
; EG-LABEL: udiv_v4i32:
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index 5acbb044c1057..889e0915b0e16 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -514,19 +514,16 @@ define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_mul_i32 s0, s0, s8
-; GCN-NEXT: s_sub_i32 s0, s3, s0
-; GCN-NEXT: s_sub_i32 s1, s0, s8
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s8
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s3, v1
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
@@ -550,19 +547,16 @@ define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64
; GCN-IR-NEXT: s_mov_b32 s5, s1
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0
-; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
-; GCN-IR-NEXT: s_sub_i32 s0, s3, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
-; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v0, s8
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s3, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
@@ -595,19 +589,16 @@ define amdgpu_kernel void @s_test_udiv31_i64(ptr addrspace(1) %out, i64 %x, i64
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
; GCN-NEXT: s_mov_b32 s5, s1
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_mul_i32 s0, s0, s8
-; GCN-NEXT: s_sub_i32 s0, s2, s0
-; GCN-NEXT: s_sub_i32 s1, s0, s8
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_mul_lo_u32 v1, v0, s8
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm
@@ -633,19 +624,16 @@ define amdgpu_kernel void @s_test_udiv31_i64(ptr addrspace(1) %out, i64 %x, i64
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
; GCN-IR-NEXT: s_mov_b32 s5, s1
-; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
-; GCN-IR-NEXT: s_sub_i32 s0, s2, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
-; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
-; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v0, s8
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll
index a56346f3bb45b..a23d99bcf3b9f 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll
@@ -54,25 +54,21 @@ define amdgpu_kernel void @test_udivrem(ptr addrspace(1) %out0, [8 x i32], ptr a
; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT: v_readfirstlane_b32 s10, v0
-; GFX6-NEXT: s_mul_i32 s10, s10, s8
-; GFX6-NEXT: s_sub_i32 s9, s9, s10
-; GFX6-NEXT: s_sub_i32 s10, s9, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s9, s8
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: s_cselect_b32 s9, s10, s9
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_sub_i32 s10, s9, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v0
-; GFX6-NEXT: s_cmp_ge_u32 s9, s8
-; GFX6-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; GFX6-NEXT: s_cselect_b32 s8, s10, s9
+; GFX6-NEXT: v_mul_lo_u32 v1, v0, s8
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_waitcnt expcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
@@ -80,6 +76,7 @@ define amdgpu_kernel void @test_udivrem(ptr addrspace(1) %out0, [8 x i32], ptr a
; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dword s6, s[4:5], 0x98
; GFX8-NEXT: s_load_dword s7, s[4:5], 0x74
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x4c
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX8-NEXT: s_sub_i32 s0, 0, s6
@@ -88,33 +85,28 @@ define amdgpu_kernel void @test_udivrem(ptr addrspace(1) %out0, [8 x i32], ptr a
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x4c
; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_mul_hi_u32 v4, s7, v0
+; GFX8-NEXT: v_mul_hi_u32 v2, s7, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
-; GFX8-NEXT: v_readfirstlane_b32 s0, v4
-; GFX8-NEXT: s_mul_i32 s0, s0, s6
-; GFX8-NEXT: s_sub_i32 s0, s7, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s6
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4
-; GFX8-NEXT: s_cmp_ge_u32 s0, s6
-; GFX8-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX8-NEXT: s_sub_i32 s1, s0, s6
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4
-; GFX8-NEXT: s_cmp_ge_u32 s0, s6
-; GFX8-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: flat_store_dword v[0:1], v4
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: flat_store_dword v[2:3], v0
+; GFX8-NEXT: v_mul_lo_u32 v3, v2, s6
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s6, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s6, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
%result0 = udiv i32 %x, %y
store i32 %result0, ptr addrspace(1) %out0
@@ -169,44 +161,40 @@ define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x,
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX6-NEXT: s_sub_i32 s6, 0, s2
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s6, v0
-; GFX6-NEXT: s_mul_i32 s6, s6, s2
-; GFX6-NEXT: s_sub_i32 s0, s0, s6
-; GFX6-NEXT: s_sub_i32 s6, s0, s2
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b32 s0, s6, s0
-; GFX6-NEXT: s_sub_i32 s6, s0, s2
-; GFX6-NEXT: s_cmp_ge_u32 s0, s2
-; GFX6-NEXT: s_cselect_b32 s0, s6, s0
-; GFX6-NEXT: s_sub_i32 s2, 0, s3
-; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, s6, v0
+; GFX6-NEXT: s_sub_i32 s6, 0, s3
+; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX6-NEXT: s_mov_b32 s6, -1
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT: v_readfirstlane_b32 s2, v0
-; GFX6-NEXT: s_mul_i32 s2, s2, s3
-; GFX6-NEXT: s_sub_i32 s1, s1, s2
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: s_sub_i32 s2, s1, s3
-; GFX6-NEXT: s_cmp_ge_u32 s1, s3
-; GFX6-NEXT: s_cselect_b32 s1, s2, s1
-; GFX6-NEXT: v_mov_b32_e32 v0, s0
-; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
@@ -216,45 +204,41 @@ define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x,
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX8-NEXT: s_sub_i32 s6, 0, s2
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s3
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s6, v0
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_lo_u32 v2, s6, v0
+; GFX8-NEXT: s_sub_i32 s6, 0, s3
+; GFX8-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
+; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, s1, v1
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, s2
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, s3
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s1, v1
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s2, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s3, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s2, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s2, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v2, s4
-; GFX8-NEXT: v_readfirstlane_b32 s6, v0
-; GFX8-NEXT: s_mul_i32 s6, s6, s2
-; GFX8-NEXT: s_sub_i32 s0, s0, s6
-; GFX8-NEXT: s_sub_i32 s6, s0, s2
-; GFX8-NEXT: s_cmp_ge_u32 s0, s2
-; GFX8-NEXT: s_cselect_b32 s0, s6, s0
-; GFX8-NEXT: s_sub_i32 s6, s0, s2
-; GFX8-NEXT: s_cmp_ge_u32 s0, s2
-; GFX8-NEXT: s_cselect_b32 s0, s6, s0
-; GFX8-NEXT: s_sub_i32 s2, 0, s3
-; GFX8-NEXT: v_mul_lo_u32 v0, s2, v1
; GFX8-NEXT: v_mov_b32_e32 v3, s5
-; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
-; GFX8-NEXT: v_mul_hi_u32 v1, s1, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s0
-; GFX8-NEXT: v_readfirstlane_b32 s0, v1
-; GFX8-NEXT: s_mul_i32 s0, s0, s3
-; GFX8-NEXT: s_sub_i32 s0, s1, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s3
-; GFX8-NEXT: s_cmp_ge_u32 s0, s3
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s3
-; GFX8-NEXT: s_cmp_ge_u32 s0, s3
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
%result0 = udiv <2 x i32> %x, %y
@@ -338,82 +322,74 @@ define amdgpu_kernel void @test_udivrem_v4(ptr addrspace(1) %out, <4 x i32> %x,
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX6-NEXT: s_sub_i32 s0, 0, s12
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13
+; GFX6-NEXT: s_sub_i32 s1, 0, s13
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s14
+; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s15
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0
-; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s14
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s12
-; GFX6-NEXT: s_sub_i32 s0, s8, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s12
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s12
-; GFX6-NEXT: s_cmp_ge_u32 s0, s12
-; GFX6-NEXT: s_cselect_b32 s6, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s13
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s15
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s13
-; GFX6-NEXT: s_sub_i32 s0, s9, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s13
-; GFX6-NEXT: s_cmp_ge_u32 s0, s13
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s13
-; GFX6-NEXT: s_cmp_ge_u32 s0, s13
-; GFX6-NEXT: s_cselect_b32 s7, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s14
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT: v_readfirstlane_b32 s0, v0
-; GFX6-NEXT: s_mul_i32 s0, s0, s14
-; GFX6-NEXT: s_sub_i32 s0, s10, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s14
-; GFX6-NEXT: s_cmp_ge_u32 s0, s14
-; GFX6-NEXT: s_cselect_b32 s0, s1, s0
-; GFX6-NEXT: s_sub_i32 s1, s0, s14
-; GFX6-NEXT: s_cmp_ge_u32 s0, s14
-; GFX6-NEXT: s_cselect_b32 s8, s1, s0
-; GFX6-NEXT: s_sub_i32 s0, 0, s15
-; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT: v_mul_lo_u32 v4, s1, v1
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT: v_mul_hi_u32 v2, s11, v0
-; GFX6-NEXT: v_mov_b32_e32 v0, s6
-; GFX6-NEXT: v_mov_b32_e32 v1, s7
-; GFX6-NEXT: v_readfirstlane_b32 s4, v2
-; GFX6-NEXT: s_mul_i32 s4, s4, s15
-; GFX6-NEXT: s_sub_i32 s4, s11, s4
-; GFX6-NEXT: s_sub_i32 s5, s4, s15
-; GFX6-NEXT: s_cmp_ge_u32 s4, s15
-; GFX6-NEXT: s_cselect_b32 s4, s5, s4
-; GFX6-NEXT: s_sub_i32 s5, s4, s15
-; GFX6-NEXT: s_cmp_ge_u32 s4, s15
-; GFX6-NEXT: s_cselect_b32 s4, s5, s4
-; GFX6-NEXT: v_mov_b32_e32 v2, s8
-; GFX6-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT: s_sub_i32 s4, 0, s14
+; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GFX6-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT: v_mul_lo_u32 v3, s4, v2
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s9, v1
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX6-NEXT: s_sub_i32 s4, 0, s15
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
+; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s13, v1
+; GFX6-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX6-NEXT: v_mul_lo_u32 v5, s4, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v2, s14
+; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GFX6-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s14, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX6-NEXT: v_mul_lo_u32 v3, v3, s15
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s14, v2
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s11, v3
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s15, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s15, v3
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
@@ -423,85 +399,77 @@ define amdgpu_kernel void @test_udivrem_v4(ptr addrspace(1) %out, <4 x i32> %x,
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s12
+; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX8-NEXT: s_sub_i32 s0, 0, s12
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s13
+; GFX8-NEXT: s_sub_i32 s1, 0, s13
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT: v_cvt_f32_u32_e32 v3, s14
+; GFX8-NEXT: s_sub_i32 s2, 0, s14
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0
-; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s14
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: s_mul_i32 s0, s0, s12
-; GFX8-NEXT: s_sub_i32 s0, s8, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s12
-; GFX8-NEXT: s_cmp_ge_u32 s0, s12
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s12
-; GFX8-NEXT: s_cmp_ge_u32 s0, s12
-; GFX8-NEXT: s_cselect_b32 s2, s1, s0
-; GFX8-NEXT: s_sub_i32 s0, 0, s13
-; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
-; GFX8-NEXT: v_mul_hi_u32 v0, s9, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s15
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: s_mul_i32 s0, s0, s13
-; GFX8-NEXT: s_sub_i32 s0, s9, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s13
-; GFX8-NEXT: s_cmp_ge_u32 s0, s13
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s13
-; GFX8-NEXT: s_cmp_ge_u32 s0, s13
-; GFX8-NEXT: s_cselect_b32 s3, s1, s0
-; GFX8-NEXT: s_sub_i32 s0, 0, s14
-; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
-; GFX8-NEXT: v_mul_hi_u32 v0, s10, v0
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT: v_readfirstlane_b32 s0, v0
-; GFX8-NEXT: s_mul_i32 s0, s0, s14
-; GFX8-NEXT: s_sub_i32 s0, s10, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s14
-; GFX8-NEXT: s_cmp_ge_u32 s0, s14
-; GFX8-NEXT: s_cselect_b32 s0, s1, s0
-; GFX8-NEXT: s_sub_i32 s1, s0, s14
-; GFX8-NEXT: s_cmp_ge_u32 s0, s14
-; GFX8-NEXT: s_cselect_b32 s6, s1, s0
-; GFX8-NEXT: s_sub_i32 s0, 0, s15
-; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX8-NEXT: v_mul_lo_u32 v2, s0, v0
+; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s15
+; GFX8-NEXT: v_mul_lo_u32 v4, s1, v1
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
+; GFX8-NEXT: v_mul_hi_u32 v1, s9, v1
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, s12
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v3
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, s13
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s8, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s12, v0
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s9, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s12, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX8-NEXT: v_mul_lo_u32 v3, s2, v2
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s13, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX8-NEXT: v_mul_hi_u32 v3, v2, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v5
+; GFX8-NEXT: s_sub_i32 s2, 0, s15
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v4
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s13, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, s10, v2
+; GFX8-NEXT: v_mul_lo_u32 v5, s2, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX8-NEXT: v_mul_lo_u32 v2, v2, s14
+; GFX8-NEXT: v_mul_hi_u32 v4, v3, v5
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s10, v2
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
+; GFX8-NEXT: v_mul_hi_u32 v3, s11, v3
+; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s14, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX8-NEXT: v_mul_lo_u32 v3, v3, s15
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s14, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s14, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s11, v3
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s15, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s15, v3
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s15, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
-; GFX8-NEXT: v_mul_hi_u32 v3, s11, v0
-; GFX8-NEXT: v_mov_b32_e32 v0, s2
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_readfirstlane_b32 s2, v3
-; GFX8-NEXT: s_mul_i32 s2, s2, s15
-; GFX8-NEXT: s_sub_i32 s2, s11, s2
-; GFX8-NEXT: s_sub_i32 s3, s2, s15
-; GFX8-NEXT: s_cmp_ge_u32 s2, s15
-; GFX8-NEXT: s_cselect_b32 s2, s3, s2
-; GFX8-NEXT: s_sub_i32 s3, s2, s15
-; GFX8-NEXT: s_cmp_ge_u32 s2, s15
-; GFX8-NEXT: s_cselect_b32 s2, s3, s2
-; GFX8-NEXT: v_mov_b32_e32 v3, s2
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
%result0 = udiv <4 x i32> %x, %y
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index 94f1b83ea2765..c12f2be8f144b 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -414,71 +414,63 @@ define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64
; GCN-LABEL: s_test_urem31_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
-; GCN-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s8, s0, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-NEXT: s_sub_i32 s0, 0, s8
+; GCN-NEXT: s_lshr_b32 s6, s0, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-NEXT: s_sub_i32 s0, 0, s6
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v1, s0, v0
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s2, s3, 1
-; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
+; GCN-NEXT: s_lshr_b32 s4, s3, 1
+; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_mul_i32 s0, s0, s8
-; GCN-NEXT: s_sub_i32 s0, s2, s0
-; GCN-NEXT: s_sub_i32 s1, s0, s8
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-NEXT: s_sub_i32 s1, s0, s8
-; GCN-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_urem31_i64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
-; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s8, s0, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
-; GCN-IR-NEXT: s_sub_i32 s0, 0, s8
+; GCN-IR-NEXT: s_lshr_b32 s6, s0, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v0
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1
-; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_mov_b32 s2, -1
+; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
+; GCN-IR-NEXT: s_lshr_b32 s4, s3, 1
+; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
-; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
-; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
-; GCN-IR-NEXT: s_sub_i32 s0, s2, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
-; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
-; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
-; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
%1 = lshr i64 %x, 33
%2 = lshr i64 %y, 33
@@ -492,53 +484,49 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64>
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s0, s13, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT: s_sub_i32 s1, 0, s0
-; GCN-NEXT: s_lshr_b32 s6, s15, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GCN-NEXT: s_lshr_b32 s6, s13, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-NEXT: s_lshr_b32 s7, s15, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GCN-NEXT: s_sub_i32 s0, 0, s6
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: s_lshr_b32 s7, s11, 1
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: s_lshr_b32 s9, s9, 1
+; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-NEXT: s_lshr_b32 s8, s11, 1
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s1, v0
-; GCN-NEXT: s_lshr_b32 s1, s9, 1
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s2, s2, s0
-; GCN-NEXT: s_sub_i32 s1, s1, s2
-; GCN-NEXT: s_sub_i32 s2, s1, s0
-; GCN-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s0
-; GCN-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-NEXT: s_cselect_b32 s8, s2, s1
-; GCN-NEXT: s_sub_i32 s0, 0, s6
-; GCN-NEXT: v_mul_lo_u32 v0, s0, v1
+; GCN-NEXT: v_mul_lo_u32 v2, s0, v0
+; GCN-NEXT: s_sub_i32 s0, 0, s7
+; GCN-NEXT: v_mul_lo_u32 v3, s0, v1
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_hi_u32 v0, v1, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v2, s7, v0
+; GCN-NEXT: v_mul_hi_u32 v2, v0, v2
+; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
+; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GCN-NEXT: v_mul_hi_u32 v1, s8, v1
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_mul_lo_u32 v1, v1, s7
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s9, v0
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GCN-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-NEXT: s_mul_i32 s4, s4, s6
-; GCN-NEXT: s_sub_i32 s4, s7, s4
-; GCN-NEXT: s_sub_i32 s5, s4, s6
-; GCN-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-NEXT: s_sub_i32 s5, s4, s6
-; GCN-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
@@ -547,53 +535,49 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64>
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s0, s13, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT: s_sub_i32 s1, 0, s0
-; GCN-IR-NEXT: s_lshr_b32 s6, s15, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s6
+; GCN-IR-NEXT: s_lshr_b32 s6, s13, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-IR-NEXT: s_lshr_b32 s7, s15, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s7
+; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-IR-NEXT: s_lshr_b32 s9, s9, 1
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GCN-IR-NEXT: s_lshr_b32 s8, s11, 1
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-IR-NEXT: v_mul_lo_u32 v1, s1, v0
-; GCN-IR-NEXT: s_lshr_b32 s1, s9, 1
-; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
+; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-IR-NEXT: s_mul_i32 s2, s2, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s1, s2
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-IR-NEXT: s_cselect_b32 s8, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
-; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v1
+; GCN-IR-NEXT: v_mul_lo_u32 v2, s0, v0
+; GCN-IR-NEXT: s_sub_i32 s0, 0, s7
+; GCN-IR-NEXT: v_mul_lo_u32 v3, s0, v1
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-IR-NEXT: v_mul_hi_u32 v2, s7, v0
+; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, v2
+; GCN-IR-NEXT: v_mul_hi_u32 v3, v1, v3
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s9, v0
+; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3
+; GCN-IR-NEXT: v_mul_hi_u32 v1, s8, v1
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, s7
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s9, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
+; GCN-IR-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
+; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v1, v2, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
-; GCN-IR-NEXT: v_readfirstlane_b32 s4, v2
-; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
-; GCN-IR-NEXT: s_sub_i32 s4, s7, s4
-; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
-; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
-; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-IR-NEXT: v_mov_b32_e32 v2, s4
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
@@ -671,40 +655,38 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b32 s6, s13, 1
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-NEXT: s_lshr_b32 s0, s15, 9
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s0
-; GCN-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-NEXT: s_sub_i32 s0, 0, s6
+; GCN-NEXT: s_lshr_b32 s8, s15, 9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s8
; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-NEXT: v_cvt_f32_u32_e32 v3, s7
-; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-NEXT: s_sub_i32 s1, 0, s6
+; GCN-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
-; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
-; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GCN-NEXT: s_lshr_b32 s8, s9, 1
-; GCN-NEXT: v_mul_hi_u32 v5, v0, v5
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v2, v2, s0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; GCN-NEXT: v_mul_hi_u32 v0, s8, v0
+; GCN-NEXT: v_mul_f32_e32 v5, v4, v5
+; GCN-NEXT: v_mul_lo_u32 v3, s0, v0
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-NEXT: v_mul_hi_u32 v3, v0, v3
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
+; GCN-NEXT: v_trunc_f32_e32 v3, v5
+; GCN-NEXT: v_mad_f32 v4, -v3, v2, v4
+; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s8
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-NEXT: s_mul_i32 s4, s4, s6
-; GCN-NEXT: s_sub_i32 s4, s8, s4
-; GCN-NEXT: s_sub_i32 s5, s4, s6
-; GCN-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-NEXT: s_sub_i32 s5, s4, s6
-; GCN-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-NEXT: s_cselect_b32 s4, s5, s4
; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
-; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
@@ -719,40 +701,38 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_lshr_b32 s6, s13, 1
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
-; GCN-IR-NEXT: s_lshr_b32 s0, s15, 9
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s0
-; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
+; GCN-IR-NEXT: s_lshr_b32 s8, s15, 9
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s8
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s7
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2
-; GCN-IR-NEXT: s_sub_i32 s1, 0, s6
+; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v5, v2
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4
-; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
-; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3
-; GCN-IR-NEXT: v_mul_lo_u32 v5, s1, v0
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v4
-; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GCN-IR-NEXT: s_lshr_b32 s8, s9, 1
-; GCN-IR-NEXT: v_mul_hi_u32 v5, v0, v5
-; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
-; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s0
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v5
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s8, v0
+; GCN-IR-NEXT: v_mul_f32_e32 v5, v4, v5
+; GCN-IR-NEXT: v_mul_lo_u32 v3, s0, v0
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1
+; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v3
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
+; GCN-IR-NEXT: v_trunc_f32_e32 v3, v5
+; GCN-IR-NEXT: v_mad_f32 v4, -v3, v2, v4
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc
+; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s8
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GCN-IR-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
+; GCN-IR-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
-; GCN-IR-NEXT: v_readfirstlane_b32 s4, v0
-; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
-; GCN-IR-NEXT: s_sub_i32 s4, s8, s4
-; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
-; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
-; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
-; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll
index baf9e9df91689..2966cc26c945c 100644
--- a/llvm/test/CodeGen/AMDGPU/wave32.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave32.ll
@@ -741,8 +741,8 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1032-NEXT: ; %bb.1:
; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX1032-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GFX1032-NEXT: s_sub_u32 s9, 0, s4
-; GFX1032-NEXT: s_subb_u32 s10, 0, s5
+; GFX1032-NEXT: s_sub_u32 s0, 0, s4
+; GFX1032-NEXT: s_subb_u32 s1, 0, s5
; GFX1032-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
; GFX1032-NEXT: v_rcp_f32_e32 v0, v0
; GFX1032-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -751,137 +751,121 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1032-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX1032-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1032-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1032-NEXT: v_readfirstlane_b32 s0, v1
-; GFX1032-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1032-NEXT: s_mul_i32 s11, s9, s0
-; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s1
-; GFX1032-NEXT: s_mul_i32 s12, s10, s1
-; GFX1032-NEXT: s_add_i32 s11, s13, s11
-; GFX1032-NEXT: s_mul_i32 s14, s9, s1
-; GFX1032-NEXT: s_add_i32 s11, s11, s12
-; GFX1032-NEXT: s_mul_hi_u32 s13, s1, s14
-; GFX1032-NEXT: s_mul_hi_u32 s15, s0, s14
-; GFX1032-NEXT: s_mul_i32 s12, s0, s14
-; GFX1032-NEXT: s_mul_hi_u32 s14, s1, s11
-; GFX1032-NEXT: s_mul_i32 s1, s1, s11
-; GFX1032-NEXT: s_mul_hi_u32 s16, s0, s11
-; GFX1032-NEXT: s_add_u32 s1, s13, s1
-; GFX1032-NEXT: s_addc_u32 s13, 0, s14
-; GFX1032-NEXT: s_add_u32 s1, s1, s12
-; GFX1032-NEXT: s_mul_i32 s11, s0, s11
-; GFX1032-NEXT: s_addc_u32 s1, s13, s15
-; GFX1032-NEXT: s_addc_u32 s12, s16, 0
-; GFX1032-NEXT: s_add_u32 s1, s1, s11
-; GFX1032-NEXT: s_addc_u32 s11, 0, s12
-; GFX1032-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1032-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1032-NEXT: s_addc_u32 s0, s0, s11
-; GFX1032-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1032-NEXT: s_mul_i32 s11, s9, s0
-; GFX1032-NEXT: s_mul_hi_u32 s12, s9, s1
-; GFX1032-NEXT: s_mul_i32 s10, s10, s1
-; GFX1032-NEXT: s_add_i32 s11, s12, s11
-; GFX1032-NEXT: s_mul_i32 s9, s9, s1
-; GFX1032-NEXT: s_add_i32 s11, s11, s10
-; GFX1032-NEXT: s_mul_hi_u32 s12, s0, s9
-; GFX1032-NEXT: s_mul_i32 s13, s0, s9
-; GFX1032-NEXT: s_mul_hi_u32 s9, s1, s9
-; GFX1032-NEXT: s_mul_hi_u32 s14, s1, s11
-; GFX1032-NEXT: s_mul_i32 s1, s1, s11
-; GFX1032-NEXT: s_mul_hi_u32 s10, s0, s11
-; GFX1032-NEXT: s_add_u32 s1, s9, s1
-; GFX1032-NEXT: s_addc_u32 s9, 0, s14
-; GFX1032-NEXT: s_add_u32 s1, s1, s13
-; GFX1032-NEXT: s_mul_i32 s11, s0, s11
-; GFX1032-NEXT: s_addc_u32 s1, s9, s12
-; GFX1032-NEXT: s_addc_u32 s9, s10, 0
-; GFX1032-NEXT: s_add_u32 s1, s1, s11
-; GFX1032-NEXT: s_addc_u32 s9, 0, s9
-; GFX1032-NEXT: v_add_co_u32 v0, s1, v0, s1
-; GFX1032-NEXT: s_cmp_lg_u32 s1, 0
-; GFX1032-NEXT: s_addc_u32 s0, s0, s9
-; GFX1032-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1032-NEXT: s_mul_i32 s10, s6, s0
-; GFX1032-NEXT: s_mul_hi_u32 s9, s6, s0
-; GFX1032-NEXT: s_mul_hi_u32 s11, s7, s0
-; GFX1032-NEXT: s_mul_i32 s0, s7, s0
-; GFX1032-NEXT: s_mul_hi_u32 s12, s6, s1
-; GFX1032-NEXT: s_mul_hi_u32 s13, s7, s1
-; GFX1032-NEXT: s_mul_i32 s1, s7, s1
-; GFX1032-NEXT: s_add_u32 s10, s12, s10
-; GFX1032-NEXT: s_addc_u32 s9, 0, s9
-; GFX1032-NEXT: s_add_u32 s1, s10, s1
-; GFX1032-NEXT: s_addc_u32 s1, s9, s13
-; GFX1032-NEXT: s_addc_u32 s9, s11, 0
-; GFX1032-NEXT: s_add_u32 s1, s1, s0
-; GFX1032-NEXT: s_addc_u32 s9, 0, s9
-; GFX1032-NEXT: s_mul_hi_u32 s0, s4, s1
-; GFX1032-NEXT: s_mul_i32 s11, s4, s9
-; GFX1032-NEXT: s_mul_i32 s12, s4, s1
-; GFX1032-NEXT: s_add_i32 s0, s0, s11
-; GFX1032-NEXT: v_sub_co_u32 v0, s11, s6, s12
-; GFX1032-NEXT: s_mul_i32 s10, s5, s1
-; GFX1032-NEXT: s_add_i32 s0, s0, s10
-; GFX1032-NEXT: v_sub_co_u32 v1, s12, v0, s4
-; GFX1032-NEXT: s_sub_i32 s10, s7, s0
-; GFX1032-NEXT: s_cmp_lg_u32 s11, 0
-; GFX1032-NEXT: s_subb_u32 s10, s10, s5
-; GFX1032-NEXT: s_cmp_lg_u32 s12, 0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v1
-; GFX1032-NEXT: s_subb_u32 s10, s10, 0
-; GFX1032-NEXT: s_cmp_ge_u32 s10, s5
-; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX1032-NEXT: s_cselect_b32 s12, -1, 0
-; GFX1032-NEXT: s_cmp_eq_u32 s10, s5
-; GFX1032-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GFX1032-NEXT: s_add_u32 s10, s1, 1
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1032-NEXT: s_addc_u32 s12, s9, 0
-; GFX1032-NEXT: s_add_u32 s13, s1, 2
-; GFX1032-NEXT: s_addc_u32 s14, s9, 0
-; GFX1032-NEXT: s_cmp_lg_u32 s11, 0
-; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v0
-; GFX1032-NEXT: s_subb_u32 s0, s7, s0
-; GFX1032-NEXT: v_mov_b32_e32 v2, s13
-; GFX1032-NEXT: s_cmp_ge_u32 s0, s5
-; GFX1032-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
-; GFX1032-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1032-NEXT: s_cmp_eq_u32 s0, s5
-; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
-; GFX1032-NEXT: s_cselect_b32 s0, -1, 0
-; GFX1032-NEXT: v_mov_b32_e32 v1, s14
-; GFX1032-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0
-; GFX1032-NEXT: v_cndmask_b32_e32 v2, s10, v2, vcc_lo
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo
-; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1032-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc_lo
-; GFX1032-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo
+; GFX1032-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX1032-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX1032-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX1032-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1032-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1032-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1032-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1032-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1032-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1032-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1032-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1032-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1032-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX1032-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1032-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1032-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1032-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1032-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1032-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1032-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1032-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1032-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1032-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1032-NEXT: v_add_co_u32 v4, vcc_lo, v4, v5
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v7, vcc_lo
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v8, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v2, vcc_lo, v3, v2
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX1032-NEXT: v_mul_hi_u32 v2, s6, v0
+; GFX1032-NEXT: v_mul_hi_u32 v5, s7, v0
+; GFX1032-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX1032-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX1032-NEXT: v_mul_lo_u32 v0, s7, v0
+; GFX1032-NEXT: v_mul_hi_u32 v6, s7, v1
+; GFX1032-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX1032-NEXT: v_add_co_u32 v2, vcc_lo, v2, v3
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v0, vcc_lo, v3, v5, vcc_lo
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v6, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v0, vcc_lo, v0, v1
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
+; GFX1032-NEXT: v_mul_hi_u32 v2, s4, v0
+; GFX1032-NEXT: v_mul_lo_u32 v4, s5, v0
+; GFX1032-NEXT: v_mul_lo_u32 v3, s4, v1
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1032-NEXT: v_mul_lo_u32 v3, s4, v0
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1032-NEXT: v_sub_co_u32 v3, vcc_lo, s6, v3
+; GFX1032-NEXT: v_sub_nc_u32_e32 v4, s7, v2
+; GFX1032-NEXT: v_subrev_co_ci_u32_e64 v4, s0, s5, v4, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v5, s0, v0, 1
+; GFX1032-NEXT: v_add_co_ci_u32_e64 v6, s0, 0, v1, s0
+; GFX1032-NEXT: v_sub_co_u32 v7, s0, v3, s4
+; GFX1032-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
+; GFX1032-NEXT: v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v7
+; GFX1032-NEXT: v_cmp_eq_u32_e64 s0, s5, v2
+; GFX1032-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s5, v4
+; GFX1032-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v3
+; GFX1032-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc_lo
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s5, v2
+; GFX1032-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
+; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v4
+; GFX1032-NEXT: v_cndmask_b32_e64 v2, v9, v3, s0
+; GFX1032-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo
+; GFX1032-NEXT: v_add_co_u32 v7, vcc_lo, v0, 2
+; GFX1032-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
+; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
+; GFX1032-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc_lo
+; GFX1032-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc_lo
+; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX1032-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s8
; GFX1032-NEXT: s_cbranch_vccnz .LBB15_3
; GFX1032-NEXT: .LBB15_2:
; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s4
-; GFX1032-NEXT: s_sub_i32 s1, 0, s4
+; GFX1032-NEXT: s_sub_i32 s0, 0, s4
; GFX1032-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1032-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1032-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1032-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1032-NEXT: s_mul_i32 s1, s1, s0
-; GFX1032-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX1032-NEXT: s_add_i32 s0, s0, s1
-; GFX1032-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX1032-NEXT: s_mul_i32 s1, s0, s4
-; GFX1032-NEXT: s_add_i32 s5, s0, 1
-; GFX1032-NEXT: s_sub_i32 s1, s6, s1
-; GFX1032-NEXT: s_sub_i32 s6, s1, s4
-; GFX1032-NEXT: s_cmp_ge_u32 s1, s4
-; GFX1032-NEXT: s_cselect_b32 s0, s5, s0
-; GFX1032-NEXT: s_cselect_b32 s1, s6, s1
-; GFX1032-NEXT: s_add_i32 s5, s0, 1
-; GFX1032-NEXT: s_cmp_ge_u32 s1, s4
-; GFX1032-NEXT: s_mov_b32 s1, 0
-; GFX1032-NEXT: s_cselect_b32 s0, s5, s0
-; GFX1032-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX1032-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1032-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1032-NEXT: v_mul_hi_u32 v0, s6, v0
+; GFX1032-NEXT: v_mul_lo_u32 v1, v0, s4
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1032-NEXT: v_sub_nc_u32_e32 v1, s6, v1
+; GFX1032-NEXT: v_subrev_nc_u32_e32 v3, s4, v1
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v1
+; GFX1032-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v1
+; GFX1032-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1032-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX1032-NEXT: .LBB15_3:
; GFX1032-NEXT: v_mov_b32_e32 v2, 0
; GFX1032-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] offset:16
@@ -903,8 +887,8 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1064-NEXT: ; %bb.1:
; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s4
; GFX1064-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GFX1064-NEXT: s_sub_u32 s9, 0, s4
-; GFX1064-NEXT: s_subb_u32 s10, 0, s5
+; GFX1064-NEXT: s_sub_u32 s0, 0, s4
+; GFX1064-NEXT: s_subb_u32 s1, 0, s5
; GFX1064-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
; GFX1064-NEXT: v_rcp_f32_e32 v0, v0
; GFX1064-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
@@ -913,136 +897,120 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 {
; GFX1064-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GFX1064-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1064-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1064-NEXT: v_readfirstlane_b32 s8, v1
-; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1064-NEXT: s_mul_i32 s1, s9, s8
-; GFX1064-NEXT: s_mul_hi_u32 s12, s9, s0
-; GFX1064-NEXT: s_mul_i32 s11, s10, s0
-; GFX1064-NEXT: s_add_i32 s1, s12, s1
-; GFX1064-NEXT: s_mul_i32 s13, s9, s0
-; GFX1064-NEXT: s_add_i32 s1, s1, s11
-; GFX1064-NEXT: s_mul_hi_u32 s12, s0, s13
-; GFX1064-NEXT: s_mul_hi_u32 s14, s8, s13
-; GFX1064-NEXT: s_mul_i32 s11, s8, s13
-; GFX1064-NEXT: s_mul_hi_u32 s13, s0, s1
-; GFX1064-NEXT: s_mul_i32 s0, s0, s1
-; GFX1064-NEXT: s_mul_hi_u32 s15, s8, s1
-; GFX1064-NEXT: s_add_u32 s0, s12, s0
-; GFX1064-NEXT: s_addc_u32 s12, 0, s13
-; GFX1064-NEXT: s_add_u32 s0, s0, s11
-; GFX1064-NEXT: s_mul_i32 s1, s8, s1
-; GFX1064-NEXT: s_addc_u32 s0, s12, s14
-; GFX1064-NEXT: s_addc_u32 s11, s15, 0
-; GFX1064-NEXT: s_add_u32 s0, s0, s1
-; GFX1064-NEXT: s_addc_u32 s11, 0, s11
-; GFX1064-NEXT: v_add_co_u32 v0, s[0:1], v0, s0
-; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: s_addc_u32 s8, s8, s11
-; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1064-NEXT: s_mul_i32 s1, s9, s8
-; GFX1064-NEXT: s_mul_hi_u32 s11, s9, s0
-; GFX1064-NEXT: s_mul_i32 s10, s10, s0
-; GFX1064-NEXT: s_add_i32 s1, s11, s1
-; GFX1064-NEXT: s_mul_i32 s9, s9, s0
-; GFX1064-NEXT: s_add_i32 s1, s1, s10
-; GFX1064-NEXT: s_mul_hi_u32 s11, s8, s9
-; GFX1064-NEXT: s_mul_i32 s12, s8, s9
-; GFX1064-NEXT: s_mul_hi_u32 s9, s0, s9
-; GFX1064-NEXT: s_mul_hi_u32 s13, s0, s1
-; GFX1064-NEXT: s_mul_i32 s0, s0, s1
-; GFX1064-NEXT: s_mul_hi_u32 s10, s8, s1
-; GFX1064-NEXT: s_add_u32 s0, s9, s0
-; GFX1064-NEXT: s_addc_u32 s9, 0, s13
-; GFX1064-NEXT: s_add_u32 s0, s0, s12
-; GFX1064-NEXT: s_mul_i32 s1, s8, s1
-; GFX1064-NEXT: s_addc_u32 s0, s9, s11
-; GFX1064-NEXT: s_addc_u32 s9, s10, 0
-; GFX1064-NEXT: s_add_u32 s0, s0, s1
-; GFX1064-NEXT: s_addc_u32 s9, 0, s9
-; GFX1064-NEXT: v_add_co_u32 v0, s[0:1], v0, s0
-; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: s_addc_u32 s0, s8, s9
-; GFX1064-NEXT: v_readfirstlane_b32 s1, v0
-; GFX1064-NEXT: s_mul_i32 s9, s6, s0
-; GFX1064-NEXT: s_mul_hi_u32 s8, s6, s0
-; GFX1064-NEXT: s_mul_hi_u32 s10, s7, s0
-; GFX1064-NEXT: s_mul_i32 s0, s7, s0
-; GFX1064-NEXT: s_mul_hi_u32 s11, s6, s1
-; GFX1064-NEXT: s_mul_hi_u32 s12, s7, s1
-; GFX1064-NEXT: s_mul_i32 s1, s7, s1
-; GFX1064-NEXT: s_add_u32 s9, s11, s9
-; GFX1064-NEXT: s_addc_u32 s8, 0, s8
-; GFX1064-NEXT: s_add_u32 s1, s9, s1
-; GFX1064-NEXT: s_addc_u32 s1, s8, s12
-; GFX1064-NEXT: s_addc_u32 s8, s10, 0
-; GFX1064-NEXT: s_add_u32 s10, s1, s0
-; GFX1064-NEXT: s_addc_u32 s11, 0, s8
-; GFX1064-NEXT: s_mul_hi_u32 s0, s4, s10
-; GFX1064-NEXT: s_mul_i32 s1, s4, s11
-; GFX1064-NEXT: s_mul_i32 s9, s4, s10
-; GFX1064-NEXT: s_add_i32 s12, s0, s1
-; GFX1064-NEXT: v_sub_co_u32 v0, s[0:1], s6, s9
-; GFX1064-NEXT: s_mul_i32 s8, s5, s10
-; GFX1064-NEXT: s_add_i32 s12, s12, s8
-; GFX1064-NEXT: v_sub_co_u32 v1, s[8:9], v0, s4
-; GFX1064-NEXT: s_sub_i32 s13, s7, s12
-; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: s_subb_u32 s13, s13, s5
-; GFX1064-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
-; GFX1064-NEXT: s_subb_u32 s8, s13, 0
-; GFX1064-NEXT: s_cmp_ge_u32 s8, s5
-; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX1064-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1064-NEXT: s_cmp_eq_u32 s8, s5
-; GFX1064-NEXT: s_cselect_b64 vcc, -1, 0
-; GFX1064-NEXT: s_add_u32 s8, s10, 1
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc
-; GFX1064-NEXT: s_addc_u32 s9, s11, 0
-; GFX1064-NEXT: s_add_u32 s13, s10, 2
-; GFX1064-NEXT: s_addc_u32 s14, s11, 0
-; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v0
-; GFX1064-NEXT: s_subb_u32 s0, s7, s12
-; GFX1064-NEXT: v_mov_b32_e32 v2, s13
-; GFX1064-NEXT: s_cmp_ge_u32 s0, s5
-; GFX1064-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GFX1064-NEXT: s_cselect_b32 s7, -1, 0
-; GFX1064-NEXT: s_cmp_eq_u32 s0, s5
-; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0
-; GFX1064-NEXT: v_mov_b32_e32 v1, s14
-; GFX1064-NEXT: v_cndmask_b32_e64 v0, s7, v0, s[0:1]
-; GFX1064-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc
-; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX1064-NEXT: v_cndmask_b32_e32 v1, s11, v1, vcc
-; GFX1064-NEXT: v_cndmask_b32_e32 v0, s10, v2, vcc
+; GFX1064-NEXT: v_mul_lo_u32 v2, s0, v1
+; GFX1064-NEXT: v_mul_hi_u32 v3, s0, v0
+; GFX1064-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v3, v2
+; GFX1064-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1064-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1064-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1064-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1064-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1064-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1064-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1064-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1064-NEXT: v_add_co_u32 v4, vcc, v4, v5
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v5, vcc, 0, v6, vcc
+; GFX1064-NEXT: v_add_co_u32 v3, vcc, v4, v3
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v3, vcc, v5, v7, vcc
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v8, vcc
+; GFX1064-NEXT: v_add_co_u32 v2, vcc, v3, v2
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1064-NEXT: v_add_co_u32 v0, vcc, v0, v2
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v3, vcc
+; GFX1064-NEXT: v_mul_hi_u32 v2, s0, v0
+; GFX1064-NEXT: v_mul_lo_u32 v4, s1, v0
+; GFX1064-NEXT: v_mul_lo_u32 v3, s0, v1
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1064-NEXT: v_mul_lo_u32 v3, s0, v0
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1064-NEXT: v_mul_hi_u32 v4, v0, v3
+; GFX1064-NEXT: v_mul_lo_u32 v5, v0, v2
+; GFX1064-NEXT: v_mul_hi_u32 v6, v0, v2
+; GFX1064-NEXT: v_mul_hi_u32 v7, v1, v3
+; GFX1064-NEXT: v_mul_lo_u32 v3, v1, v3
+; GFX1064-NEXT: v_mul_hi_u32 v8, v1, v2
+; GFX1064-NEXT: v_mul_lo_u32 v2, v1, v2
+; GFX1064-NEXT: v_add_co_u32 v4, vcc, v4, v5
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v5, vcc, 0, v6, vcc
+; GFX1064-NEXT: v_add_co_u32 v3, vcc, v4, v3
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v3, vcc, v5, v7, vcc
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v8, vcc
+; GFX1064-NEXT: v_add_co_u32 v2, vcc, v3, v2
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1064-NEXT: v_add_co_u32 v0, vcc, v0, v2
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, v1, v3, vcc
+; GFX1064-NEXT: v_mul_hi_u32 v2, s6, v0
+; GFX1064-NEXT: v_mul_hi_u32 v5, s7, v0
+; GFX1064-NEXT: v_mul_lo_u32 v3, s6, v1
+; GFX1064-NEXT: v_mul_hi_u32 v4, s6, v1
+; GFX1064-NEXT: v_mul_lo_u32 v0, s7, v0
+; GFX1064-NEXT: v_mul_hi_u32 v6, s7, v1
+; GFX1064-NEXT: v_mul_lo_u32 v1, s7, v1
+; GFX1064-NEXT: v_add_co_u32 v2, vcc, v2, v3
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v3, vcc, 0, v4, vcc
+; GFX1064-NEXT: v_add_co_u32 v0, vcc, v2, v0
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v0, vcc, v3, v5, vcc
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v2, vcc, 0, v6, vcc
+; GFX1064-NEXT: v_add_co_u32 v0, vcc, v0, v1
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, 0, v2, vcc
+; GFX1064-NEXT: v_mul_hi_u32 v2, s4, v0
+; GFX1064-NEXT: v_mul_lo_u32 v4, s5, v0
+; GFX1064-NEXT: v_mul_lo_u32 v3, s4, v1
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v2, v3
+; GFX1064-NEXT: v_mul_lo_u32 v3, s4, v0
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, v2, v4
+; GFX1064-NEXT: v_sub_co_u32 v3, vcc, s6, v3
+; GFX1064-NEXT: v_sub_nc_u32_e32 v4, s7, v2
+; GFX1064-NEXT: v_subrev_co_ci_u32_e64 v4, s[0:1], s5, v4, vcc
+; GFX1064-NEXT: v_add_co_u32 v5, s[0:1], v0, 1
+; GFX1064-NEXT: v_add_co_ci_u32_e64 v6, s[0:1], 0, v1, s[0:1]
+; GFX1064-NEXT: v_sub_co_u32 v7, s[0:1], v3, s4
+; GFX1064-NEXT: v_sub_co_ci_u32_e32 v2, vcc, s7, v2, vcc
+; GFX1064-NEXT: v_subrev_co_ci_u32_e64 v4, s[0:1], 0, v4, s[0:1]
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v7
+; GFX1064-NEXT: v_cmp_eq_u32_e64 s[0:1], s5, v2
+; GFX1064-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s5, v4
+; GFX1064-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v3
+; GFX1064-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s5, v2
+; GFX1064-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, s5, v4
+; GFX1064-NEXT: v_cndmask_b32_e64 v2, v9, v3, s[0:1]
+; GFX1064-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc
+; GFX1064-NEXT: v_add_co_u32 v7, vcc, v0, 2
+; GFX1064-NEXT: v_add_co_ci_u32_e32 v8, vcc, 0, v1, vcc
+; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX1064-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
+; GFX1064-NEXT: v_cndmask_b32_e32 v4, v6, v8, vcc
+; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX1064-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
+; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX1064-NEXT: s_cbranch_execnz .LBB15_3
; GFX1064-NEXT: .LBB15_2:
; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s4
-; GFX1064-NEXT: s_sub_i32 s1, 0, s4
+; GFX1064-NEXT: s_sub_i32 s0, 0, s4
; GFX1064-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX1064-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX1064-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX1064-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1064-NEXT: s_mul_i32 s1, s1, s0
-; GFX1064-NEXT: s_mul_hi_u32 s1, s0, s1
-; GFX1064-NEXT: s_add_i32 s0, s0, s1
-; GFX1064-NEXT: s_mul_hi_u32 s0, s6, s0
-; GFX1064-NEXT: s_mul_i32 s1, s0, s4
-; GFX1064-NEXT: s_add_i32 s5, s0, 1
-; GFX1064-NEXT: s_sub_i32 s1, s6, s1
-; GFX1064-NEXT: s_sub_i32 s6, s1, s4
-; GFX1064-NEXT: s_cmp_ge_u32 s1, s4
-; GFX1064-NEXT: s_cselect_b32 s0, s5, s0
-; GFX1064-NEXT: s_cselect_b32 s1, s6, s1
-; GFX1064-NEXT: s_add_i32 s5, s0, 1
-; GFX1064-NEXT: s_cmp_ge_u32 s1, s4
-; GFX1064-NEXT: s_mov_b32 s1, 0
-; GFX1064-NEXT: s_cselect_b32 s0, s5, s0
-; GFX1064-NEXT: v_mov_b32_e32 v0, s0
-; GFX1064-NEXT: v_mov_b32_e32 v1, s1
+; GFX1064-NEXT: v_mul_lo_u32 v1, s0, v0
+; GFX1064-NEXT: v_mul_hi_u32 v1, v0, v1
+; GFX1064-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX1064-NEXT: v_mul_hi_u32 v0, s6, v0
+; GFX1064-NEXT: v_mul_lo_u32 v1, v0, s4
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1064-NEXT: v_sub_nc_u32_e32 v1, s6, v1
+; GFX1064-NEXT: v_subrev_nc_u32_e32 v3, s4, v1
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
+; GFX1064-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v1
+; GFX1064-NEXT: v_add_nc_u32_e32 v2, 1, v0
+; GFX1064-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX1064-NEXT: .LBB15_3:
; GFX1064-NEXT: v_mov_b32_e32 v2, 0
; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] offset:16
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