[llvm] [CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (PR #131526)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 16 11:08:27 PDT 2025
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/131526
>From 09b4447d2b4b57681645c7b752cd5355da562578 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 16 Mar 2025 18:08:18 +0000
Subject: [PATCH] [CodeGen][GlobalISel] Add a getVectorIdxWidth and
getVectorIdxLLT.
>From #106446, this adds a variant of getVectorIdxTy that returns an LLT. Many
uses only look at the width, so a getVectorIdxWidth was added as the common
base.
---
.../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 7 +++----
llvm/include/llvm/CodeGen/TargetLowering.h | 18 ++++++++++++++++--
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 8 ++++----
.../lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 4 ++--
llvm/lib/CodeGen/MachineVerifier.cpp | 6 ++----
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 ++--
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 5 +++++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 4 ++--
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 4 +---
llvm/lib/Target/SystemZ/SystemZISelLowering.h | 4 ++--
11 files changed, 40 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 7b0475ac2481d..f9dcbeb370bef 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1375,10 +1375,9 @@ class MachineIRBuilder {
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res,
const SrcOp &Val,
const int Idx) {
- auto TLI = getMF().getSubtarget().getTargetLowering();
- unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits();
- return buildExtractVectorElement(
- Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx));
+ const TargetLowering *TLI = getMF().getSubtarget().getTargetLowering();
+ LLT IdxTy = TLI->getVectorIdxLLT(getDataLayout());
+ return buildExtractVectorElement(Res, Val, buildConstant(IdxTy, Idx));
}
/// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index a3fb4e9a8513b..053e9d14dc2f7 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -416,11 +416,25 @@ class TargetLoweringBase {
return ShiftValueTy;
}
+ /// Returns the type to be used for the index operand vector operations. By
+ /// default we assume it will have the same size as an address space 0
+ /// pointer.
+ virtual unsigned getVectorIdxWidth(const DataLayout &DL) const {
+ return DL.getPointerSizeInBits(0);
+ }
+
/// Returns the type to be used for the index operand of:
/// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
/// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
- virtual MVT getVectorIdxTy(const DataLayout &DL) const {
- return getPointerTy(DL);
+ MVT getVectorIdxTy(const DataLayout &DL) const {
+ return MVT::getIntegerVT(getVectorIdxWidth(DL));
+ }
+
+ /// Returns the type to be used for the index operand of:
+ /// G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT,
+ /// G_INSERT_SUBVECTOR, and G_EXTRACT_SUBVECTOR
+ LLT getVectorIdxLLT(const DataLayout &DL) const {
+ return LLT::scalar(getVectorIdxWidth(DL));
}
/// Returns the type to be used for the EVL/AVL operand of VP nodes:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index b85239ebf08cb..6014f57d439f0 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3174,7 +3174,7 @@ bool IRTranslator::translateInsertElement(const User &U,
Register Res = getOrCreateVReg(U);
Register Val = getOrCreateVReg(*U.getOperand(0));
Register Elt = getOrCreateVReg(*U.getOperand(1));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
Register Idx;
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3200,7 +3200,7 @@ bool IRTranslator::translateInsertVector(const User &U,
Register Elt = getOrCreateVReg(*U.getOperand(1));
ConstantInt *CI = cast<ConstantInt>(U.getOperand(2));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
// Resize Index to preferred index width.
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3255,7 +3255,7 @@ bool IRTranslator::translateExtractElement(const User &U,
Register Res = getOrCreateVReg(U);
Register Val = getOrCreateVReg(*U.getOperand(0));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
Register Idx;
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3279,7 +3279,7 @@ bool IRTranslator::translateExtractVector(const User &U,
Register Res = getOrCreateVReg(U);
Register Vec = getOrCreateVReg(*U.getOperand(0));
ConstantInt *CI = cast<ConstantInt>(U.getOperand(1));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
// Resize Index to preferred index width.
if (CI->getBitWidth() != PreferredVecIdxWidth) {
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index ed8bd25698c03..622d6d0052c51 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4229,7 +4229,7 @@ LegalizerHelper::scalarizeVectorBooleanStore(GStore &StoreMI) {
unsigned NumBits = MemTy.getSizeInBits();
LLT IntTy = LLT::scalar(NumBits);
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
- LLT IdxTy = getLLTForMVT(TLI.getVectorIdxTy(MF.getDataLayout()));
+ LLT IdxTy = TLI.getVectorIdxLLT(MF.getDataLayout());
for (unsigned I = 0, E = MemTy.getNumElements(); I < E; ++I) {
auto Elt = MIRBuilder.buildExtractVectorElement(
@@ -6277,7 +6277,7 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
auto NeutralElement = getNeutralElementForVecReduce(
MI.getOpcode(), MIRBuilder, MoreTy.getElementType());
- LLT IdxTy(TLI.getVectorIdxTy(MIRBuilder.getDataLayout()));
+ LLT IdxTy(TLI.getVectorIdxLLT(MIRBuilder.getDataLayout()));
for (size_t i = OrigTy.getNumElements(), e = MoreTy.getNumElements();
i != e; i++) {
auto Idx = MIRBuilder.buildConstant(IdxTy, i);
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 87d3033038414..b8067906b5d73 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1993,8 +1993,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
auto TLI = MF->getSubtarget().getTargetLowering();
- if (IdxTy.getSizeInBits() !=
- TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
+ if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
report("Index type must match VectorIdxTy", MI);
break;
}
@@ -2023,8 +2022,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
auto TLI = MF->getSubtarget().getTargetLowering();
- if (IdxTy.getSizeInBits() !=
- TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
+ if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
report("Index type must match VectorIdxTy", MI);
break;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index df30148b78b65..b0e3521a8d143 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7548,7 +7548,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
N1VT.getVectorMinNumElements()) &&
"Extract subvector overflow!");
assert(N2C->getAPIntValue().getBitWidth() ==
- TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
+ TLI->getVectorIdxWidth(getDataLayout()) &&
"Constant index for EXTRACT_SUBVECTOR has an invalid size");
// Trivial extraction.
@@ -7782,7 +7782,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
VT.getVectorMinNumElements()) &&
"Insert subvector overflow!");
assert(N3->getAsAPIntVal().getBitWidth() ==
- TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
+ TLI->getVectorIdxWidth(getDataLayout()) &&
"Constant index for INSERT_SUBVECTOR has an invalid size");
// Trivial insertion.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 1987c892ac080..bc0c3a832bb28 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -616,6 +616,11 @@ class AArch64TargetLowering : public TargetLowering {
}
}
+ unsigned getVectorIdxWidth(const DataLayout &DL) const override {
+ // The VectorIdx type is i64, with both normal and ilp32.
+ return 64;
+ }
+
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
const APInt &DemandedElts,
TargetLoweringOpt &TLO) const override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index ade81f17ecca5..281c06f598245 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -796,8 +796,8 @@ EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
return EVT::getIntegerVT(Context, 32 * ((Size + 31) / 32));
}
-MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
- return MVT::i32;
+unsigned AMDGPUTargetLowering::getVectorIdxWidth(const DataLayout &) const {
+ return 32;
}
bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index c74dc7942f52c..bb1dae1956143 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -209,7 +209,7 @@ class AMDGPUTargetLowering : public TargetLowering {
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
ISD::NodeType ExtendKind) const override;
- MVT getVectorIdxTy(const DataLayout &) const override;
+ unsigned getVectorIdxWidth(const DataLayout &) const override;
bool isSelectSupported(SelectSupportKind) const override;
bool isFPImmLegal(const APFloat &Imm, EVT VT,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
index 77356b7512a73..eb78299b72f04 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h
@@ -43,9 +43,7 @@ class SPIRVTargetLowering : public TargetLowering {
// This is to prevent sexts of non-i64 vector indices which are generated
// within general IRTranslator hence type generation for it is omitted.
- MVT getVectorIdxTy(const DataLayout &DL) const override {
- return MVT::getIntegerVT(32);
- }
+ unsigned getVectorIdxWidth(const DataLayout &DL) const override { return 32; }
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
CallingConv::ID CC,
EVT VT) const override;
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index a97962c17767c..86b5f82674818 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -430,10 +430,10 @@ class SystemZTargetLowering : public TargetLowering {
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
return MVT::i32;
}
- MVT getVectorIdxTy(const DataLayout &DL) const override {
+ unsigned getVectorIdxWidth(const DataLayout &DL) const override {
// Only the lower 12 bits of an element index are used, so we don't
// want to clobber the upper 32 bits of a GPR unnecessarily.
- return MVT::i32;
+ return 32;
}
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
const override {
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