[llvm] 90e6ba6 - [AArch64][GlobalISel] Remove min/max v2s64 clamp

David Green via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 16 03:43:02 PDT 2025


Author: David Green
Date: 2025-03-16T09:49:22Z
New Revision: 90e6ba606f7a0a8c9b7b3881a7a8df2cf4cfeb70

URL: https://github.com/llvm/llvm-project/commit/90e6ba606f7a0a8c9b7b3881a7a8df2cf4cfeb70
DIFF: https://github.com/llvm/llvm-project/commit/90e6ba606f7a0a8c9b7b3881a7a8df2cf4cfeb70.diff

LOG: [AArch64][GlobalISel] Remove min/max v2s64 clamp

We can now lower the icmp, allowing us to remove the FIXME.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
    llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index fdedf44e0ba1b..3598fe63c867c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -251,9 +251,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampNumElements(0, v8s8, v16s8)
       .clampNumElements(0, v4s16, v8s16)
       .clampNumElements(0, v2s32, v4s32)
-      // FIXME: This sholdn't be needed as v2s64 types are going to
-      // be expanded anyway, but G_ICMP doesn't support splitting vectors yet
-      .clampNumElements(0, v2s64, v2s64)
       .lower();
 
   getActionDefinitionsBuilder(

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
index 403c12d1f4235..4a3457a35256d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -248,17 +248,19 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
+    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
-    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
     ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -518,17 +520,19 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
+    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
-    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
     ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -788,17 +792,19 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
+    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
-    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
     ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -1058,17 +1064,19 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
     ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
+    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP]], 1
+    ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ICMP1]], 1
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
     ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
-    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]]
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
-    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]]
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]]
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[SEXT_INREG1]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[SEXT_INREG1]]
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
     ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND1]], [[AND3]]
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
     ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
     ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16

diff  --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 67d625dd16473..81770a4ebdd4d 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -388,29 +388,29 @@ define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-GI-NEXT:    fcvtzs v1.2d, v2.2d
 ; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI12_1]
 ; CHECK-GI-NEXT:    adrp x8, .LCPI12_0
+; CHECK-GI-NEXT:    cmgt v6.2d, v2.2d, v3.2d
 ; CHECK-GI-NEXT:    cmgt v4.2d, v2.2d, v0.2d
 ; CHECK-GI-NEXT:    cmgt v5.2d, v2.2d, v1.2d
 ; CHECK-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
 ; CHECK-GI-NEXT:    bif v1.16b, v2.16b, v5.16b
-; CHECK-GI-NEXT:    cmgt v4.2d, v2.2d, v3.2d
-; CHECK-GI-NEXT:    ldr q5, [x8, :lo12:.LCPI12_0]
-; CHECK-GI-NEXT:    bit v2.16b, v3.16b, v4.16b
-; CHECK-GI-NEXT:    cmgt v3.2d, v0.2d, v5.2d
-; CHECK-GI-NEXT:    cmgt v4.2d, v1.2d, v5.2d
-; CHECK-GI-NEXT:    bif v0.16b, v5.16b, v3.16b
-; CHECK-GI-NEXT:    bif v1.16b, v5.16b, v4.16b
-; CHECK-GI-NEXT:    cmgt v3.2d, v2.2d, v5.2d
-; CHECK-GI-NEXT:    bif v2.16b, v5.16b, v3.16b
+; CHECK-GI-NEXT:    ldr q4, [x8, :lo12:.LCPI12_0]
+; CHECK-GI-NEXT:    bit v2.16b, v3.16b, v6.16b
+; CHECK-GI-NEXT:    cmgt v3.2d, v0.2d, v4.2d
+; CHECK-GI-NEXT:    cmgt v5.2d, v1.2d, v4.2d
+; CHECK-GI-NEXT:    cmgt v6.2d, v2.2d, v4.2d
+; CHECK-GI-NEXT:    bif v0.16b, v4.16b, v3.16b
+; CHECK-GI-NEXT:    bif v1.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT:    bif v2.16b, v4.16b, v6.16b
 ; CHECK-GI-NEXT:    mov d3, v0.d[1]
 ; CHECK-GI-NEXT:    mov d4, v1.d[1]
 ; CHECK-GI-NEXT:    fmov x0, d0
+; CHECK-GI-NEXT:    fmov x4, d2
 ; CHECK-GI-NEXT:    fmov x2, d1
 ; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 killed $x0
 ; CHECK-GI-NEXT:    // kill: def $w2 killed $w2 killed $x2
-; CHECK-GI-NEXT:    fmov x4, d2
+; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
 ; CHECK-GI-NEXT:    fmov x1, d3
 ; CHECK-GI-NEXT:    fmov x3, d4
-; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
 ; CHECK-GI-NEXT:    // kill: def $w1 killed $w1 killed $x1
 ; CHECK-GI-NEXT:    // kill: def $w3 killed $w3 killed $x3
 ; CHECK-GI-NEXT:    ret
@@ -5236,6 +5236,7 @@ define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
 ; CHECK-GI-NEXT:    adrp x8, .LCPI83_0
 ; CHECK-GI-NEXT:    fcvtzs v6.2d, v6.2d
 ; CHECK-GI-NEXT:    fcvtzs v7.2d, v7.2d
+; CHECK-GI-NEXT:    ldr q25, [x8, :lo12:.LCPI83_0]
 ; CHECK-GI-NEXT:    cmgt v17.2d, v16.2d, v0.2d
 ; CHECK-GI-NEXT:    cmgt v18.2d, v16.2d, v1.2d
 ; CHECK-GI-NEXT:    cmgt v19.2d, v16.2d, v2.2d
@@ -5246,29 +5247,28 @@ define <16 x i8> @test_signed_v16f64_v16i8(<16 x double> %f) {
 ; CHECK-GI-NEXT:    cmgt v24.2d, v16.2d, v7.2d
 ; CHECK-GI-NEXT:    bif v0.16b, v16.16b, v17.16b
 ; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v18.16b
-; CHECK-GI-NEXT:    ldr q17, [x8, :lo12:.LCPI83_0]
 ; CHECK-GI-NEXT:    bif v2.16b, v16.16b, v19.16b
 ; CHECK-GI-NEXT:    bif v3.16b, v16.16b, v20.16b
 ; CHECK-GI-NEXT:    bif v4.16b, v16.16b, v21.16b
 ; CHECK-GI-NEXT:    bif v5.16b, v16.16b, v22.16b
 ; CHECK-GI-NEXT:    bif v6.16b, v16.16b, v23.16b
 ; CHECK-GI-NEXT:    bif v7.16b, v16.16b, v24.16b
-; CHECK-GI-NEXT:    cmgt v16.2d, v0.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v18.2d, v1.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v19.2d, v2.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v20.2d, v3.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v21.2d, v4.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v22.2d, v5.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v23.2d, v6.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v24.2d, v7.2d, v17.2d
-; CHECK-GI-NEXT:    bif v0.16b, v17.16b, v16.16b
-; CHECK-GI-NEXT:    bif v1.16b, v17.16b, v18.16b
-; CHECK-GI-NEXT:    bif v2.16b, v17.16b, v19.16b
-; CHECK-GI-NEXT:    bif v3.16b, v17.16b, v20.16b
-; CHECK-GI-NEXT:    bif v4.16b, v17.16b, v21.16b
-; CHECK-GI-NEXT:    bif v5.16b, v17.16b, v22.16b
-; CHECK-GI-NEXT:    bif v6.16b, v17.16b, v23.16b
-; CHECK-GI-NEXT:    bif v7.16b, v17.16b, v24.16b
+; CHECK-GI-NEXT:    cmgt v16.2d, v0.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v17.2d, v1.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v18.2d, v2.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v19.2d, v3.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v20.2d, v4.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v21.2d, v5.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v22.2d, v6.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v23.2d, v7.2d, v25.2d
+; CHECK-GI-NEXT:    bif v0.16b, v25.16b, v16.16b
+; CHECK-GI-NEXT:    bif v1.16b, v25.16b, v17.16b
+; CHECK-GI-NEXT:    bif v2.16b, v25.16b, v18.16b
+; CHECK-GI-NEXT:    bif v3.16b, v25.16b, v19.16b
+; CHECK-GI-NEXT:    bif v4.16b, v25.16b, v20.16b
+; CHECK-GI-NEXT:    bif v5.16b, v25.16b, v21.16b
+; CHECK-GI-NEXT:    bif v6.16b, v25.16b, v22.16b
+; CHECK-GI-NEXT:    bif v7.16b, v25.16b, v23.16b
 ; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
 ; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
 ; CHECK-GI-NEXT:    uzp1 v2.4s, v4.4s, v5.4s
@@ -5505,6 +5505,7 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
 ; CHECK-GI-NEXT:    adrp x8, .LCPI85_0
 ; CHECK-GI-NEXT:    fcvtzs v6.2d, v6.2d
 ; CHECK-GI-NEXT:    fcvtzs v7.2d, v7.2d
+; CHECK-GI-NEXT:    ldr q25, [x8, :lo12:.LCPI85_0]
 ; CHECK-GI-NEXT:    cmgt v17.2d, v16.2d, v0.2d
 ; CHECK-GI-NEXT:    cmgt v18.2d, v16.2d, v1.2d
 ; CHECK-GI-NEXT:    cmgt v19.2d, v16.2d, v2.2d
@@ -5515,29 +5516,28 @@ define <16 x i16> @test_signed_v16f64_v16i16(<16 x double> %f) {
 ; CHECK-GI-NEXT:    cmgt v24.2d, v16.2d, v7.2d
 ; CHECK-GI-NEXT:    bif v0.16b, v16.16b, v17.16b
 ; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v18.16b
-; CHECK-GI-NEXT:    ldr q17, [x8, :lo12:.LCPI85_0]
 ; CHECK-GI-NEXT:    bif v2.16b, v16.16b, v19.16b
 ; CHECK-GI-NEXT:    bif v3.16b, v16.16b, v20.16b
 ; CHECK-GI-NEXT:    bif v4.16b, v16.16b, v21.16b
 ; CHECK-GI-NEXT:    bif v5.16b, v16.16b, v22.16b
 ; CHECK-GI-NEXT:    bif v6.16b, v16.16b, v23.16b
 ; CHECK-GI-NEXT:    bif v7.16b, v16.16b, v24.16b
-; CHECK-GI-NEXT:    cmgt v16.2d, v0.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v18.2d, v1.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v19.2d, v2.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v20.2d, v3.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v21.2d, v4.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v22.2d, v5.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v23.2d, v6.2d, v17.2d
-; CHECK-GI-NEXT:    cmgt v24.2d, v7.2d, v17.2d
-; CHECK-GI-NEXT:    bif v0.16b, v17.16b, v16.16b
-; CHECK-GI-NEXT:    bif v1.16b, v17.16b, v18.16b
-; CHECK-GI-NEXT:    bif v2.16b, v17.16b, v19.16b
-; CHECK-GI-NEXT:    bif v3.16b, v17.16b, v20.16b
-; CHECK-GI-NEXT:    bif v4.16b, v17.16b, v21.16b
-; CHECK-GI-NEXT:    bif v5.16b, v17.16b, v22.16b
-; CHECK-GI-NEXT:    bif v6.16b, v17.16b, v23.16b
-; CHECK-GI-NEXT:    bif v7.16b, v17.16b, v24.16b
+; CHECK-GI-NEXT:    cmgt v16.2d, v0.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v17.2d, v1.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v18.2d, v2.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v19.2d, v3.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v20.2d, v4.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v21.2d, v5.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v22.2d, v6.2d, v25.2d
+; CHECK-GI-NEXT:    cmgt v23.2d, v7.2d, v25.2d
+; CHECK-GI-NEXT:    bif v0.16b, v25.16b, v16.16b
+; CHECK-GI-NEXT:    bif v1.16b, v25.16b, v17.16b
+; CHECK-GI-NEXT:    bif v2.16b, v25.16b, v18.16b
+; CHECK-GI-NEXT:    bif v3.16b, v25.16b, v19.16b
+; CHECK-GI-NEXT:    bif v4.16b, v25.16b, v20.16b
+; CHECK-GI-NEXT:    bif v5.16b, v25.16b, v21.16b
+; CHECK-GI-NEXT:    bif v6.16b, v25.16b, v22.16b
+; CHECK-GI-NEXT:    bif v7.16b, v25.16b, v23.16b
 ; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
 ; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
 ; CHECK-GI-NEXT:    uzp1 v2.4s, v4.4s, v5.4s

diff  --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 4d3486d4a2993..a01644678b25f 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -367,22 +367,22 @@ define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-GI-NEXT:    fcvtzu v3.2d, v4.2d
 ; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
 ; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-GI-NEXT:    cmhi v6.2d, v1.2d, v3.2d
 ; CHECK-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
 ; CHECK-GI-NEXT:    cmhi v5.2d, v1.2d, v2.2d
 ; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
 ; CHECK-GI-NEXT:    bif v2.16b, v1.16b, v5.16b
-; CHECK-GI-NEXT:    cmhi v4.2d, v1.2d, v3.2d
-; CHECK-GI-NEXT:    bit v1.16b, v3.16b, v4.16b
+; CHECK-GI-NEXT:    bit v1.16b, v3.16b, v6.16b
 ; CHECK-GI-NEXT:    mov d3, v0.d[1]
 ; CHECK-GI-NEXT:    mov d4, v2.d[1]
+; CHECK-GI-NEXT:    fmov x4, d1
 ; CHECK-GI-NEXT:    fmov x0, d0
 ; CHECK-GI-NEXT:    fmov x2, d2
+; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
 ; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 killed $x0
 ; CHECK-GI-NEXT:    // kill: def $w2 killed $w2 killed $x2
-; CHECK-GI-NEXT:    fmov x4, d1
 ; CHECK-GI-NEXT:    fmov x1, d3
 ; CHECK-GI-NEXT:    fmov x3, d4
-; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
 ; CHECK-GI-NEXT:    // kill: def $w1 killed $w1 killed $x1
 ; CHECK-GI-NEXT:    // kill: def $w3 killed $w3 killed $x3
 ; CHECK-GI-NEXT:    ret


        


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