[llvm] 2549517 - [X86][APX] Remove the EFLAGS def operand rather than the last one (#131430)

[via llvm-commits]

Author: Phoebe Wang
Date: 2025-03-15T16:37:38+08:00
New Revision: 254951749febef42620242fd22dfba62f624f79f

URL: https://github.com/llvm/llvm-project/commit/254951749febef42620242fd22dfba62f624f79f
DIFF: https://github.com/llvm/llvm-project/commit/254951749febef42620242fd22dfba62f624f79f.diff

LOG: [X86][APX] Remove the EFLAGS def operand rather than the last one (#131430)

The last one may be an implict use, e.g.,
`IDIV32r %4:gr32, implicit-def dead $eax, implicit-def $edx,
implicit-def dead $eflags, implicit $eax, implicit $edx`

https://godbolt.org/z/KPKzj5c8K

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrInfo.cpp
    llvm/test/CodeGen/X86/apx/ctest.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index b13412df4b8b0..0c1329c55fcd6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5691,7 +5691,8 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   // Replace non-NF with NF instructions.
   for (auto &Inst : InstsToUpdate) {
     Inst.first->setDesc(get(Inst.second));
-    Inst.first->removeOperand(Inst.first->getNumOperands() - 1);
+    Inst.first->removeOperand(
+        Inst.first->findRegisterDefOperandIdx(X86::EFLAGS, /*TRI=*/nullptr));
   }
 
   // Make sure Sub instruction defines EFLAGS and mark the def live.

diff  --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll
index 4f79b0a999632..5f3ec8a19d0a4 100644
--- a/llvm/test/CodeGen/X86/apx/ctest.ll
+++ b/llvm/test/CodeGen/X86/apx/ctest.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+ndd -verify-machineinstrs | FileCheck %s --check-prefix=NDD
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+nf -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ccmp,+ndd,+nf -verify-machineinstrs | FileCheck %s --check-prefix=NDD
 
 define void @ctest8rr_zf(i8 noundef %a, i8 noundef %b) {
 ; CHECK-LABEL: ctest8rr_zf:
@@ -936,4 +936,52 @@ if.end:                                           ; preds = %entry, %if.then
   ret void
 }
 
+define void @cmp_srem(ptr %p, i32 %a, ptr %b) {
+; CHECK-LABEL: cmp_srem:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    subl $1, %eax
+; CHECK-NEXT:    movl (%rdi), %edi
+; CHECK-NEXT:    cltd
+; CHECK-NEXT:    {nf} idivl %edi
+; CHECK-NEXT:    ctestnel {dfv=} %edx, %edx
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    cmpl $1, %esi
+; CHECK-NEXT:    ccmpael {dfv=zf} $1, %edi
+; CHECK-NEXT:    sete %dl
+; CHECK-NEXT:    orb %al, %dl
+; CHECK-NEXT:    movb %dl, (%rcx)
+; CHECK-NEXT:    retq
+;
+; NDD-LABEL: cmp_srem:
+; NDD:       # %bb.0: # %bb
+; NDD-NEXT:    movq %rdx, %rcx
+; NDD-NEXT:    subl $1, %esi, %eax
+; NDD-NEXT:    movl (%rdi), %edi
+; NDD-NEXT:    cltd
+; NDD-NEXT:    {nf} idivl %edi
+; NDD-NEXT:    ctestnel {dfv=} %edx, %edx
+; NDD-NEXT:    sete %al
+; NDD-NEXT:    cmpl $1, %esi
+; NDD-NEXT:    ccmpael {dfv=zf} $1, %edi
+; NDD-NEXT:    sete %dl
+; NDD-NEXT:    orb %dl, %al
+; NDD-NEXT:    movb %al, (%rcx)
+; NDD-NEXT:    retq
+bb:
+  %i = icmp eq i32 %a, 0
+  %i2 = load i32, ptr %p, align 4
+  %i3 = icmp eq i32 %i2, 1
+  %i4 = or i1 %i, %i3
+  %i5 = add i32 %a, -1
+  %i6 = srem i32 %i5, %i2
+  %i7 = icmp eq i32 %i6, 0
+  %i8 = icmp ne i32 %a, 1
+  %i9 = and i1 %i8, %i7
+  %i10 = or i1 %i4, %i9
+  store i1 %i10, ptr %b, align 1
+  ret void
+}
+
 declare dso_local void @foo(...)