[llvm] [RISCV] Reorder RISCVInstrInfoXCV.td to separate Operands, SDNodeXForms, formats, and instructions into separate sections. NFC (PR #131411)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 14 18:15:34 PDT 2025


https://github.com/topperc created https://github.com/llvm/llvm-project/pull/131411

This is more consistent with some of our other InstrInfo.td file.

>From b0e9cebe5a586abb43b5bffce366c64e2fe35f2e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 14 Mar 2025 18:07:11 -0700
Subject: [PATCH] [RISCV] Reorder RISCVInstrInfoXCV.td to separate Operands,
 SDNodeXForms, formats, and instructions into separate sections. NFC

---
 llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 654 +++++++++++----------
 1 file changed, 335 insertions(+), 319 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 344b8e13ba2ae..e18a61ad79278 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -10,6 +10,51 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def CVrrAsmOperand : AsmOperandClass {
+  let Name = "RegReg";
+  let ParserMethod = "parseRegReg";
+  let DiagnosticType = "InvalidRegReg";
+  let DiagnosticString = "operands must be register and register";
+}
+
+def CVrr : Operand<i32>,
+           ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {
+   let ParserMatchClass = CVrrAsmOperand;
+   let EncoderMethod =  "getRegReg";
+   let DecoderMethod = "decodeRegReg";
+   let PrintMethod = "printRegReg";
+   let MIOperandInfo = (ops GPR:$base, GPR:$offset);
+}
+
+def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
+def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
+def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
+
+def CV_LO5: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def CV_HI5: SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def powerOf2Minus1 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(Imm+1); }]>;
+def trailing1sPlus1 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(
+                          llvm::countr_one(N->getZExtValue()) + 1,
+                          SDLoc(N), N->getValueType(0));
+}]>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
@@ -38,37 +83,6 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
-let Predicates = [HasVendorXCVbitmanip, IsRV32], DecoderNamespace = "XCV" in {
-  def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
-  def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
-
-  def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
-  def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
-  def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
-
-  def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
-  def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
-
-  let Constraints = "$rd = $rd_wb" in {
-    def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
-                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
-                             "cv.insert", "$rd, $rs1, $is3, $is2">;
-    let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
-                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
-                             "cv.insertr", "$rd, $rs1, $rs2">;
-  }
-
-  def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
-  def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
-
-  def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
-  def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
-  def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
-  def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
-  def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
-}
-
 class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1,
               (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
@@ -103,69 +117,6 @@ class CVInstMulN<bits<2> funct2, bits<3> funct3, string opcodestr>
     : CVInstMacMulN<funct2, funct3, (outs GPR:$rd),
                     (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
 
-let Predicates = [HasVendorXCVmac, IsRV32], DecoderNamespace = "XCV" in {
-  // 32x32 bit macs
-  def CV_MAC      : CVInstMac<0b1001000, 0b011, "cv.mac">,
-                    Sched<[]>;
-  def CV_MSU      : CVInstMac<0b1001001, 0b011, "cv.msu">,
-                    Sched<[]>;
-
-  // Signed 16x16 bit macs with imm
-  def CV_MACSN    : CVInstMacN<0b00, 0b110, "cv.macsn">,
-                    Sched<[]>;
-  def CV_MACHHSN  : CVInstMacN<0b01, 0b110, "cv.machhsn">,
-                    Sched<[]>;
-  def CV_MACSRN   : CVInstMacN<0b10, 0b110, "cv.macsrn">,
-                    Sched<[]>;
-  def CV_MACHHSRN : CVInstMacN<0b11, 0b110, "cv.machhsrn">,
-                    Sched<[]>;
-
-  // Unsigned 16x16 bit macs with imm
-  def CV_MACUN    : CVInstMacN<0b00, 0b111, "cv.macun">,
-                    Sched<[]>;
-  def CV_MACHHUN  : CVInstMacN<0b01, 0b111, "cv.machhun">,
-                    Sched<[]>;
-  def CV_MACURN   : CVInstMacN<0b10, 0b111, "cv.macurn">,
-                    Sched<[]>;
-  def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">,
-                    Sched<[]>;
-
-  // Signed 16x16 bit muls with imm
-  def CV_MULSN    : CVInstMulN<0b00, 0b100, "cv.mulsn">,
-                    Sched<[]>;
-  def CV_MULHHSN  : CVInstMulN<0b01, 0b100, "cv.mulhhsn">,
-                    Sched<[]>;
-  def CV_MULSRN   : CVInstMulN<0b10, 0b100, "cv.mulsrn">,
-                    Sched<[]>;
-  def CV_MULHHSRN : CVInstMulN<0b11, 0b100, "cv.mulhhsrn">,
-                    Sched<[]>;
-
-  // Unsigned 16x16 bit muls with imm
-  def CV_MULUN    : CVInstMulN<0b00, 0b101, "cv.mulun">,
-                    Sched<[]>;
-  def CV_MULHHUN  : CVInstMulN<0b01, 0b101, "cv.mulhhun">,
-                    Sched<[]>;
-  def CV_MULURN   : CVInstMulN<0b10, 0b101, "cv.mulurn">,
-                    Sched<[]>;
-  def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">,
-                    Sched<[]>;
-} // Predicates = [HasVendorXCVmac, IsRV32], DecoderNamespace = "XCV"
-
-let Predicates = [HasVendorXCVmac, IsRV32] in {
-  // Xcvmac Pseudo Instructions
-  // Signed 16x16 bit muls
-  def : InstAlias<"cv.muls $rd1, $rs1, $rs2",
-                  (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
-  def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",
-                  (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
-
-  // Unsigned 16x16 bit muls
-  def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
-                  (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
-  def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
-                  (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
-} // Predicates = [HasVendorXCVmac, IsRV32]
-
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
       : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
@@ -204,81 +155,6 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
   }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
-let Predicates = [HasVendorXCValu, IsRV32], DecoderNamespace = "XCV" in {
-  // General ALU Operations
-  def CV_ABS    : CVInstAluR<0b0101000, 0b011, "cv.abs">,
-                  Sched<[]>;
-  def CV_SLE    : CVInstAluRR<0b0101001, 0b011, "cv.sle">,
-                  Sched<[]>;
-  def CV_SLEU   : CVInstAluRR<0b0101010, 0b011, "cv.sleu">,
-                  Sched<[]>;
-  def CV_MIN    : CVInstAluRR<0b0101011, 0b011, "cv.min">,
-                  Sched<[]>;
-  def CV_MINU   : CVInstAluRR<0b0101100, 0b011, "cv.minu">,
-                  Sched<[]>;
-  def CV_MAX    : CVInstAluRR<0b0101101, 0b011, "cv.max">,
-                  Sched<[]>;
-  def CV_MAXU   : CVInstAluRR<0b0101110, 0b011, "cv.maxu">,
-                  Sched<[]>;
-  def CV_EXTHS  : CVInstAluR<0b0110000, 0b011, "cv.exths">,
-                  Sched<[]>;
-  def CV_EXTHZ  : CVInstAluR<0b0110001, 0b011, "cv.exthz">,
-                  Sched<[]>;
-  def CV_EXTBS  : CVInstAluR<0b0110010, 0b011, "cv.extbs">,
-                  Sched<[]>;
-  def CV_EXTBZ  : CVInstAluR<0b0110011, 0b011, "cv.extbz">,
-                  Sched<[]>;
-
-  def CV_CLIP   : CVInstAluRI<0b0111000, 0b011, "cv.clip">,
-                  Sched<[]>;
-  def CV_CLIPU  : CVInstAluRI<0b0111001, 0b011, "cv.clipu">,
-                  Sched<[]>;
-  def CV_CLIPR  : CVInstAluRR<0b0111010, 0b011, "cv.clipr">,
-                  Sched<[]>;
-  def CV_CLIPUR : CVInstAluRR<0b0111011, 0b011, "cv.clipur">,
-                  Sched<[]>;
-
-  def CV_ADDN   : CVInstAluRRI<0b00, 0b010, "cv.addn">,
-                  Sched<[]>;
-  def CV_ADDUN  : CVInstAluRRI<0b01, 0b010, "cv.addun">,
-                  Sched<[]>;
-  def CV_ADDRN  : CVInstAluRRI<0b10, 0b010, "cv.addrn">,
-                  Sched<[]>;
-  def CV_ADDURN : CVInstAluRRI<0b11, 0b010, "cv.addurn">,
-                  Sched<[]>;
-  def CV_SUBN   : CVInstAluRRI<0b00, 0b011, "cv.subn">,
-                  Sched<[]>;
-  def CV_SUBUN  : CVInstAluRRI<0b01, 0b011, "cv.subun">,
-                  Sched<[]>;
-  def CV_SUBRN  : CVInstAluRRI<0b10, 0b011, "cv.subrn">,
-                  Sched<[]>;
-  def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
-                  Sched<[]>;
-
-  def CV_ADDNR   : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
-                   Sched<[]>;
-  def CV_ADDUNR  : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,
-                   Sched<[]>;
-  def CV_ADDRNR  : CVInstAluRRNR<0b1000010, 0b011, "cv.addrnr">,
-                   Sched<[]>;
-  def CV_ADDURNR : CVInstAluRRNR<0b1000011, 0b011, "cv.addurnr">,
-                   Sched<[]>;
-  def CV_SUBNR   : CVInstAluRRNR<0b1000100, 0b011, "cv.subnr">,
-                   Sched<[]>;
-  def CV_SUBUNR  : CVInstAluRRNR<0b1000101, 0b011, "cv.subunr">,
-                   Sched<[]>;
-  def CV_SUBRNR  : CVInstAluRRNR<0b1000110, 0b011, "cv.subrnr">,
-                   Sched<[]>;
-  def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
-                   Sched<[]>;
-
-} // Predicates = [HasVendorXCValu, IsRV32]
-
-let Predicates = [HasVendorXCValu, IsRV32] in {
-  def : MnemonicAlias<"cv.slet", "cv.sle">;
-  def : MnemonicAlias<"cv.sletu", "cv.sleu">;
-}
-
 class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
                    RISCVOpcode opcode, dag outs,
                    dag ins, string opcodestr, string argstr>
@@ -384,30 +260,268 @@ multiclass CVSIMDBinaryUnsignedWb<bits<5> funct5, bit F, bit funct1, string mnem
   def CV_ # NAME # _SCI_B : CVSIMDRUWb<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
 }
 
+class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+    : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
+  bits<5> imm5;
+  let rs2 = imm5;
+  let isBranch = 1;
+  let isTerminator = 1;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+}
 
-let Predicates = [HasVendorXCVsimd, IsRV32], DecoderNamespace = "XCV" in {
-  defm ADD :    CVSIMDBinarySigned<0b00000, 0, 0, "add">;
-  defm SUB :    CVSIMDBinarySigned<0b00001, 0, 0, "sub">;
-  defm AVG :    CVSIMDBinarySigned<0b00010, 0, 0, "avg">;
-  defm AVGU : CVSIMDBinaryUnsigned<0b00011, 0, 0, "avgu">;
-  defm MIN :    CVSIMDBinarySigned<0b00100, 0, 0, "min">;
-  defm MINU : CVSIMDBinaryUnsigned<0b00101, 0, 0, "minu">;
-  defm MAX :    CVSIMDBinarySigned<0b00110, 0, 0, "max">;
-  defm MAXU : CVSIMDBinaryUnsigned<0b00111, 0, 0, "maxu">;
-  defm SRL :           CVSIMDShift<0b01000, 0, 0, "srl">;
-  defm SRA :           CVSIMDShift<0b01001, 0, 0, "sra">;
-  defm SLL :           CVSIMDShift<0b01010, 0, 0, "sll">;
-  defm OR :     CVSIMDBinarySigned<0b01011, 0, 0, "or">;
-  defm XOR :    CVSIMDBinarySigned<0b01100, 0, 0, "xor">;
-  defm AND :    CVSIMDBinarySigned<0b01101, 0, 0, "and">;
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
+              (ins GPRMem:$rs1, simm12:$imm12),
+              opcodestr, "$rd, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+}
 
-  def CV_ABS_H :    CVSIMDR<0b01110, 0, 0, 0b000, "cv.abs.h">;
-  def CV_ABS_B :    CVSIMDR<0b01110, 0, 0, 0b001, "cv.abs.b">;
+class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb),
+              (ins GPRMem:$rs1, GPR:$rs2),
+              opcodestr, "$rd, (${rs1}), ${rs2}"> {
+  let Constraints = "$rs1_wb = $rs1";
+}
 
-  // 0b01111xx: UNDEF
+class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
+              opcodestr, "$rd, $cvrr"> {
+  bits<5> rd;
+  bits<10> cvrr;
 
-  defm DOTUP :   CVSIMDBinaryUnsigned<0b10000, 0, 0, "dotup">;
-  defm DOTUSP :  CVSIMDBinarySigned<0b10001, 0, 0, "dotusp">;
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = cvrr{4-0};
+  let Inst{19-15} = cvrr{9-5};
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+}
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+class CVStore_ri_inc<bits<3> funct3, string opcodestr>
+    : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
+              (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rs2, (${rs1}), ${imm12}"> {
+  let Constraints = "$rs1_wb = $rs1";
+}
+
+class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>
+    : RVInst<(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3), opcodestr,
+             "$rs2, (${rs1}), ${rs3}", [], InstFormatOther> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rs3;
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+  let Constraints = "$rs1_wb = $rs1";
+}
+
+
+class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
+    : RVInst<(outs), (ins GPR:$rs2, CVrr:$cvrr), opcodestr, "$rs2, $cvrr", [],
+             InstFormatOther> {
+  bits<5> rs2;
+  bits<10> cvrr;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = cvrr{9-5};
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = cvrr{4-0};
+  let Inst{6-0} = OPC_CUSTOM_1.Value;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
+
+class CVLoad_ri<bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+      (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XCV" in {
+
+let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
+  def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
+  def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
+
+  def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
+  def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
+  def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
+
+  def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
+  def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
+
+  let Constraints = "$rd = $rd_wb" in {
+    def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
+                             (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
+                             "cv.insert", "$rd, $rs1, $is3, $is2">;
+    let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+    def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
+                             (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                             "cv.insertr", "$rd, $rs1, $rs2">;
+  }
+
+  def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
+  def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
+
+  def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
+  def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
+  def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
+  def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
+  def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
+} // Predicates = [HasVendorXCVbitmanip, IsRV32]
+
+let Predicates = [HasVendorXCVmac, IsRV32] in {
+  // 32x32 bit macs
+  def CV_MAC      : CVInstMac<0b1001000, 0b011, "cv.mac">,
+                    Sched<[]>;
+  def CV_MSU      : CVInstMac<0b1001001, 0b011, "cv.msu">,
+                    Sched<[]>;
+
+  // Signed 16x16 bit macs with imm
+  def CV_MACSN    : CVInstMacN<0b00, 0b110, "cv.macsn">,
+                    Sched<[]>;
+  def CV_MACHHSN  : CVInstMacN<0b01, 0b110, "cv.machhsn">,
+                    Sched<[]>;
+  def CV_MACSRN   : CVInstMacN<0b10, 0b110, "cv.macsrn">,
+                    Sched<[]>;
+  def CV_MACHHSRN : CVInstMacN<0b11, 0b110, "cv.machhsrn">,
+                    Sched<[]>;
+
+  // Unsigned 16x16 bit macs with imm
+  def CV_MACUN    : CVInstMacN<0b00, 0b111, "cv.macun">,
+                    Sched<[]>;
+  def CV_MACHHUN  : CVInstMacN<0b01, 0b111, "cv.machhun">,
+                    Sched<[]>;
+  def CV_MACURN   : CVInstMacN<0b10, 0b111, "cv.macurn">,
+                    Sched<[]>;
+  def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">,
+                    Sched<[]>;
+
+  // Signed 16x16 bit muls with imm
+  def CV_MULSN    : CVInstMulN<0b00, 0b100, "cv.mulsn">,
+                    Sched<[]>;
+  def CV_MULHHSN  : CVInstMulN<0b01, 0b100, "cv.mulhhsn">,
+                    Sched<[]>;
+  def CV_MULSRN   : CVInstMulN<0b10, 0b100, "cv.mulsrn">,
+                    Sched<[]>;
+  def CV_MULHHSRN : CVInstMulN<0b11, 0b100, "cv.mulhhsrn">,
+                    Sched<[]>;
+
+  // Unsigned 16x16 bit muls with imm
+  def CV_MULUN    : CVInstMulN<0b00, 0b101, "cv.mulun">,
+                    Sched<[]>;
+  def CV_MULHHUN  : CVInstMulN<0b01, 0b101, "cv.mulhhun">,
+                    Sched<[]>;
+  def CV_MULURN   : CVInstMulN<0b10, 0b101, "cv.mulurn">,
+                    Sched<[]>;
+  def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">,
+                    Sched<[]>;
+} // Predicates = [HasVendorXCVmac, IsRV32]
+
+let Predicates = [HasVendorXCValu, IsRV32] in {
+  // General ALU Operations
+  def CV_ABS    : CVInstAluR<0b0101000, 0b011, "cv.abs">,
+                  Sched<[]>;
+  def CV_SLE    : CVInstAluRR<0b0101001, 0b011, "cv.sle">,
+                  Sched<[]>;
+  def CV_SLEU   : CVInstAluRR<0b0101010, 0b011, "cv.sleu">,
+                  Sched<[]>;
+  def CV_MIN    : CVInstAluRR<0b0101011, 0b011, "cv.min">,
+                  Sched<[]>;
+  def CV_MINU   : CVInstAluRR<0b0101100, 0b011, "cv.minu">,
+                  Sched<[]>;
+  def CV_MAX    : CVInstAluRR<0b0101101, 0b011, "cv.max">,
+                  Sched<[]>;
+  def CV_MAXU   : CVInstAluRR<0b0101110, 0b011, "cv.maxu">,
+                  Sched<[]>;
+  def CV_EXTHS  : CVInstAluR<0b0110000, 0b011, "cv.exths">,
+                  Sched<[]>;
+  def CV_EXTHZ  : CVInstAluR<0b0110001, 0b011, "cv.exthz">,
+                  Sched<[]>;
+  def CV_EXTBS  : CVInstAluR<0b0110010, 0b011, "cv.extbs">,
+                  Sched<[]>;
+  def CV_EXTBZ  : CVInstAluR<0b0110011, 0b011, "cv.extbz">,
+                  Sched<[]>;
+
+  def CV_CLIP   : CVInstAluRI<0b0111000, 0b011, "cv.clip">,
+                  Sched<[]>;
+  def CV_CLIPU  : CVInstAluRI<0b0111001, 0b011, "cv.clipu">,
+                  Sched<[]>;
+  def CV_CLIPR  : CVInstAluRR<0b0111010, 0b011, "cv.clipr">,
+                  Sched<[]>;
+  def CV_CLIPUR : CVInstAluRR<0b0111011, 0b011, "cv.clipur">,
+                  Sched<[]>;
+
+  def CV_ADDN   : CVInstAluRRI<0b00, 0b010, "cv.addn">,
+                  Sched<[]>;
+  def CV_ADDUN  : CVInstAluRRI<0b01, 0b010, "cv.addun">,
+                  Sched<[]>;
+  def CV_ADDRN  : CVInstAluRRI<0b10, 0b010, "cv.addrn">,
+                  Sched<[]>;
+  def CV_ADDURN : CVInstAluRRI<0b11, 0b010, "cv.addurn">,
+                  Sched<[]>;
+  def CV_SUBN   : CVInstAluRRI<0b00, 0b011, "cv.subn">,
+                  Sched<[]>;
+  def CV_SUBUN  : CVInstAluRRI<0b01, 0b011, "cv.subun">,
+                  Sched<[]>;
+  def CV_SUBRN  : CVInstAluRRI<0b10, 0b011, "cv.subrn">,
+                  Sched<[]>;
+  def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
+                  Sched<[]>;
+
+  def CV_ADDNR   : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
+                   Sched<[]>;
+  def CV_ADDUNR  : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,
+                   Sched<[]>;
+  def CV_ADDRNR  : CVInstAluRRNR<0b1000010, 0b011, "cv.addrnr">,
+                   Sched<[]>;
+  def CV_ADDURNR : CVInstAluRRNR<0b1000011, 0b011, "cv.addurnr">,
+                   Sched<[]>;
+  def CV_SUBNR   : CVInstAluRRNR<0b1000100, 0b011, "cv.subnr">,
+                   Sched<[]>;
+  def CV_SUBUNR  : CVInstAluRRNR<0b1000101, 0b011, "cv.subunr">,
+                   Sched<[]>;
+  def CV_SUBRNR  : CVInstAluRRNR<0b1000110, 0b011, "cv.subrnr">,
+                   Sched<[]>;
+  def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
+                   Sched<[]>;
+} // Predicates = [HasVendorXCValu, IsRV32]
+
+let Predicates = [HasVendorXCVsimd, IsRV32] in {
+  defm ADD :    CVSIMDBinarySigned<0b00000, 0, 0, "add">;
+  defm SUB :    CVSIMDBinarySigned<0b00001, 0, 0, "sub">;
+  defm AVG :    CVSIMDBinarySigned<0b00010, 0, 0, "avg">;
+  defm AVGU : CVSIMDBinaryUnsigned<0b00011, 0, 0, "avgu">;
+  defm MIN :    CVSIMDBinarySigned<0b00100, 0, 0, "min">;
+  defm MINU : CVSIMDBinaryUnsigned<0b00101, 0, 0, "minu">;
+  defm MAX :    CVSIMDBinarySigned<0b00110, 0, 0, "max">;
+  defm MAXU : CVSIMDBinaryUnsigned<0b00111, 0, 0, "maxu">;
+  defm SRL :           CVSIMDShift<0b01000, 0, 0, "srl">;
+  defm SRA :           CVSIMDShift<0b01001, 0, 0, "sra">;
+  defm SLL :           CVSIMDShift<0b01010, 0, 0, "sll">;
+  defm OR :     CVSIMDBinarySigned<0b01011, 0, 0, "or">;
+  defm XOR :    CVSIMDBinarySigned<0b01100, 0, 0, "xor">;
+  defm AND :    CVSIMDBinarySigned<0b01101, 0, 0, "and">;
+
+  def CV_ABS_H :    CVSIMDR<0b01110, 0, 0, 0b000, "cv.abs.h">;
+  def CV_ABS_B :    CVSIMDR<0b01110, 0, 0, 0b001, "cv.abs.b">;
+
+  // 0b01111xx: UNDEF
+
+  defm DOTUP :   CVSIMDBinaryUnsigned<0b10000, 0, 0, "dotup">;
+  defm DOTUSP :  CVSIMDBinarySigned<0b10001, 0, 0, "dotusp">;
   defm DOTSP :   CVSIMDBinarySigned<0b10010, 0, 0, "dotsp">;
   defm SDOTUP :  CVSIMDBinaryUnsignedWb<0b10011, 0, 0, "sdotup">;
   defm SDOTUSP : CVSIMDBinarySignedWb<0b10100, 0, 0, "sdotusp">;
@@ -482,19 +596,7 @@ let Predicates = [HasVendorXCVsimd, IsRV32], DecoderNamespace = "XCV" in {
   def CV_SUB_DIV8 :    CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;
 }
 
-class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
-                      string opcodestr, string argstr>
-    : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
-  bits<5> imm5;
-  let rs2 = imm5;
-  let isBranch = 1;
-  let isTerminator = 1;
-  let hasSideEffects = 0;
-  let mayLoad = 0;
-  let mayStore = 0;
-}
-
-let Predicates = [HasVendorXCVbi, IsRV32], DecoderNamespace = "XCV" in {
+let Predicates = [HasVendorXCVbi, IsRV32] in {
   // Immediate branching operations
   def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
         (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
@@ -504,52 +606,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], DecoderNamespace = "XCV" in {
         "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
 }
 
-def CVrrAsmOperand : AsmOperandClass {
-  let Name = "RegReg";
-  let ParserMethod = "parseRegReg";
-  let DiagnosticType = "InvalidRegReg";
-  let DiagnosticString = "operands must be register and register";
-}
-
-def CVrr : Operand<i32>,
-           ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {
-   let ParserMatchClass = CVrrAsmOperand;
-   let EncoderMethod =  "getRegReg";
-   let DecoderMethod = "decodeRegReg";
-   let PrintMethod = "printRegReg";
-   let MIOperandInfo = (ops GPR:$base, GPR:$offset);
-}
-
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
-              (ins GPRMem:$rs1, simm12:$imm12),
-              opcodestr, "$rd, (${rs1}), ${imm12}"> {
-  let Constraints = "$rs1_wb = $rs1";
-}
-
-class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
-    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb),
-              (ins GPRMem:$rs1, GPR:$rs2),
-              opcodestr, "$rd, (${rs1}), ${rs2}"> {
-  let Constraints = "$rs1_wb = $rs1";
-}
-
-class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
-    : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
-              opcodestr, "$rd, $cvrr"> {
-  bits<5> rd;
-  bits<10> cvrr;
-
-  let Inst{31-25} = funct7;
-  let Inst{24-20} = cvrr{4-0};
-  let Inst{19-15} = cvrr{9-5};
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-}
-} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
-
-let Predicates = [HasVendorXCVmem, IsRV32], DecoderNamespace = "XCV" in {
+let Predicates = [HasVendorXCVmem, IsRV32] in {
   // Register-Immediate load with post-increment
   def CV_LB_ri_inc  : CVLoad_ri_inc<0b000, "cv.lb">;
   def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
@@ -570,49 +627,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], DecoderNamespace = "XCV" in {
   def CV_LH_rr  : CVLoad_rr<0b0000101, 0b011, "cv.lh">;
   def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;
   def CV_LW_rr  : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
-}
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-class CVStore_ri_inc<bits<3> funct3, string opcodestr>
-    : RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
-              (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
-              opcodestr, "$rs2, (${rs1}), ${imm12}"> {
-  let Constraints = "$rs1_wb = $rs1";
-}
-
-class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>
-    : RVInst<(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3), opcodestr,
-             "$rs2, (${rs1}), ${rs3}", [], InstFormatOther> {
-  bits<5> rs3;
-  bits<5> rs2;
-  bits<5> rs1;
-
-  let Inst{31-25} = funct7;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rs3;
-  let Inst{6-0} = OPC_CUSTOM_1.Value;
-  let Constraints = "$rs1_wb = $rs1";
-}
-
-
-class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
-    : RVInst<(outs), (ins GPR:$rs2, CVrr:$cvrr), opcodestr, "$rs2, $cvrr", [],
-             InstFormatOther> {
-  bits<5> rs2;
-  bits<10> cvrr;
 
-  let Inst{31-25} = funct7;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = cvrr{9-5};
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = cvrr{4-0};
-  let Inst{6-0} = OPC_CUSTOM_1.Value;
-}
-} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
-
-let Predicates = [HasVendorXCVmem, IsRV32], DecoderNamespace = "XCV" in {
   // Register-Immediate store with post-increment
   def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
   def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;
@@ -629,16 +644,38 @@ let Predicates = [HasVendorXCVmem, IsRV32], DecoderNamespace = "XCV" in {
   def CV_SW_rr : CVStore_rr<0b011, 0b0010110, "cv.sw">;
 }
 
-class CVLoad_ri<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
-      (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
-
-let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
+let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0,
     mayLoad = 1, mayStore = 0 in {
   // Event load
   def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
 }
 
+} // DecoderNamespace = "XCV"
+
+//===----------------------------------------------------------------------===//
+// Aliases
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasVendorXCVmac, IsRV32] in {
+  // Xcvmac Pseudo Instructions
+  // Signed 16x16 bit muls
+  def : InstAlias<"cv.muls $rd1, $rs1, $rs2",
+                  (CV_MULSN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
+  def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",
+                  (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
+
+  // Unsigned 16x16 bit muls
+  def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
+                  (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
+  def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
+                  (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
+} // Predicates = [HasVendorXCVmac, IsRV32]
+
+let Predicates = [HasVendorXCValu, IsRV32] in {
+  def : MnemonicAlias<"cv.slet", "cv.sle">;
+  def : MnemonicAlias<"cv.sletu", "cv.sleu">;
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns for load & store operations
 //===----------------------------------------------------------------------===//
@@ -680,31 +717,10 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStrrPat<store, CV_SW_rr>;
 }
 
-def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
-def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
-def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
-
-def CV_LO5: SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
-def CV_HI5: SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
-def powerOf2Minus1 : ImmLeaf<XLenVT, [{ return isPowerOf2_32(Imm+1); }]>;
-def trailing1sPlus1 : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(
-                          llvm::countr_one(N->getZExtValue()) + 1,
-                          SDLoc(N), N->getValueType(0));
-}]>;
-
 multiclass PatCoreVBitManip<Intrinsic intr> {
   def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
   def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
-            (!cast<RVInst>("CV_" # NAME) 
+            (!cast<RVInst>("CV_" # NAME)
              GPR:$rs1, (CV_HI5 cv_uimm10:$imm), (CV_LO5 cv_uimm10:$imm))>;
 }
 
@@ -717,7 +733,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
   def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, GPR:$rs2, GPR:$rd),
             (CV_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
   def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, cv_uimm10:$imm, GPR:$rd),
-            (CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm), 
+            (CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm),
                                           (CV_LO5 cv_uimm10:$imm))>;
 
   def : PatGpr<cttz, CV_FF1>;
@@ -727,7 +743,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
 
   def : PatGprGpr<rotr, CV_ROR>;
 
-  def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts, 
+  def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts,
              cv_tuimm2:$radix),
             (CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
   def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;



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