[llvm] dccc0a8 - [NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN() (#131379)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 14 14:02:19 PDT 2025
Author: Shilei Tian
Date: 2025-03-14T17:02:15-04:00
New Revision: dccc0a836c20914549fa375905615db49d2f813b
URL: https://github.com/llvm/llvm-project/commit/dccc0a836c20914549fa375905615db49d2f813b
DIFF: https://github.com/llvm/llvm-project/commit/dccc0a836c20914549fa375905615db49d2f813b.diff
LOG: [NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN() (#131379)
This is an extension of #131357. Hopefully this would be the last one.
Added:
Modified:
clang/include/clang/Driver/ToolChain.h
clang/lib/Basic/Targets/AMDGPU.h
clang/lib/Driver/Driver.cpp
clang/lib/Driver/ToolChains/HIPAMD.cpp
clang/lib/Frontend/CompilerInvocation.cpp
flang/lib/Frontend/CompilerInvocation.cpp
llvm/include/llvm/TargetParser/Triple.h
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Removed:
################################################################################
diff --git a/clang/include/clang/Driver/ToolChain.h b/clang/include/clang/Driver/ToolChain.h
index 7d1d8feebf35e..90004c64a694a 100644
--- a/clang/include/clang/Driver/ToolChain.h
+++ b/clang/include/clang/Driver/ToolChain.h
@@ -821,7 +821,7 @@ class ToolChain {
return llvm::Triple("nvptx-nvidia-cuda");
if (TT.getArch() == llvm::Triple::nvptx64)
return llvm::Triple("nvptx64-nvidia-cuda");
- if (TT.getArch() == llvm::Triple::amdgcn)
+ if (TT.isAMDGCN())
return llvm::Triple("amdgcn-amd-amdhsa");
}
return TT;
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 3d6778fb5a76f..63b0d4b6e5fc0 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -52,7 +52,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
std::string TargetID;
bool hasFP64() const {
- return getTriple().getArch() == llvm::Triple::amdgcn ||
+ return getTriple().isAMDGCN() ||
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
}
@@ -62,12 +62,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
/// Has fast fma f64
- bool hasFastFMA() const {
- return getTriple().getArch() == llvm::Triple::amdgcn;
- }
+ bool hasFastFMA() const { return getTriple().isAMDGCN(); }
bool hasFMAF() const {
- return getTriple().getArch() == llvm::Triple::amdgcn ||
+ return getTriple().isAMDGCN() ||
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);
}
@@ -76,13 +74,11 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
bool hasLDEXPF() const {
- return getTriple().getArch() == llvm::Triple::amdgcn ||
+ return getTriple().isAMDGCN() ||
!!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);
}
- static bool isAMDGCN(const llvm::Triple &TT) {
- return TT.getArch() == llvm::Triple::amdgcn;
- }
+ static bool isAMDGCN(const llvm::Triple &TT) { return TT.isAMDGCN(); }
static bool isR600(const llvm::Triple &TT) {
return TT.getArch() == llvm::Triple::r600;
@@ -125,7 +121,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
uint64_t getMaxPointerWidth() const override {
- return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
+ return getTriple().isAMDGCN() ? 64 : 32;
}
bool hasBFloat16Type() const override { return isAMDGCN(getTriple()); }
@@ -269,7 +265,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
}
bool isValidCPUName(StringRef Name) const override {
- if (getTriple().getArch() == llvm::Triple::amdgcn)
+ if (getTriple().isAMDGCN())
return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
}
@@ -277,7 +273,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
bool setCPU(const std::string &Name) override {
- if (getTriple().getArch() == llvm::Triple::amdgcn) {
+ if (getTriple().isAMDGCN()) {
GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
} else {
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 848b27012976d..056bfcf1b739a 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -158,8 +158,7 @@ getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
auto TT = getOffloadTargetTriple(D, Args);
if (!TT)
return std::nullopt;
- if (TT->getArch() == llvm::Triple::amdgcn &&
- TT->getVendor() == llvm::Triple::AMD &&
+ if (TT->isAMDGCN() && TT->getVendor() == llvm::Triple::AMD &&
TT->getOS() == llvm::Triple::AMDHSA)
return TT;
if (TT->getArch() == llvm::Triple::spirv64)
@@ -3409,8 +3408,7 @@ class OffloadingActionBuilder final {
const ToolChain *HostTC = C.getSingleOffloadToolChain<Action::OFK_Host>();
assert(HostTC && "No toolchain for host compilation.");
- if (HostTC->getTriple().isNVPTX() ||
- HostTC->getTriple().getArch() == llvm::Triple::amdgcn) {
+ if (HostTC->getTriple().isNVPTX() || HostTC->getTriple().isAMDGCN()) {
// We do not support targeting NVPTX/AMDGCN for host compilation. Throw
// an error and abort pipeline construction early so we don't trip
// asserts that assume device-side compilation.
diff --git a/clang/lib/Driver/ToolChains/HIPAMD.cpp b/clang/lib/Driver/ToolChains/HIPAMD.cpp
index 271626ed54aed..55a8f2ca87de0 100644
--- a/clang/lib/Driver/ToolChains/HIPAMD.cpp
+++ b/clang/lib/Driver/ToolChains/HIPAMD.cpp
@@ -296,7 +296,7 @@ HIPAMDToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
}
Tool *HIPAMDToolChain::buildLinker() const {
- assert(getTriple().getArch() == llvm::Triple::amdgcn ||
+ assert(getTriple().isAMDGCN() ||
getTriple().getArch() == llvm::Triple::spirv64);
return new tools::AMDGCN::Linker(*this);
}
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 4eb743acf327f..e708bee464c5c 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -4322,8 +4322,7 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
TT.getArch() == llvm::Triple::systemz ||
TT.getArch() == llvm::Triple::loongarch64 ||
TT.getArch() == llvm::Triple::nvptx ||
- TT.getArch() == llvm::Triple::nvptx64 ||
- TT.getArch() == llvm::Triple::amdgcn ||
+ TT.getArch() == llvm::Triple::nvptx64 || TT.isAMDGCN() ||
TT.getArch() == llvm::Triple::x86 ||
TT.getArch() == llvm::Triple::x86_64))
Diags.Report(diag::err_drv_invalid_omp_target) << A->getValue(i);
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp
index edf738785fb97..f433ec9966922 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -1174,8 +1174,7 @@ static bool parseOpenMPArgs(CompilerInvocation &res, llvm::opt::ArgList &args,
!(tt.getArch() == llvm::Triple::aarch64 || tt.isPPC() ||
tt.getArch() == llvm::Triple::systemz ||
tt.getArch() == llvm::Triple::nvptx ||
- tt.getArch() == llvm::Triple::nvptx64 ||
- tt.getArch() == llvm::Triple::amdgcn ||
+ tt.getArch() == llvm::Triple::nvptx64 || tt.isAMDGCN() ||
tt.getArch() == llvm::Triple::x86 ||
tt.getArch() == llvm::Triple::x86_64))
diags.Report(clang::diag::err_drv_invalid_omp_target)
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index 390ed7fbab8c0..da5b05632f2ec 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -888,9 +888,7 @@ class Triple {
/// Tests whether the target is AMDGCN
bool isAMDGCN() const { return getArch() == Triple::amdgcn; }
- bool isAMDGPU() const {
- return getArch() == Triple::r600 || getArch() == Triple::amdgcn;
- }
+ bool isAMDGPU() const { return getArch() == Triple::r600 || isAMDGCN(); }
/// Tests whether the target is Thumb (little and big endian).
bool isThumb() const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 746e9e4f65099..5e4ac35224a7b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -454,8 +454,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
// 1 = Vector Register Class
SmallVector<SDValue, 32 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
- bool IsGCN = CurDAG->getSubtarget().getTargetTriple().getArch() ==
- Triple::amdgcn;
+ bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN();
RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
bool IsRegSeq = true;
unsigned NOps = N->getNumOperands();
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 54ed3789326cb..82e310d73b69a 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5463,7 +5463,7 @@ bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
}
bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
- if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
+ if (!getSTI().getTargetTriple().isAMDGCN())
return TokError("directive only supported for amdgcn architecture");
std::string TargetIDDirective;
@@ -5550,7 +5550,7 @@ bool AMDGPUAsmParser::calculateGPRBlocks(
}
bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
- if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
+ if (!getSTI().getTargetTriple().isAMDGCN())
return TokError("directive only supported for amdgcn architecture");
if (!isHsaAbi(getSTI()))
@@ -6142,7 +6142,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
}
bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
- if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
+ if (!getSTI().getTargetTriple().isAMDGCN()) {
return Error(getLoc(),
".amd_amdgpu_isa directive is not available on non-amdgcn "
"architectures");
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index ac6b07bad3e35..cf3413d1f8bfb 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1004,7 +1004,7 @@ unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
unsigned FlatWorkGroupSize) {
assert(FlatWorkGroupSize != 0);
- if (STI->getTargetTriple().getArch() != Triple::amdgcn)
+ if (!STI->getTargetTriple().isAMDGCN())
return 8;
unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
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