[llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)

[via llvm-commits]

https://github.com/mssefat created https://github.com/llvm/llvm-project/pull/131387

This fixes an issue where the si-fold-operands pass would incorrectly fold immediate values into COPY instructions targeting av_32 registers.

The pass now checks register class constraints before attempting to fold the immediate.

>From fe1800af2772bd1b68fa1c11cfda53ca727a51dd Mon Sep 17 00:00:00 2001
From: mssefat <syadus.sefat at gmail.com>
Date: Fri, 14 Mar 2025 16:14:19 -0400
Subject: [PATCH] [AMDGPU] Fix register class constraints for si-fold-operands
 pass

This fixes an issue where the si-fold-operands pass would incorrectly
fold immediate values into COPY instructions targeting av_32 registers,
which is illegal.

The pass now properly checks register class constraints before attempting to
fold the immediates.
---
 llvm/lib/Target/AMDGPU/SIFoldOperands.cpp     |  5 +++
 .../AMDGPU/si-fold-operands-imm-into-copy.mir | 36 +++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/si-fold-operands-imm-into-copy.mir

diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 91df516b80857..5a7fefaafd768 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1047,6 +1047,11 @@ void SIFoldOperandsImpl::foldOperand(
     if (MovOp == AMDGPU::COPY)
       return;
 
+    // Check if the destination register of the MOV operation belongs
+    // to a vector superclass. Folding would be illegal.
+    if (TRI->isVectorSuperClass(DestRC))
+      return;
+
     MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
     MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
     while (ImpOpI != ImpOpE) {
diff --git a/llvm/test/CodeGen/AMDGPU/si-fold-operands-imm-into-copy.mir b/llvm/test/CodeGen/AMDGPU/si-fold-operands-imm-into-copy.mir
new file mode 100644
index 0000000000000..869da156a83d6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-fold-operands-imm-into-copy.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-fold-operands -verify-machineinstrs -o - %s 2>&1 | FileCheck %s
+
+---
+
+name: s_mov_b32_imm_literal_copy_s_to_av_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: s_mov_b32_imm_literal_copy_s_to_av_32
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[S_MOV_B32_]]
+    ; CHECK-NEXT: $agpr0 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sreg_32 = S_MOV_B32 999
+    %1:av_32 = COPY %0
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+...
+
+---
+
+name: v_mov_b32_imm_literal_copy_v_to_av_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: v_mov_b32_imm_literal_copy_v_to_av_32
+    ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[V_MOV_B32_e32_]]
+    ; CHECK-NEXT: $agpr0 = COPY [[COPY]]
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
+    %1:av_32 = COPY %0
+    $agpr0 = COPY %1
+    S_ENDPGM 0
+...