[llvm] [RISCV] Add combine for shadd family of instructions. (PR #130829)

[Min-Yih Hsu via llvm-commits]

================
@@ -14306,6 +14314,86 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::SHL, DL, VT, SHADD, DAG.getConstant(Bits, DL, VT));
 }
 
+// Check if this SDValue is an add immediate that is fed by a shift of 1, 2,
+// or 3.
+static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,
+                              int64_t &ShlConst) {
+  // Based on testing it seems that performance degrades if the ADDI has
+  // more than 2 uses.
+  if (AddI->use_size() > 2)
+    return false;
+
+  auto *AddConstNode = dyn_cast<ConstantSDNode>(AddI->getOperand(1));
+  if (!AddConstNode)
+    return false;
+
+  SDValue SHLVal = AddI->getOperand(0);
+  if (SHLVal->getOpcode() != ISD::SHL)
+    return false;
+
+  auto *ShiftNode = dyn_cast<ConstantSDNode>(SHLVal->getOperand(1));
+  if (!ShiftNode)
+    return false;
+
+  if (ShiftNode->getSExtValue() < 1 || ShiftNode->getSExtValue() > 3)
+    return false;
+
+  ShlConst = ShiftNode->getSExtValue();
+  AddConst = AddConstNode->getSExtValue();
+  return true;
+}
+
+// Optimize (add (add (shl x, c0),  c1), y) ->
+//          (ADDI (SH*ADD y, x), c1), if c0 equals to [1|2|3].
+static SDValue combineShlAddIAdd(SDNode *N, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
+  // Perform this optimization only in the zba extension.
+  if (!ReassocShlAddiAdd || !Subtarget.hasStdExtZba())
+    return SDValue();
+
+  // Skip for vector types and larger types.
+  EVT VT = N->getValueType(0);
+  if (VT != Subtarget.getXLenVT())
+    return SDValue();
+
+  // Looking for a reg-reg add and not an addi.
+  if (isa<ConstantSDNode>(N->getOperand(1)))
+    return SDValue();
+
+  SDValue AddI = N->getOperand(0);
+  SDValue Other = N->getOperand(1);
+  bool LHSIsAddI = SDPatternMatch::sd_match(
+      AddI, SDPatternMatch::m_Add(SDPatternMatch::m_Value(),
+                                  SDPatternMatch::m_ConstInt()));
+  bool RHSIsAddI = SDPatternMatch::sd_match(
+      Other, SDPatternMatch::m_Add(SDPatternMatch::m_Value(),
+                                   SDPatternMatch::m_ConstInt()));
+  int64_t AddConst = 0;
+  int64_t ShlConst = 0;
+
+  // At least one addi is required.
+  if (!LHSIsAddI && !RHSIsAddI)
+    return SDValue();
+
+  // If the LHS is not the result of an add or both sides are results of an add,
+  // but the LHS does not have the desired structure with a shift, swap the
+  // operands.
+  if (!LHSIsAddI || (RHSIsAddI && !checkAddiForShift(AddI, AddConst, ShlConst)))
----------------
mshockwave wrote:

I think you can exploit the fact that `m_Add` is commutative, so with this
```
auto AddIPat = m_Add(m_Value(), m_ConstantInt());
sd_match(N, m_Add(m_Value(OtherI), m_AllOf(AddIPat, m_Value(AddI))))
```
You don't need to worry about whether it's LHS or RHS (of N) being ADDI. And thus saving you some code, including the swapping here.

https://github.com/llvm/llvm-project/pull/130829