[llvm] [BOLT] Pass unfiltered relocations to disassembler. NFCI (PR #131202)
Maksim Panchenko via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 14 11:47:17 PDT 2025
================
@@ -256,78 +256,6 @@ static bool skipRelocationTypeRISCV(uint64_t Type) {
}
}
-static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) {
- return false;
-}
-
-static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
- auto IsMov = [](uint64_t Contents) -> bool {
- // The bits 28-23 are 0b100101
- return (Contents & 0x1f800000) == 0x12800000;
- };
-
- auto IsB = [](uint64_t Contents) -> bool {
- // The bits 31-26 are 0b000101
- return (Contents & 0xfc000000) == 0x14000000;
- };
-
- auto IsAddImm = [](uint64_t Contents) -> bool {
- // The bits 30-23 are 0b00100010
- return (Contents & 0x7F800000) == 0x11000000;
- };
-
- // The linker might relax ADRP+LDR instruction sequence for loading symbol
- // address from GOT table to ADRP+ADD sequence that would point to the
- // binary-local symbol. Change relocation type in order to process it right.
- if (Type == ELF::R_AARCH64_LD64_GOT_LO12_NC && IsAddImm(Contents)) {
- Type = ELF::R_AARCH64_ADD_ABS_LO12_NC;
- return false;
- }
-
- // The linker might perform TLS relocations relaxations, such as
- // changed TLS access model (e.g. changed global dynamic model
- // to initial exec), thus changing the instructions. The static
- // relocations might be invalid at this point and we might no
- // need to process these relocations anymore.
- // More information could be found by searching
- // elfNN_aarch64_tls_relax in bfd
- switch (Type) {
- default:
- break;
- case ELF::R_AARCH64_TLSDESC_LD64_LO12:
- case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
- case ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
- case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: {
- if (IsMov(Contents))
- return true;
- }
- }
-
- // The linker might replace load/store instruction with jump and
- // veneer due to errata 843419
- // https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
- // Thus load/store relocations for these instructions must be ignored
- // NOTE: We only process GOT and TLS relocations this way since the
- // addend used in load/store instructions won't change after bolt
- // (it is important since the instruction in veneer won't have relocation)
- switch (Type) {
- default:
- break;
- case ELF::R_AARCH64_LD64_GOT_LO12_NC:
----------------
maksfb wrote:
We currently don't symbolize branch instructions, so I was under impression that this code was effectively a no-op . cc: @yota9 . Also, I realized that we lack a test case for the errata.
https://github.com/llvm/llvm-project/pull/131202
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