[llvm] 352b9e6 - [X86] combineConcatVectorOps - extend ISD::ROTLI/VROTRI handling to support 256-bit types

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-03-14T17:34:27Z
New Revision: 352b9e65be1756cafd6097ce858f87a2a48a71c5

URL: https://github.com/llvm/llvm-project/commit/352b9e65be1756cafd6097ce858f87a2a48a71c5
DIFF: https://github.com/llvm/llvm-project/commit/352b9e65be1756cafd6097ce858f87a2a48a71c5.diff

LOG: [X86] combineConcatVectorOps - extend ISD::ROTLI/VROTRI handling to support 256-bit types

Add checks that we aren't concatenating 128-bit X86ISD::VPERMI nodes.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f02609a62425b..25101d0c9ba27 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58330,11 +58330,15 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
     case X86ISD::VPERMI:
     case X86ISD::VROTLI:
     case X86ISD::VROTRI:
-      // TODO: 256-bit VROT?I handling
-      if (VT.is512BitVector() && Subtarget.useAVX512Regs() &&
+      if (!IsSplat &&
+          ((VT.is256BitVector() && Subtarget.hasVLX()) ||
+           (VT.is512BitVector() && Subtarget.useAVX512Regs())) &&
           llvm::all_of(Ops, [Op0](SDValue Op) {
             return Op0.getOperand(1) == Op.getOperand(1);
           })) {
+        assert(!(Opcode == X86ISD::VPERMI &&
+                 Op0.getValueType().is128BitVector()) &&
+               "Illegal 128-bit X86ISD::VPERMI nodes");
         return DAG.getNode(Opcode, DL, VT, ConcatSubOperand(VT, Ops, 0),
                            Op0.getOperand(1));
       }

diff  --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
index b942af1dc87d9..2d72cfee7fe74 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
@@ -102,9 +102,9 @@ declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 define <8 x i32> @concat_vrotli_v4i32(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK-LABEL: concat_vrotli_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vprold $3, %xmm0, %xmm0
-; CHECK-NEXT:    vprold $3, %xmm1, %xmm1
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
 ; CHECK-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vprold $3, %ymm0, %ymm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %r0 = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a0, <4 x i32> %a0, <4 x i32> splat (i32 3))
   %r1 = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a1, <4 x i32> %a1, <4 x i32> splat (i32 3))