[llvm] [RISCV] Add nf argument to VReg class instead overriding with a let. NFC (PR #131235)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/131235

>From 9a4a055081b7a2d462de1290574d0da0bc2d6fda Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 13 Mar 2025 15:51:30 -0700
Subject: [PATCH] [RISCV] Add nf argument to VReg class instead overriding with
 a let. NFC

This treats nf consistently with LMul.
---
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 23 +++++++++++-----------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index bbb1e82fbadaa..5eb362156a644 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -713,12 +713,13 @@ foreach m = [1, 2, 4] in {
   }
 }
 
-class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
+class VReg<list<ValueType> regTypes, dag regList, int Vlmul, int nf = 1>
     : RISCVRegisterClass<regTypes,
                          64, // The maximum supported ELEN is 64.
                          regList> {
   let IsVRegClass = 1;
   let VLMul = Vlmul;
+  let NF = nf;
 }
 
 defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
@@ -799,17 +800,15 @@ class VTupRegList<int LMUL, int NF> {
 
 foreach m = LMULList in {
   foreach nf = NFList<m>.L in {
-    let NF = nf in {
-      def "VRN" # nf # "M" # m # "NoV0"
-        : VReg<VTupRegList<m, nf>.L,
-               (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
-               m>;
-      def "VRN" # nf # "M" # m
-        : VReg<VTupRegList<m, nf>.L,
-               (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
-                    !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
-               m>;
-    }
+    def "VRN" # nf # "M" # m # "NoV0"
+      : VReg<VTupRegList<m, nf>.L,
+             (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
+             m, nf>;
+    def "VRN" # nf # "M" # m
+      : VReg<VTupRegList<m, nf>.L,
+             (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"),
+                  !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
+             m, nf>;
   }
 }