[llvm] [RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (PR #131349)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> What architecture did you measure the dynamic IC on? I'm mostly interested in whether it had vector or not. I could see the presence of vector skewing results through interactions with our other heuristics (e.g. vector remat causing more scalar register pressure). Whichever you measured, might be a good idea to sanity check in the other. You don't need to repeat the whole matrix of tests, but maybe confirm the chosen point at least doesn't regress the other?

It had vector, but I do not see any diff related to vector while skimming benchmarks.

> Which CPU did you measure the performance (runtime) on? Is it in order? Or out of order? Does it have any kind of stack engine or ST/LD forwarding? I'm mostly just trying to understand how general this result might be. If this is e.g. a low end in-order, the perf impact might not carry over to other CPUs.

This was measured on our higher end out of order core (p470).

> What are the noise bands on your runtime measurements? Glancing at e.g. x264 which has basically no dynamic IC change, the runtime measurements look a lot like random noise. That's somewhat unavoidable when the impact is this small, but I want to have some clue which numbers I should be treating as having likely statistical significance.

> @lukel97 Might be good to queue this one on the BP3. Your setup does a decent job of pruning statistical false positives, and as above, it looks like that might be relevant here.

These numbers are mostly within our noise band. It would be great if @lukel97 could have a look! I did notice some cases where some CSR spills turned into non-csr moves (which is a win), which is why I wanted to look at runtime numbers.

https://github.com/llvm/llvm-project/pull/131349