[llvm] cd54d58 - [AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)

[via llvm-commits]

Author: Brox Chen
Date: 2025-03-14T12:31:57-04:00
New Revision: cd54d581b506accf10435778219b647313cb493d

URL: https://github.com/llvm/llvm-project/commit/cd54d581b506accf10435778219b647313cb493d
DIFF: https://github.com/llvm/llvm-project/commit/cd54d581b506accf10435778219b647313cb493d.diff

LOG: [AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)

add v_cndmask_t16 to hazardmask

Added: 
    llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir

Modified: 
    llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 582da42a0dc4e..aaefe27b1324f 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -2994,7 +2994,9 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
     switch (I.getOpcode()) {
     case AMDGPU::V_ADDC_U32_e32:
     case AMDGPU::V_ADDC_U32_dpp:
+    case AMDGPU::V_CNDMASK_B16_t16_e32:
     case AMDGPU::V_CNDMASK_B16_fake16_e32:
+    case AMDGPU::V_CNDMASK_B16_t16_dpp:
     case AMDGPU::V_CNDMASK_B16_fake16_dpp:
     case AMDGPU::V_CNDMASK_B32_e32:
     case AMDGPU::V_CNDMASK_B32_dpp:
@@ -3010,7 +3012,9 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
              HazardReg == AMDGPU::VCC_HI;
     case AMDGPU::V_ADDC_U32_e64:
     case AMDGPU::V_ADDC_U32_e64_dpp:
+    case AMDGPU::V_CNDMASK_B16_t16_e64:
     case AMDGPU::V_CNDMASK_B16_fake16_e64:
+    case AMDGPU::V_CNDMASK_B16_t16_e64_dpp:
     case AMDGPU::V_CNDMASK_B16_fake16_e64_dpp:
     case AMDGPU::V_CNDMASK_B32_e64:
     case AMDGPU::V_CNDMASK_B32_e64_dpp:

diff  --git a/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
new file mode 100644
index 0000000000000..9c8e0a48b114b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
@@ -0,0 +1,16 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefixes=GCN %s
+
+---
+name:            mask_hazard_cndmask_t16_dpp4
+body:            |
+  bb.0:
+    ; GCN-LABEL: name: mask_hazard_cndmask_t16_dpp4
+    ; GCN: $vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
+    ; GCN-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
+    ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
+    ; GCN-NEXT: S_ENDPGM 0
+    $vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
+    $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
+    S_ENDPGM 0
+...