[llvm] [RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (PR #131349)

[Philip Reames via llvm-commits]

preames wrote:

This seems generally reasonable, and well motivated.  A couple of questions:
1) What architecture did you measure the dynamic IC on?  I'm mostly interested in whether it had vector or not.  I could see the presence of vector skewing results through interactions with our other heuristics (e.g. vector remat causing more scalar register pressure).  Whichever you measured, might be a good idea to sanity check in the other.  You don't need to repeat the whole matrix of tests, but maybe confirm the chosen point at least doesn't regress the other?
2) Which CPU did you measure the performance (runtime) on?  Is it in order?  Or out of order?  Does it have any kind of stack engine or ST/LD forwarding?  I'm mostly just trying to understand how general this result might be.  If this is e.g. a low end in-order, the perf impact might not carry over to other CPUs.

https://github.com/llvm/llvm-project/pull/131349