[llvm] b936ef1 - [RISCV] Reorder include of RISCVInstrInfoZi* before C and Zc*. NFC (#131274)

[via llvm-commits]

Author: Craig Topper
Date: 2025-03-14T09:23:08-07:00
New Revision: b936ef18559aac8d982229040158c65843d43eb2

URL: https://github.com/llvm/llvm-project/commit/b936ef18559aac8d982229040158c65843d43eb2
DIFF: https://github.com/llvm/llvm-project/commit/b936ef18559aac8d982229040158c65843d43eb2.diff

LOG: [RISCV] Reorder include of RISCVInstrInfoZi* before C and Zc*. NFC (#131274)

Zclsd needs to reference Zilsd in CompressPats so put Zi before Zc.

The one issue I encountered is that RISCVInstrFormatsC.td needs to be
included before RISCVInstrInfoZicfiss. To fix this I moved the include
of RISCVInstrFormatsC.td from RISCVInstrInfoC.td to RISCVInstrInfo.td
where we include RISCVInstrFormats.td. I moved RISCVInstrFormatsV.td for
consistency.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index aab368680e814..11d93892ee7a5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -518,6 +518,8 @@ def LeadingOnesWMask : ImmLeaf<XLenVT, [{
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrFormats.td"
+include "RISCVInstrFormatsC.td"
+include "RISCVInstrFormatsV.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
@@ -2135,17 +2137,17 @@ include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZvk.td"
 
-// Compressed
-include "RISCVInstrInfoC.td"
-include "RISCVInstrInfoZc.td"
-include "RISCVInstrInfoZcmop.td"
-
 // Integer
 include "RISCVInstrInfoZimop.td"
 include "RISCVInstrInfoZicbo.td"
 include "RISCVInstrInfoZicond.td"
 include "RISCVInstrInfoZicfiss.td"
 
+// Compressed
+include "RISCVInstrInfoC.td"
+include "RISCVInstrInfoZc.td"
+include "RISCVInstrInfoZcmop.td"
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 0f320d2375ec2..41ed253f2f36d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -6,8 +6,6 @@
 //
 //===----------------------------------------------------------------------===//
 
-include "RISCVInstrFormatsC.td"
-
 //===----------------------------------------------------------------------===//
 // Operand definitions.
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 73345c92b0694..8e18736dc8ecb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -11,8 +11,6 @@
 ///
 //===----------------------------------------------------------------------===//
 
-include "RISCVInstrFormatsV.td"
-
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//