[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 14 09:11:40 PDT 2025
================
@@ -0,0 +1,1079 @@
+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+//
+// This version is still experimental as the 'P' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RVPGPRPairRV32 : RegisterOperand<GPRPair> {
+ let ParserMatchClass = GPRPairRV32Operand;
+ let EncoderMethod = "getRVPGPRPair";
+ let DecoderMethod = "decodeRVPGPRPair";
+}
+
+def simm10 : RISCVSImmLeafOp<10> {
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isInt<10>(Imm);
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnary<bits<5> funct5, bits<7> wuimm,
+ bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
+ : RVInstIBase<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let Inst{31-27} = funct5;
+ let Inst{26-20} = wuimm;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9<bits<7> funct7, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10:$simm10),
+ opcodestr, "$rd, $simm10"> {
+ bits<10> simm10;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = simm10;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9Rdp<bits<7> funct7, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+ (ins simm10:$simm10),
+ opcodestr, "$rdp, $simm10"> {
+ bits<10> simm10;
+ bits<4> rdp;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = simm10;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm8<bits<8> funct8, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins uimm8:$uimm8),
+ opcodestr, "$rd, $uimm8"> {
+ bits<8> uimm8;
+
+ let Inst{31-24} = funct8;
+ let Inst{23-16} = uimm8;
+ let Inst{15} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm8Rdp<bits<8> funct8, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+ (ins uimm8:$uimm8), opcodestr, "$rdp, $uimm8"> {
+ bits<8> uimm8;
+ bits<4> rdp;
+
+ let Inst{31-24} = funct8;
+ let Inst{23-16} = uimm8;
+ let Inst{15} = 0b0;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let Inst{31-27} = 0b11100;
+ let Inst{26-25} = w;
+ let Inst{24-20} = uf;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUFRs1pRdp<bits<2> w, bits<5> uf, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p), opcodestr, "$rdp, $rs1p"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{31-27} = 0b01100;
+ let Inst{26-25} = w;
+ let Inst{24-20} = uf;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = 0b0;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryF<bit bfr, bits<3> f, bit aft, bits<7> wuimm, string opcodestr,
+ bits<3> funct3, dag outs, dag ins, string argstr>
+ : RVInstIBase<funct3, OPC_OP_IMM_32, outs, ins, opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-28} = f;
+ let Inst{27} = aft;
+ let Inst{26-20} = wuimm;
+}
+
+class RVPUnary1F0<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<1, f, 0, wuimm, opcodestr, 0b100, (outs GPR:$rd),
+ (ins GPR:$rs1), "$rd, $rs1">;
+
+class RVPUnary0F0Rdp<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b010, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1), "$rdp, $rs1"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPUnary0F0Rs1p<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b100, (outs GPR:$rd),
+ (ins RVPGPRPairRV32:$rs1p), "$rd, $rs1p"> {
+ bits<4> rs1p;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = 0b1;
+}
+
+class RVPUnary0F0Rs1pRdp<bits<3> f, bits<7> wuimm, string opcodestr,
+ bit aft = 0b0>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b110, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p), "$rdp, $rs1p"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinaryFW<bit bfr, bits<3> f, bit aft, bits<2> w, bits<3> funct3,
+ string opcodestr, RISCVOpcode Opcode = OPC_OP_32,
+ dag outs = (outs GPR:$rd), dag ins = (ins GPR:$rs1, GPR:$rs2),
+ string argstr = "$rd, $rs1, $rs2">
+ : RVInstRBase<funct3, Opcode, outs, ins, opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-28} = f;
+ let Inst{27} = aft;
+ let Inst{26-25} = w;
+}
+
+class RVPBinary1F1W<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<1, f, 1, w, funct3, opcodestr, Opcode>;
+
+class RVPBinary1F0W<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr,
+ RISCVOpcode Opcode = OPC_OP_32>
+ : RVPBinaryFW<1, f, 0, w, funct3, opcodestr, Opcode>;
+
+class RVPBinary0F1WRdp<bits<3> f, bits<2> w, string opcodestr,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, 0b010, opcodestr, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1, GPR:$rs2), "$rdp, $rs1, $rs2"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPBinary0F1WRs1p<bits<3> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, 0b100, opcodestr, Opcode, (outs GPR:$rd),
+ (ins RVPGPRPairRV32:$rs1p, GPR:$rs2), "$rd, $rs1p, $rs2"> {
+ bits<4> rs1p;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+}
+
+class RVPBinary0F1WRs1pRdp<bits<3> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, 0b110, opcodestr, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, GPR:$rs2), "$rdp, $rs1p, $rs2"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinary1FWRs2pRs1pRdp<bits<4> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVInstRBase<0b110, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, RVPGPRPairRV32:$rs2p),
+ opcodestr, "$rdp, $rs1p, $rs2p"> {
+ bits<4> rs1p;
+ bits<4> rs2p;
+ bits<4> rdp;
+
+ let Inst{31} = 0b1;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+ let Inst{24-21} = rs2p;
+ let Inst{20} = aft;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPBinary1F0WRs2pRs1pRdp<bits<3> f, bits<2> w, string opcodestr,
+ bit bfr = 0b1, bit aft = 0b0,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<1, f, 0, w, 0b110, opcodestr, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, RVPGPRPairRV32:$rs2p), "$rdp, $rs1p, $rs2p"> {
+ bits<4> rs1p;
+ bits<4> rs2p;
+ bits<4> rdp;
+
+ let Inst{24-21} = rs2p;
+ let Inst{20} = bfr;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinaryLongFW<bit bfr = 1, bits<4> f, bits<2> w, bits<3> funct3,
+ string opcodestr, dag outs, dag ins, string argstr>
+ : RVInstRBase<funct3, OPC_OP_32, outs, ins,
+ opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+}
+
+class RVPBinary1LongFW<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
+ : RVPBinaryLongFW<1, f, w, funct3, opcodestr, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), "$rd, $rs1, $rs2">;
+
+class RVPBinary0LongFW<bits<4> f, bits<2> w, string opcodestr>
+ : RVPBinaryLongFW<0, f, w, 0b010, opcodestr, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1, RVPGPRPairRV32:$rs2), "$rdp, $rs1, $rs2"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b1;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtP] in {
+def CLS : RVPUnary<0b01100, 0b0000011, 0b001, OPC_OP_IMM, "cls">;
+def ABS : RVPUnary<0b01100, 0b0000111, 0b001, OPC_OP_IMM, "abs">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32] in
+def REV_RV32 : RVPUnary<0b01101, 0b0011111, 0b101, OPC_OP_IMM, "rev">;
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def REV16 : RVPUnary<0b01101, 0b0110000, 0b101, OPC_OP_IMM, "rev16">;
+def REV_RV64 : RVPUnary<0b01111, 0b0111111, 0b101, OPC_OP_IMM, "rev">;
+
+def CLSW : RVPUnary<0b01100, 0b0000011, 0b001, OPC_OP_IMM_32, "clsw">;
+def ABSW : RVPUnary<0b01100, 0b0000111, 0b001, OPC_OP_IMM_32, "absw">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+def PSLLI_B : RVPUnary<0b10000, 0b0001000, 0b010, OPC_OP_IMM_32, "pslli.b">;
+def PSLLI_H : RVPUnary<0b10000, 0b0010000, 0b010, OPC_OP_IMM_32, "pslli.h">;
+def PSSLAI_H : RVPUnary<0b11010, 0b0010000, 0b010, OPC_OP_IMM_32, "psslai.h">;
+} // Predicates = [HasStdExtP]
+let DecoderNamespace = "POverlap",
----------------
topperc wrote:
POverlap use RV32GPRPair32? Which we could rename to RISCV32Only_?
https://github.com/llvm/llvm-project/pull/123271
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